KR19980044251A - Structure of Chip Size Semiconductor Package and Manufacturing Method Thereof - Google Patents

Abstract

The present invention relates to a structure of a chip sized semiconductor package and a method of manufacturing the same, wherein the semiconductor chip has a plurality of input / output pads formed thereon, bumps formed on the input / output pads of the semiconductor chip, and are bonded to the inside of the input / output pad. A tape, a lead bonded to the tape and extending to the upper surface of the bump, the bump being electrically connected by a connecting means, a solder ball fused as an input / output means inside the lead, the tape, the lead and It is made of encapsulation means covering part of solder ball to make the size of the semiconductor chip and the package almost the same, maximizing the mounting density when mounting, and also exposing the semiconductor chip to the outside directly to improve the heat dissipation ability of the semiconductor chip. Chip can shorten wiring length by using flip chip technology Structure of sized semiconductor package and manufacturing method thereof.

Description

Structure of Chip Size Semiconductor Package and Manufacturing Method Thereof

The present invention relates to a structure of a chip size semiconductor package and a method of manufacturing the same. More specifically, the size of the semiconductor chip and the size of the package surrounding the semiconductor chip are manufactured to be substantially the same, and the mounting density thereof when the package is mounted on the main board. The chip size semiconductor package can maximize the heat dissipation ability of the semiconductor chip by exposing the semiconductor chip directly to the outside air and improve the performance of the semiconductor chip by shortening the wiring length by using the flip chip technology. It relates to a structure and a method of manufacturing the same.

In general, a semiconductor package protects a semiconductor chip such as a single device or an integrated circuit formed by stacking various electronic circuits and wirings from various external environments such as dust, moisture, electrical and mechanical loads, and optimizes and maximizes the performance of the semiconductor chip. In order to achieve this, the signal input / output terminals to the main board are formed using a lead frame and the like is sealed using a sealing means.

Such a conventional lead frame and a semiconductor package (Quad Flat Package type) using the same are shown in FIGS. 1A and 1B.

As shown in FIG. 1A, a conventional lead frame includes a semiconductor chip mounting plate 140 ′ on which a semiconductor chip is mounted, and a plurality of tie bars 110 ′ supporting and fixing the semiconductor chip mounting plate 140 ′. A plurality of internal leads 130 'connected by conductive wires from respective input / output pads, which are external terminals of the semiconductor chip, external leads 120' extending from the internal leads 130 ', and bent; It consists of a dam bar 150 'which borders the inner lead 130' and the outer lead 120 '.

In the conventional semiconductor package using the lead frame, as illustrated in FIG. 1B, a circuit chip and wirings of various electric and electronic devices are stacked and a plurality of input / output pads 240 ′ are formed on a surface thereof. ), A semiconductor chip mounting plate 140 'to which the semiconductor chip 210' is attached and fixed by an adhesive 145 ', and a tie bar 110' for supporting and fixing the semiconductor chip mounting plate 140 '. ), A plurality of internal leads 130 ′ connected by the conductive wire 230 ′ from an input / output pad 240 ′ that is an input / output terminal of the semiconductor chip 210 ′, and the semiconductor chip ( 210 '), the encapsulation means 220' surrounding the conductive wire 230 ', the inner lead 130', and extending from the inner lead 130 'to the outer surface of the encapsulation means 220' in four directions. It is composed of a plurality of external leads (120 ') which are positioned to come out and serve as an external connection terminal (pin).

However, such a conventional semiconductor package occupies a region in which the size of the semiconductor chip mounting plate 140 'is much larger than that of the semiconductor chip 210', and includes internal and external leads for drawing signals to the main board. 130 'and 120' are fabricated at a predetermined distance from the semiconductor chip mounting plate 140 ', and the external leads 120' of the semiconductor package are completely formed in two directions in the left and right sides of the semiconductor package or in four directions of the front, rear, left, and right sides of the semiconductor package. Since the semiconductor packages are protruded and formed on the main board, the semiconductor packages occupy a large area of the main board, thereby reducing the mounting density and reducing the design margin of the electrical patterns formed in the main board. There is a problem to reduce. That is, the size of the encapsulation means 220 'surrounding the semiconductor chip 210' and the size of the external lead 120 'protruding outward are much larger than the size of the semiconductor chip 210' itself. It takes up a lot of mounting space.

On the other hand, since the amount of encapsulation means 220 'surrounding the semiconductor chip 210' is relatively large compared to the size of the semiconductor chip 210 ', the heat dissipation capability of the semiconductor chip 210' is poor and thus the semiconductor chip 210 It is a cause of drastically reducing the electrical performance of '). In other words, the integration and design technology of the semiconductor chip 210 'have been developed and its electrical performance has been improved day by day, but the package surrounding the semiconductor chip 210' has hindered its electrical performance.

In addition, until the electrical signal is transmitted from the semiconductor chip to the main board, the wires pass through long wires such as the conductive wire 230 ', the inner lead 130', and the outer lead 120 '. If it is, the signal is delayed or reduced due to an increase in electrical resistance such as inductance, crosstalk, etc. generated in the wiring, and various electrical noises are easily penetrated, causing further reduction in electrical performance of the semiconductor chip.

Such a semiconductor package can meet the demand for increasing the integrated capacity of semiconductor chips required for ultra-small, ultra-thin electronic products or the advanced space industry. It is not there.

Accordingly, an object of the present invention is to make the size of the semiconductor chip and the size of the package surrounding the semiconductor chip almost the same to maximize the mounting density when mounted on the main board and to expose the semiconductor chip directly to the outside air SUMMARY OF THE INVENTION An object of the present invention is to provide a structure of a chip size semiconductor package and a method of manufacturing the same, which can significantly improve the performance of a semiconductor chip by improving the heat dissipation capability of the chip and shortening the wiring length by using flip chip technology.

1A and 1B are a plan view and a cross-sectional view illustrating a conventional general lead frame and a semiconductor package using the same.

2A and 2B are a cross-sectional view and a plan view showing a chip size semiconductor package according to the present invention.

3A to 3F are state diagrams illustrating a method for manufacturing a chip size semiconductor package according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: semiconductor chip 110: input / output pad (Pad)

120: Bump 200: Tape

300: Lead 310: Dent

400: Solder Ball 500: Sealing means

550: anisotropic conductive film

In order to achieve the above object, a structure of a chip size semiconductor package according to the present invention includes a semiconductor chip having a plurality of input / output pads formed on an integrated circuit and a surface thereof, bumps formed on each input / output pad of the semiconductor chip; A tape adhered to an upper surface of an input / output pad on the upper surface of the semiconductor chip, a lead adhered on the tape to the upper surface of the bump, the lead is radially positioned and electrically connected to the bump by a connecting means, and a lead on the tape. It is characterized by consisting of a solder ball fused as an input / output means, and sealing means wrapped around a portion of the tape, lead and solder ball.

Here, the bumps are formed of gold or solder, and the tape is a double-sided adhesive tape, and electrically insulating. In addition, a dent is formed inside the lead to which the solder balls are fused, the sealing means is an adhesive polyimide film, and the connecting means may achieve the object of the present invention by using an anisotropic conductive film.

In order to achieve the above object, a method of manufacturing a chip size semiconductor package according to the present invention includes a bump forming step of forming bumps on a plurality of input / output pads positioned on a surface of a semiconductor chip, and a bump inner region of the semiconductor chip. A tape bonding step of adhering the tape to the tape, a lead seating step of electrically connecting the radial lead to the bumps on the tape, and a cutting step of cutting the lead protruding outwardly on the semiconductor chip; A solder ball fusion step for fusion welding the solder ball on the inside, and the sealing step of wrapping a portion of the tape, lead and solder ball with sealing means.

Here, the lead seating step may be performed after first applying an anisotropic conductive film around the bumps, and the sealing step may be achieved by applying an adhesive polyimide solution.

Hereinafter, a structure and a manufacturing method of a chip size semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As follows.

2A and 2B are a cross-sectional view and a plan view showing a chip size semiconductor package according to the present invention.

First, as shown in the cross-sectional view of FIG. 2A, the structure of the chip size semiconductor package according to the present invention includes an integrated circuit having various electronic circuit elements and wirings stacked on a lower end thereof, and a plurality of input / output pads 110 on an upper surface thereof. A semiconductor chip 100 having a / Output Pad formed thereon, and each of the input / output pads 110 of the semiconductor chip 100 has a rounded hill shape formed using Au or solder. Bump 120 is located.

The upper surface of the semiconductor chip 100 is electrically insulated and adhesive inside the input / output pad 110, and double-sided tape is adhered to the height of the bump 120, and the tape 200 is again on the tape 200. A lead 300 extending to the upper surface of the bump 120 and electrically connected to the bump 120 by a connecting means is positioned.

In addition, a plurality of solder balls 400 are fused to the inside of the lead 300 on the tape 200 as a main board (not shown) input / output means, and the tape 200 and the lead 300 are connected to each other. And a portion of the solder ball 400 has a structure in which the encapsulation means 500 is wrapped.

Here, the bump 120 serves as a means for connecting the input / output pad 110 of the semiconductor chip 100 to the lead 300 of the semiconductor package. The bump 120 has a shorter distance than the conventional conductive wire bonding. Since the connection between the lead 120 and the lead 300 can be performed within a short time, it is mainly used recently. In addition, pure gold is the best as the material, and can also be carried out using a conventional solder or the like.

On the other hand, the connecting means of the bump 120 and the lead 300 is a thermocompression bonding or anisotropic conductive film (550, ACF; Anisotropic Conductive) mainly used in flip chip technology as is widely known Film) can be used.

In addition, a dent 310 (Dent) is formed inside the lead 300 to which the solder ball 400 is fused as a chemical etching or stamping method. The dent 310 of the lead 300 increases the adhesion area with the solder ball 400 to increase the fusion strength, and also in each dent 310 by the surface tension during the high temperature solder fusion process. By using a round gathering property to serve to prevent the short between the solder ball 400.

The encapsulation means 500 surrounding the tape 200, the lead 300, and the solder ball 400 is made of a polyimide film having excellent adhesion.

In order to explain this in more detail, referring to the plan view of the chip size semiconductor package shown in FIG. 2B, a plurality of input / output pads 110 are formed at a rectangular periphery of the semiconductor chip 100, and the lead 300 is formed on an upper surface thereof. ) Is located and the solder ball 400 is fused to the inside of the lead 300 is used as the input / output means of the semiconductor chip 100. Here, the solder ball 400 may be formed in an array form by bending the shape of the lead 300 in various ways, and the input / output pads 110 and bumps indicated by dotted lines. 120 is not actually visible because it is hidden by the lid 300, for convenience, the sealing means 500 is removed and shown.

As can be seen from the above structure, according to the chip size semiconductor package according to the present invention, the bump 120 and the lead until a signal is transmitted from the input / output pad 110 of the semiconductor chip 100 to the main board. By passing through the 300 and the solder ball 400 will be seen that the overall wiring length is shortened compared to the prior art. In addition, since the polyimide film used as the encapsulation means 500 is applied only to the upper surface of the semiconductor chip 100, the size of the semiconductor chip 100 and the package size are almost the same, and most of the semiconductor chip 100 is used. It can be seen that the heat release ability is excellent as the structure directly exposed to the air.

3A to 3F are state diagrams illustrating a method of manufacturing a chip size semiconductor package according to the present invention.

1. bump formation step; The bumps 120 are formed on the plurality of input / output pads 110 positioned on the surface of the semiconductor chip 100 using gold or solder.

2. tape bonding step; The double-sided tape having excellent adhesiveness and electrical insulation is adhered to the inner region of the bump 120 of the semiconductor chip 100.

3. Lead seating step; On the tape 200, the leads 300 having a plurality of dents 310 formed thereon in an array form are radially extended to the bumps 120, and aligned with the bumps 120 to be electrically connected by the connecting means. Let's do it.

4. cutting step; The lead 300 protruding outward on the semiconductor chip 100 is cut.

5. solder ball fusion step; The solder balls 400 are placed on the plurality of dents 310 formed in an array form inside the leads 300 and fused at high temperatures.

6. encapsulation step; A portion of the tape 200, the lead 300, and the solder ball 400 are applied using a sealing means 500 such as an adhesive polyimide solution.

Here, the connecting means for electrically connecting the bump 120 and the lead 300 is a flip chip technology, by reflowing the bump 120 in a furnace (furnace), or anisotropic conductive film 550 It is carried out using), which will be described in detail as follows.

After bonding the gold or solder to the input / output pad 110 of the semiconductor chip 100 using thermal bonding bonding or ultrasonic bonding to form a bump 120, the positions of the leads 300 and the bumps 120 may be adjusted. After aligning correctly, the furnace is heated up to a predetermined temperature to reflow the bump 120 into the lead 300, or an adhesive method using an anisotropic conductive film 550, which is frequently used recently.

Here, the anisotropic conductive film 550 is a mixture of a general adhesive film and conductive metal grains. The thickness of the adhesive film is about 50 μm and the diameter of the conductive metal grains is about 5 μm. In addition, the surface of the conductive metal grains are coated with a thin polymer (Polymer), and when heat or pressure is applied to a predetermined region of the anisotropic conductive film 550, the polymer surrounding the conductive metal grains of the portion is melted and the conductive Since the metal grains are connected to each other to become conductive and the other parts have a characteristic of maintaining a certain insulating property, it is easy to adjust the alignment position of the objects to be bonded to each other. Accordingly, the anisotropic conductive film 550 is a material that is commercially available for outer lead bonding (OLB) or chip on glass (COG) of tape automated bonding (TAB). When the flip chip technology and the anisotropic conductive film 550 having the above characteristics are used for the electrical bonding between the bump 120 and the lead 300 formed on the input / output pad 110 of the semiconductor chip 100, After adhering the anisotropic conductive film 550 around the bumps 120 formed on the output pad 110, align the positions of the leads 300 and the bumps 120, and then press down the leads 300 as they are. When the compression is applied, the input / output pad 110 and the lead 300 are electrically bonded to each other.

Meanwhile, in the solder ball fusion step, the solder ball 400 is placed on the dent 310 formed inside the lead 300, and the solder ball 400 can be easily fused by reflow at a high temperature. Encapsulation is carried out by applying an adhesive polyimide solution or the like to dry the remaining portions except the solder balls 400 serving as the input / output means of the tape 200, the leads 300, and the solder balls 400. will be.

Although the present invention has been described only in the above-described embodiments, various modifications and changes may be made without departing from the scope and spirit of the present invention.

Accordingly, the present invention provides a semiconductor chip including a plurality of input / output pads formed on an integrated circuit and a surface thereof, a bump formed on each input / output pad of the semiconductor chip, and an inner side of the input / output pad of the upper surface of the semiconductor chip. A tape, a lead bonded onto the tape and radially extending to the bump top surface, the bump being electrically connected by a connecting means, a solder ball to be fused as an input / output means inside the lead on the tape, and the tape And a sealing means covering a part of the lead and the solder ball, so that the size of the semiconductor chip and the size of the package surrounding the semiconductor chip are made almost the same to maximize the mounting density when mounting on the main board. Direct exposure to outside air improves the heat dissipation capability of the semiconductor chip and utilizes flip chip technology. It is to provide a structure of a chip size semiconductor package and a method of manufacturing the same, which can shorten the wiring length and the like, thereby greatly improving the performance of the semiconductor chip.

Claims (10)

A semiconductor chip having a plurality of input / output pads formed on an integrated circuit and a surface thereof, a bump formed on each input / output pad of the semiconductor chip, a tape bonded into an input / output pad of an upper surface of the semiconductor chip, and the tape A lead bonded to and positioned radially to the top of the bump and electrically connected to the bump by a connecting means, a solder ball fused as an input / output means inside the lead on the tape, the tape, lead and solder ball The structure of the chip size semiconductor package, characterized in that consisting of a sealing means wrapped around. The structure of a chip size semiconductor package according to claim 1, wherein the bump is formed of one of gold and solder. The structure of a chip size semiconductor package according to claim 1, wherein the tape is a double-sided adhesive tape. The structure of a chip size semiconductor package according to any one of claims 1 to 3, wherein the tape is electrically insulating. The structure of the chip size semiconductor package according to claim 1, wherein a dent is formed inside the lead to which the solder ball is fused. The structure of a chip size semiconductor package according to claim 1, wherein the sealing means is an adhesive polyimide film. The structure of a chip size semiconductor package according to claim 1, wherein the connecting means is an anisotropic conductive film. A bump forming step of forming bumps on a plurality of input / output pads located on the surface of the semiconductor chip, a tape bonding step of adhering the tape to the bump inner region of the semiconductor chip, and bumping radial leads on the tape; A lead seating step of electrically connecting and bonding, a cutting step of cutting a lead protruding outward on the semiconductor chip, a solder ball fusion step of fusion of a solder ball inside the lead, and the tape, lead and solder ball Method for manufacturing a chip size semiconductor package, characterized in that it comprises a step of encapsulating a portion of the sealing means. The method of claim 8, wherein the lead seating step is performed after applying an anisotropic conductive film around the bumps. The method of claim 8, wherein the encapsulating is performed by applying an adhesive polyimide solution.