KR19980044238A - Ball Grid Array (BGA) Semiconductor Package - Google Patents
Ball Grid Array (BGA) Semiconductor Package Download PDFInfo
- Publication number
- KR19980044238A KR19980044238A KR1019960062300A KR19960062300A KR19980044238A KR 19980044238 A KR19980044238 A KR 19980044238A KR 1019960062300 A KR1019960062300 A KR 1019960062300A KR 19960062300 A KR19960062300 A KR 19960062300A KR 19980044238 A KR19980044238 A KR 19980044238A
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- South Korea
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- semiconductor package
- bga
- circuit
- semiconductor chip
- circuit board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 발명은 BGA(Ball Grid Array) 반도체 패키지에 관한 것으로, 중앙부에는 구리(Cu)가 부착되고, 상.하면에는 각각 제1, 2 회로패턴이 형성되어 관통홀에 의해 서로 연결되며, 이 제1, 2 회로패턴을 보호하기 위해 제1, 2 솔더마스크가 코팅된 회로기판과, 상기의 회로기판에 부착된 구리의 상. 하면에 각각 부착된 제1, 2 반도체칩과, 상기 제1 반도체칩과 제1 회로패턴 및 제2 반도체칩과 제2 회로패턴을 각각 전기적으로 연결하여 신호를 전달하는 와이어와, 상기의 제1, 2 회로패턴에 연결되어 외부로 신호를 전달할 수 있도록 회로기판의 일면에 융착된 솔더볼과, 상기의 제1, 2 반도체칩과 그 외 주변 구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 회로기판의 상. 하면 중심부에 몰딩된 제1, 2 수지봉지재로 이루어진 것으로, 반도체 패키지의 용량을 확대하고, 실장밀도를 높이며, 고집적화 및 고성능화한 것이다.The present invention relates to a ball grid array (BGA) semiconductor package, wherein copper (Cu) is attached to a central portion, and first and second circuit patterns are formed on upper and lower surfaces, respectively, and are connected to each other by through holes. A circuit board coated with first and second solder masks to protect the two circuit patterns, and an image of copper attached to the circuit board. First and second semiconductor chips attached to the lower surface, wires for transmitting signals by electrically connecting the first semiconductor chip and the first circuit pattern, and the second semiconductor chip and the second circuit pattern, respectively, and the first And solder balls fused to one surface of the circuit board so as to be connected to two circuit patterns to transmit signals to the outside, and to protect the first and second semiconductor chips and other peripheral components from external oxidation and corrosion. Prize. It consists of the first and second resin encapsulation material molded in the center of the lower surface, to increase the capacity of the semiconductor package, to increase the mounting density, and to achieve high integration and high performance.
Description
본 발명은 BGA(Ball Grid Array ; 볼 그리드 어레이) 반도체 패키지에 관한 것으로, 더욱 상세하게는 BGA 반도체 패키지의 내부에 두개의 반도체칩을 각각 부착하여 반도체 패키지의 용량을 확대함은 물론, 실장밀도를 높이고, 반도체 패키지를 고집적화 및 고성능화 할 수 있는 BGA 반도체 패키지에 관한 것이다.The present invention relates to a ball grid array (BGA) semiconductor package, and more particularly, two semiconductor chips are attached to the inside of the BGA semiconductor package to expand the capacity of the semiconductor package and to increase the mounting density. The present invention relates to a BGA semiconductor package capable of increasing the integration and high performance of a semiconductor package.
최근에 다핀화의 추세에 따른 기술적 요구를 해결하기 위해서 등장한 BGA 반도체 패키지는 입출력 수단으로서 반도체 패키지의 일면에 솔더볼을 융착하여 이를 입출력 수단으로 사용함으로서 많은 수의 입출력 신호를 수용할 수 있음은 물론, 그 크기도 작게 형성된 것이다.Recently, BGA semiconductor package, which appeared to solve the technical requirements according to the trend of multi-pinning, is used as an input / output means by soldering solder balls to one surface of the semiconductor package and using it as an input / output means, as well as receiving a large number of input / output signals. Its size is also small.
이러한 BGA 반도체 패키지의 구성은 도 1에 도시된 바와 같이 표면에 회로패턴(2')이 형성되고, 이 회로패턴(2')을 보호하기 위해 솔더마스크(2)가 코팅된 회로기판(2)과, 상기 회로기판(2)의 일면 중앙에 부착된 반도체칩(1)과, 상기 반도체칩(1)과 상기 회로기판(2)의 회로패턴(2')을 전기적으로 연결하여 신호를 전달하는 와이어(3)와, 상기 회로기판(2)의 회로패턴(2')과 연결되어 외부로 신호를 전달할 수 있도록 회로기판(2)의 일면에 융착된 솔더볼(4)과, 상기 반도체칩(1)과 그 외주변 구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 수지봉지재(5)로 구성되는 것이다.As shown in FIG. 1, the BGA semiconductor package has a circuit pattern 2 ′ formed on its surface, and a circuit board 2 coated with a solder mask 2 to protect the circuit pattern 2 ′. And electrically connect the semiconductor chip 1 attached to the center of one surface of the circuit board 2 and the circuit pattern 2 'of the semiconductor chip 1 and the circuit board 2 to transmit a signal. A solder ball 4 fused to one surface of the circuit board 2 so as to be connected to the wire 3, the circuit pattern 2 ′ of the circuit board 2, and to transmit a signal to the outside, and the semiconductor chip 1. ) And its outer periphery components are composed of a resin encapsulant (5) wrapped around the outside to protect it from external oxidation and corrosion.
그러나, 이러한 BGA 반도체 패키지는 내부에 하나의 반도체칩(1)이 부착되어 있어 반도체 패키지의 용량을 확대하기 위해서는 하나 이상의 BGA 반도체 패키지를 마더보드에 실장하여야 그 용량을 확대시킬 수 있는데, 이와 같이 하나 이상의 BGA 반도체 패키지를 마더보드에 실장 할 경우에는 마더보드의 표면에 각각 실장하여야 됨으로서 실장면적이 커지게 되고, 이는 소형화 추세에 역행하는 결과를 가져오는 문제점이 있었던 것이다.However, such a BGA semiconductor package has one semiconductor chip 1 attached therein, and thus, in order to increase the capacity of the semiconductor package, at least one BGA semiconductor package must be mounted on the motherboard to increase its capacity. When the above-described BGA semiconductor package is mounted on the motherboard, the mounting area is increased by mounting each on the surface of the motherboard, which has a problem that results in a miniaturization trend.
본 발명의 목적은 이와 같은 문제점을 해결하기 위하여 발명된 것으로서, BGA 반도체 패키지의 내부에 두개의 반도체칩을 부착함으로서 반도체 패키지의 용량을 확대하고, 실장밀도를 높이며, 반도체 패키지를 고집적화 및 고성능화 할 수 있는 BGA 반도체 패키지를 제공함에 있다.An object of the present invention is to solve the above problems, by attaching two semiconductor chips to the inside of the BGA semiconductor package, it is possible to increase the capacity of the semiconductor package, increase the mounting density, high integration and high performance of the semiconductor package To provide a BGA semiconductor package.
도 1은 일반적인 BGA 반도체 패키지의 구조를 나타낸 단면도1 is a cross-sectional view showing the structure of a typical BGA semiconductor package
도 2는 본 발명에 따른 BGA 반도체 패키지의 구성을 나타낸 단면도Figure 2 is a cross-sectional view showing the configuration of the BGA semiconductor package according to the present invention
도 3은 본 발명의 실시예에 따른 BGA 반도체 패키지를 나타낸 단면도3 is a cross-sectional view illustrating a BGA semiconductor package according to an embodiment of the present invention.
도 4은 본 발명에 따른 회로기판의 요부를 도시한 도면4 is a view illustrating main parts of a circuit board according to the present invention;
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10a,10b : 제1, 2 반도체칩20 : 회로기판10a, 10b: first and second semiconductor chip 20: circuit board
21a,21b : 제1, 2 회로패턴22a,22b : 제1, 2 솔더마스크21a and 21b: First and second circuit patterns 22a and 22b: First and second solder masks
23 : 관통홀24 : 구리(Cu)23 through hole 24 copper (Cu)
30 : 와이어40 : 솔더볼30: wire 40: solder ball
50a,50b : 제1, 2 수지봉지재50a, 50b: First and second resin encapsulant
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 BGA 반도체 패키지의 구성을 나타낸 단면도로서, 그 구조는 중앙부에는 구리(24 ; Cu)가 부착되고, 상. 하면에는 각각 제1 회로패턴(21a) 및 제2 회로패턴(21b)이 형성되어 관통홀(23 ; Through Hole)에 의해 서로 연결되며, 이 제1, 2 회로패턴(21a)(21b)을 보호하기 위해 제1 솔더마스크(22a) 및 제2 솔더마스크(22b)가 코팅된 회로기판(20)과, 상기의 회로기판(20)에 부착된 구리(24)의 상. 하면에 각각 부착된 제1 반도체칩(10a) 및 제2 반도체칩(10b)과, 상기 제1 반도체칩(10a)과 제1 회로패턴(21a) 및 제2 반도체칩(10b)과 제2 회로패턴(21b)을 각각 전기적으로 연결하여 신호를 전달하는 와이어(30)와, 상기의 제1, 2 회로패턴(21a)(21b)에 연결되어 외부로 신호를 전달하는 솔더볼(40)과, 상기의 제1 반도체칩(10a) 및 제2 반도체칩(10b)과 그 외 주변 구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 회로기판(20)의 상. 하면 중심부에 몰딩된 제1 수지봉지재(50a) 및 제2 수지봉지재(50b)로 이루어지는 것을 특징으로 하는 BGA 반도체 패키지이다.2 is a cross-sectional view showing a configuration of a BGA semiconductor package according to the present invention, in which a copper (24; Cu) is attached to a central portion thereof. A first circuit pattern 21a and a second circuit pattern 21b are formed on the lower surface thereof, respectively, and are connected to each other by a through hole 23 to protect the first and second circuit patterns 21a and 21b. The circuit board 20 coated with the first solder mask 22a and the second solder mask 22b and the copper 24 attached to the circuit board 20 for the purpose. The first semiconductor chip 10a and the second semiconductor chip 10b attached to the lower surface, respectively, the first semiconductor chip 10a, the first circuit pattern 21a, the second semiconductor chip 10b, and the second circuit. A wire 30 electrically connecting the patterns 21b to each other to transfer signals, a solder ball 40 connected to the first and second circuit patterns 21a and 21b to transfer signals to the outside, and the On the circuit board 20 to protect the first semiconductor chip 10a and the second semiconductor chip 10b and other peripheral components thereof from external oxidation and corrosion. A BGA semiconductor package comprising a first resin encapsulating material 50a and a second resin encapsulating material 50b molded in a lower surface center.
상기의 솔더볼(40)은 회로기판(20)의 일면에만 융착될 수 있고, 필요에 따라 회로기판(20)의 양면에 각각 솔더볼(40)을 융착시킬 수 있을 뿐 아니라, 상기의 솔더볼(40)은 회로기판(20)의 일면에 융착되고, 그 반대면에는 랜드(41)가 형성되어 다수의 반도체 패키지를 적층시킬 수 있는 것이다. 즉, BGA 반도체 패키지의 하면으로는 솔더볼(40)이 융착되고, BGA 반도체 패키지의 상면으로 랜드(41)가 형성될 수 있는 것이다. 또한, 도 4에 도시된 바와 같이 상기 제1, 2 회로패턴(21a)(21b)에 와이어(30)가 본딩되는 에리어(Area) 부위에는 본딩을 용이하게 하기 위하여 니켈(Ni), 은(Ag), 금(Au) 또는 합금(Alloy)을 플레이팅(Plating)하는 것이다.The solder ball 40 may be fused to only one surface of the circuit board 20, and the solder ball 40 may be fused to both surfaces of the circuit board 20 as necessary, as well as the solder ball 40. The silver is fused to one surface of the circuit board 20, and the land 41 is formed on the opposite surface thereof to stack a plurality of semiconductor packages. That is, the solder ball 40 may be fused to the lower surface of the BGA semiconductor package, and the lands 41 may be formed on the upper surface of the BGA semiconductor package. In addition, as shown in FIG. 4, nickel (Ni) and silver (Ag) are used to facilitate bonding at an area where the wire 30 is bonded to the first and second circuit patterns 21a and 21b. ), Plating gold (Au) or alloy (Alloy).
이와 같이 구성된 본 발명의 BGA 반도체 패키지는 내부에 제1 반도체칩(10a)과 제2 반도체칩(10b)을 부착시켜 용량을 확대한 것으로, 대 용량을 요구하는 장비에 실장시에 매우 유용하다. 즉, 상기 BGA 반도체 패키지를 마더보드에 실장하면 두개의 BGA 반도체 패키지를 실장한 결과를 얻음으로서 용량을 확대할 수 있는 것으로 실장면적을 줄일 수 있는 것이다.The BGA semiconductor package of the present invention configured as described above has an enlarged capacity by attaching the first semiconductor chip 10a and the second semiconductor chip 10b therein, and is very useful for mounting in equipment requiring a large capacity. In other words, when the BGA semiconductor package is mounted on a motherboard, the result of mounting two BGA semiconductor packages is obtained, thereby increasing the capacity, thereby reducing the mounting area.
이상의 설명에서와 같이 본 발명에 따른 BGA 반도체 패키지는 내부에 두개의 반도체칩을 부착함으로서 반도체 패키지의 용량을 확대하고, 실장밀도를 높이며, 반도체 패키지를 고집적화 및 고성능화 할 수 있는 효과가 있다.As described above, the BGA semiconductor package according to the present invention has an effect of increasing the capacity of the semiconductor package, increasing the mounting density, and increasing the integration and performance of the semiconductor package by attaching two semiconductor chips therein.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960062300A KR100225236B1 (en) | 1996-12-06 | 1996-12-06 | Bga semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960062300A KR100225236B1 (en) | 1996-12-06 | 1996-12-06 | Bga semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980044238A true KR19980044238A (en) | 1998-09-05 |
| KR100225236B1 KR100225236B1 (en) | 1999-10-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960062300A KR100225236B1 (en) | 1996-12-06 | 1996-12-06 | Bga semiconductor package |
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| Country | Link |
|---|---|
| KR (1) | KR100225236B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100549312B1 (en) * | 2000-10-10 | 2006-02-02 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04144270A (en) * | 1990-10-05 | 1992-05-18 | Nec Corp | Integrated circuit case |
-
1996
- 1996-12-06 KR KR1019960062300A patent/KR100225236B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100549312B1 (en) * | 2000-10-10 | 2006-02-02 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
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| Publication number | Publication date |
|---|---|
| KR100225236B1 (en) | 1999-10-15 |
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