KR19980032378U - Data transfer device between time switch and link controller in switching system - Google Patents

Abstract

The present invention relates to a switching system, and a data transmission apparatus for transmitting a large amount of data in a short time when transmitting data between the time switch and the link controller in the switching system.

In the conventional data transmission apparatus, when the data from the time switch is transmitted to the link controller, data is transmitted through a single time slot. Therefore, when a large amount of data is transmitted to the link controller, it takes a lot of time. There is a problem that reduces the performance of.

When the data is transmitted between the time switch and the link controller in the switching system, the data is transmitted through a plurality of timeslots, thereby improving the performance of the switching system.

Description

Data transfer device between time switch and link controller in switching system

The present invention relates to a switching system, and more particularly, to a data transmission device for transmitting a large amount of data in a short time when transmitting data between the time switch and the link controller in the switching system.

In general, an exchange system performs an operation of exchanging data between a time switch and a link controller. Thus, a conventional data transmission apparatus for transmitting data between the time switch and the link controller is configured as shown in FIG.

In FIG. 1, when the time switch 1 outputs data at 2 Mbps and outputs a clock of 4 MHz, the data and clock are received by the rate matching section 2, and the rate matching section 2 outputs the data. It converts at 64Kbps speed and transmits 64Khz clock to link controller 3 side, and link controller 3 transfers 64Kbps data applied from rate matching section 2 to 64Khz. It is received in accordance with the clock and recorded in the memory section 4. At this time, the CPU 5 accesses the memory unit 4, reads data, and performs a call processing operation in accordance with a program. When the CPU 5 has data to transmit, the data is recorded in the memory section 4, and the link controller 3 reads the data recorded in the memory section 4 and matches the rate at a speed of 64 Kbps. The rate matching section 2 receives 64 Kbps of data from the link controller 3 and transmits the data to the time switch 1 side at a rate of 2 Mbps.

In the conventional data transmission apparatus as described above, when the data from the time switch 1 is transmitted to the link controller 3 side, a single time slot among the plurality of time slots T1 to T32 as shown in FIG. Since the data is transmitted through the link controller 3, a large amount of time is required to transmit the data to the link controller 3, thereby degrading the performance of the exchange system.

The present invention has been made to solve the above problems, and when the data transfer between the time switch and the link controller in the exchange system to transmit a large amount of data in a short time by transmitting data through a plurality of timeslots An object is to provide a data transmission device.

A feature of the present invention for achieving the above object is a time switch for transmitting data while performing a switching operation; A data transfer device between a time switch and a link controller in a switching system including a link controller that receives data, outputs the data to a CPU side through a memory unit, and transmits data applied from the CPU to the CPU side, the data applied from the time switch. A multiplexer / demultiplexer for demultiplexing the corresponding data upon transmission to the link controller and multiplexing the corresponding data to the time switch when receiving the data applied from the link controller; A time slot counter configured to receive a frame synchronization signal and a clock supplied from the time switch and output a plurality of time slot designation signals; A time slot for transmitting the clock generated by the time slot designation signal from the timeslot counter and the clock from the time switch to the link controller and a time slot selection signal to the link controller. It has a decoder.

The present invention, when transmitting data between the time switch and the link controller in the exchange system transmits the data through a plurality of timeslots to transmit a large amount of data in a short time to improve the performance of the exchange system.

1 is a block diagram of a data transmission device between a time switch and a link controller in a conventional switching system.

Fig. 2 is a diagram showing the operation of the data transmission device shown in Fig. 1;

3 is a block diagram of a data transmission device between a time switch and a link controller in an exchange system according to the present invention;

4 is a view showing the operation of the data transmission device shown in FIG.

FIG. 5 is a detailed configuration diagram of the timeslot counter shown in FIG.

6 to 9 are circuit diagrams showing an example of the configuration of the timeslot decoder shown in FIG.

Explanation of symbols on the main parts of the drawings

10: time switch 20: multiplexing / demultiplexing unit

30: timeslot decoder 40: timeslot counter

50: link controller 60: memory unit

70: CPU

In the switching system according to the present invention, a data transmission device between a time switch and a link controller includes a multiplexing / demultiplexing unit 20, a timeslot decoder 30, and a timeslot counter 40 as shown in FIG. Lose. When the multiplexer / demultiplexer 20 receives data applied from the time switch 10, the multiplexer / demultiplexer 20 demultiplexes the corresponding data and transmits the data to the link controller 50, and receives the data applied from the link controller 50. The data is multiplexed and transmitted to the time switch 10 side. The timeslot counter 40 operates by receiving the frame synchronization signal FS and the clock CLK1 supplied from the time switch 10 to output a plurality of timeslot designation signals to the timeslot decoder 30. The timeslot decoder 30 operates the clock CLK2 generated by operating in accordance with the timeslot designation signal from the timeslot counter 40 and the clock CLK1 from the time switch 10. The time slot selection signal TSS is transmitted to the link controller 50 at the same time.

That is, in the present invention, when data from the time switch 10 is transmitted to the link controller 50, the data is transmitted to a plurality of timeslots as shown in FIG. 4, and the link controller 50 is multiplexed / When receiving the data applied from the demultiplexer 20, the data of each timeslot is received from the timeslot decoder 30 based on the clock CLK2 and the tine slot select signal TSS. In addition, when data is transmitted and received between the CPU 70 and the link controller 50, data is transmitted and received via the memory unit 60.

On the other hand, the timeslot counter 40 is provided with a divider 41, a flip-flop 45 and a plurality of inverters IN1 to IN6 as shown in FIG. The division unit 41 includes a plurality of counters 43 and 44, which are generated by division operation according to the clock synchronization signal FS of 8 Khz and the clock CLK1 of 4Mhz applied from the time switch 10. A plurality of timeslot designation signals n1 to n4 are outputted to the timeslot decoder 30 side. In the flip-flop 45, the data input terminals J and K and the preset terminal PRN are connected to the power supply Vcc, and the clock is clocked inverted through the first inverter IN1 from the division unit 41. And the frame synchronization signal FS is applied to the clear terminal CLRN from the time switch unit 10 to operate the time slot designation signal n5 to the time slot decoder 30 through the output terminal Q. The second inverter IN2 supplies the time slot designation signal p5, which is obtained by inverting the time slot designation signal n5 applied from the output terminal Q of the flip-flop 45, to the time slot decoder 30. Output Further, the third inverter IN3 outputs the timeslot designation signal p1, which is obtained by inverting the timeslot designation signal n1 applied from the frequency divider 41, to the timeslot decoder 30, and the fourth inverter. IN4 outputs the timeslot designation signal p2, which is made by inverting the timeslot designation signal n2 applied from the frequency divider 41, to the timeslot decoder 30, and the fifth inverter IN5 is divided into minutes. The time slot designation signal p3 generated by inverting the time slot designation signal n3 applied from the main part 41 is outputted to the time slot decoder 30, and the sixth inverter IN6 is supplied from the frequency division part 41. The time slot designation signal p4, which is made by inverting the applied time slot designation signal n4, is output to the time slot decoder 30 side.

In addition, the timeslot decoder 30 can be implemented in various ways according to the number of bits of data carried in each timeslot. When sending 8 bits of data in one timeslot, the time as shown in FIG. When a slot decoder is used and 16 bits of data are sent in one timeslot, a time slot decoder as shown in FIG. 7 is used, and when 32 bits of data are sent in one timeslot, it is shown in FIG. A time slot decoder as shown in FIG. 9 is used, and a time slot decoder as shown in FIG. 9 is used when 64 bits of data are sent to one time slot.

The timeslot decoder shown in FIG. 6 is connected to the first to fourth AND gates AND1 to AND4 and the flip-flop FF1. The first AND gate AND1 receives the timeslot designation signals n4 and p4 from the timeslot counter 40 as the input signal i4 and receives the timeslot designation signal n3 from the timeslot counter 40. , p3) is applied as an input signal i3 to output a signal generated by logical multiplication to the third AND gate AND3, and the second AND gate AND2 designates the timeslot from the timeslot counter 40. A signal generated by applying the signals n2 and p2 as the input signal i2 and receiving the timeslot designation signals n1 and p1 from the timeslot counter 40 as the input signal i1 Output to the AND gate AND3 side. In addition, the third AND gate AND3 performs an AND operation on the signals applied from the first and second AND gates AND1 and 2 and outputs the result to the fourth AND gate AND4, and the fourth AND gate AND4 is timed. Links the timeslot selection signal generated by applying the timeslot designation signals n5 and p5 from the slot counter 40 as the input signal i5 and the AND of the third AND gate AND3. Output to the controller 50 side. In the flip-flop FF1, the preset terminal PRN and the clear terminal CLRN are connected to the power supply Vcc, and the timeslot selection signal from the fourth AND gate AND4 is applied to the data input terminal D. The clock switch CLK1 of 4Mhz is applied to the clock terminal from the time switch 10 to output an 8-bit clock to the link controller 50 through the output terminal Q.

The timeslot decoder shown in FIG. 7 is connected to the fifth to seventh gates AND5 to AND7 and the flip-flop FF2. The fifth AND gate AND5 receives the timeslot designation signals n5 and p5 from the timeslot counter 40 as the input signal i5 and receives the timeslot designation signal n4 from the timeslot counter 40. , p4 is applied as an input signal i4 to output a signal generated by AND multiplication to the seventh AND gate AND7 side, and the sixth AND gate AND6 designates the timeslot from the timeslot counter 40. The signal generated by applying the signals n3 and p3 as the input signal i3 and receiving the timeslot designation signals n2 and p2 from the timeslot counter 40 as the input signal i2 is logically multiplied. Output to the AND gate AND7 side. In addition, the seventh AND gate AND7 outputs the timeslot selection signal generated by ANDing the signals applied from the fifth and sixth AND gates AND5 and 6 to the link controller 50. In the flip-flop FF2, the preset terminal PRN and the clear terminal CLRN are connected to the power supply Vcc, and the timeslot selection signal from the seventh AND gate AND7 is applied to the data input terminal D. 4Mhz clock CLK1 is applied to the clock terminal from the time switch 10 to output a 16-bit clock to the link controller 50 through the output terminal Q.

The timeslot decoder shown in FIG. 8 is connected to eighth and ninth AND gates AND8 and AND9 and a flip-flop FF3. The eighth AND gate AND8 receives the timeslot designation signals n4 and p4 from the timeslot counter 40 as the input signal i4 and receives the timeslot designation signal n3 from the timeslot counter 40. , p3) is applied as an input signal i3 to output a signal generated by AND multiplication to the ninth AND gate AND9 side, and the ninth AND gate AND9 designates the timeslot from the timeslot counter 40. The signals n5 and p5 are applied as the input signal i5, and the signals from the eighth AND gate AND8 are applied to be ANDed to output the time slot selection signal generated by the link controller 50. In the flip-flop FF3, the preset terminal PRN and the clear terminal CLRN are connected to the power supply Vcc, and the timeslot selection signal from the ninth end gate AND9 is applied to the data input terminal D. 4Mhz clock CLK1 is applied to the clock terminal from the time switch 10 to output a 32-bit clock to the link controller 50 through the output terminal Q.

The timeslot decoder shown in FIG. 9 is connected to the tenth AND gate AND10 and the flip-flop FF4. The tenth AND gate AND10 receives the timeslot designation signals n5 and p5 from the timeslot counter 40 as the input signal i5 and receives the timeslot designation signal n4 from the timeslot counter 40. , p4) is applied as the input signal i4 to output the time slot selection signal generated by the AND to the link controller 50 side. In the flip-flop FF4, the preset terminal PRN and the clear terminal CLRN are connected to the power supply Vcc, and the timeslot selection signal from the tenth AND gate AND10 is applied to the data input terminal D. 4Mhz clock CLK1 is applied to the clock terminal from the time switch 10 to output a 64-bit clock to the link controller 50 through the output terminal Q.

The data transmission apparatus of the present invention configured as described above operates as follows.

For example, when the data applied from the time switch 10 is loaded in a plurality of timeslots and is transmitted to the link controller 50, the timeslot counter 40 may be used to transmit 8 bits of data in one timeslot. Is operated by receiving the 8 kHz flame synchronous signal FS and the 4 MHz clock CLK1 applied from the time switch 10 to generate a plurality of time slot designation signals n1 to n5 and p1 to p5. When outputting to the timeslot decoder, the timeslot decoder receives the timeslot designation signal from the timeslot counter 40 as the input signals i1 to i5 and receives the 4Mhz clock CLK1 from the time switch 10. The time slot selection signal generated by the operation is transmitted to the link controller 50, and the 8-bit clock is transmitted to the link controller 50. At this time, the link controller 50 receives data applied from the multiplexer / demultiplexer 20 and receives data according to a timeslot selection signal from an timeslot decoder and an 8-bit clock. That is, when the link controller 50 receives data from the multiplexer / demultiplexer 20, the link controller 50 selects data of the corresponding timeslot according to the timeslot selection signal from the timeslot decoder to the timeslot decoder. Based on the 8-bit clock from, it receives 8-bit data of the corresponding timeslot.

As described above, when transmitting 16-bit data in one time slot, the link controller 50 receives the data according to the time slot selection signal and the 16-bit clock applied from the time slot decoder configured as shown in FIG. In the case of transmitting 32 bits of data in the timeslot of the link controller 50, the link controller 50 receives data according to the timeslot selection signal and the 32 bits clock applied from the timeslot decoder configured as shown in FIG. When transmitting bit data, the link controller 50 receives data according to a timeslot selection signal and a 64-bit clock applied from a timeslot decoder configured as shown in FIG.

As described above, the present invention transmits data through a plurality of timeslots when data is transferred between the time switch and the link controller in the switching system, thereby improving the performance of the switching system by transmitting a large amount of data in a short time. .

Claims (6)

A time switch for transmitting data while performing a switching operation; A data transmission device between a time switch and a link controller in a switching system including a link controller that receives data, outputs the data to a CPU side through a memory unit, and transmits data applied from the CPU to the CPU. When receiving the data applied from the time switch, the data is demultiplexed and transmitted to the link controller, and when receiving the data from the link controller, the multiplexed / demultiplexed data is transmitted to the time switch side. Wealth; A time slot counter configured to receive a frame synchronization signal and a clock supplied from the time switch and output a plurality of time slot designation signals; A time slot for transmitting the clock generated by the time slot designation signal from the timeslot counter and the clock from the time switch to the link controller and a time slot selection signal to the link controller. An apparatus for transmitting data between a time switch and a link controller in an exchange system comprising a decoder. The method of claim 1, The timeslot counter includes a plurality of counters to divide the first to fourth timeslot designation signals generated by the frequency division operation according to a clock and a frame synchronization signal of a predetermined frequency applied from the timeswitch. A dispensing unit for outputting to; A fourth time slot designation signal, which is inverted through the first inverter from the division unit, is applied to the clock terminal and a frame synchronization signal is applied to the clear terminal from the time switching unit to operate the fifth time slot decoder. A flip-flop for applying a slot designation signal; A second inverter for outputting a tenth timeslot designation signal generated by inverting a fifth timeslot designation signal applied from the flip-flop to the timeslot decoder; A third inverter for outputting a sixth timeslot designation signal generated by inverting the first timeslot designation signal applied from the frequency divider to the timeslot decoder; A fourth inverter for outputting a seventh timeslot designation signal generated by inverting the second timeslot designation signal applied from the frequency divider to the timeslot decoder; A fifth inverter for outputting an eighth timeslot designation signal generated by inverting a third timeslot designation signal applied from the frequency divider to the timeslot decoder; And a sixth inverter for outputting a ninth timeslot designation signal generated by inverting the fourth timeslot designation signal applied from the frequency divider to the timeslot decoder. Data transfer device. The method according to claim 1 or 2, The timeslot decoder receives fourth and ninth timeslot designation signals from the timeslot counter as a first input signal and receives third and eighth timeslot designation signals from the timeslot counter as a second input signal. A first AND gate that is applied as an AND and outputs a signal generated by logical multiplication; The second and seventh timeslot designation signals from the timeslot counter are applied as first input signals, and the first and sixth timeslot designation signals from the timeslot counter are applied as the second input signals and logically multiplied. A second AND gate for outputting the generated signal; A third AND gate which ANDs and outputs a signal applied from the first and second AND gates; A timeslot selection signal generated by applying a fifth and tenth timeslot designation signal from the timeslot counter as a first input signal and receiving a signal from the third end gate as a second input signal A fourth end gate output to the link controller side; And a flip-flop for outputting an 8-bit clock to the link controller by operating the time slot selection signal from the fourth end gate to a data input terminal and receiving a clock from the time switch. Data transfer device between the time switch and the link controller in a switching system. The method according to claim 1 or 2, The timeslot decoder receives the fifth and tenth timeslot designation signals from the timeslot counter as a first input signal and receives the fourth and ninth timeslot designation signals from the timeslot counter as a second input signal. A fifth AND gate, which is applied as an AND and outputs a signal generated by logical multiplication; The third and eighth timeslot designation signals from the timeslot counter are applied as first input signals, and the second and seventh timeslot designation signals from the timeslot counter are applied as the second input signals and logically multiplied. A sixth AND gate for outputting the generated signal; A seventh AND gate outputting the timeslot selection signal generated by ANDing the signals applied from the fifth and sixth AND gates to the link controller side; And a flip-flop for outputting a 16-bit clock to the link controller by operating the time slot selection signal from the seventh AND gate to a data input terminal and receiving a clock from the time switch. Data transfer device between the time switch and the link controller in a switching system. The method according to claim 1 or 2, The timeslot decoder receives the fourth and ninth timeslot designation signals from the timeslot counter as a first input signal and receives the third and eighth timeslot designation signals from the timeslot counter as a second input signal. An eighth AND gate configured to receive an AND and output a signal generated by AND; A timeslot selection signal generated by applying a fifth and tenth timeslot designation signal from the timeslot counter as a first input signal and receiving a signal from the eighth end gate as a second input signal A ninth end gate output to the link controller side; And a flip-flop for operating a time slot selection signal from the ninth end gate to a data input terminal and receiving a clock from the time switch to a clock terminal to output a 32-bit clock to the link controller. Data transfer device between the time switch and the link controller in a switching system. The method according to claim 1 or 2, The timeslot decoder receives the fifth and tenth timeslot designation signals from the timeslot counter as a first input signal and uses the fourth and ninth timeslot designation signals from the timeslot counter as a second input signal. A tenth AND gate for outputting the timeslot selection signal, which is applied and logically generated, to the link controller side; And a flip-flop for outputting a 64-bit clock to the link controller by operating the time slot selection signal from the tenth end gate to a data input terminal and receiving a clock from the time switch. Data transfer device between the time switch and the link controller in a switching system.