KR100222412B1 - Circuit and method of highway multiplexing/demultiplexing - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

It relates to a highway that connects the control and line shelves of an exchange.

I. The technical problem that the invention is trying to solve

The purpose of the present invention is to implement a circuit and a method for reducing the thickness of a cable connecting the control shelf and the line shelf by multiplexing and demultiplexing the highway.

All. Summary of Solution of the Invention

The present invention relates to an exchange comprising at least one line shelf for accommodating subscribers and a control shelf for switching between subscribers accommodated in the line shelf; Respectively connected to the line shelf and the control shelf and multiplexing a plurality of low speed highways provided from one shelf to one high speed highway and outputting the multiplexed highways to the plurality of low speed highways A multiplexing / demultiplexing circuit for restoring and applying the restored plurality of low speed highways to the other side shelf is proposed.

la. Important uses of the invention

The occupied area inside the exchanger can be usefully used.

Description

Highway Multiplexing / Demultiplexing Circuits and Methods

The present invention relates to highways in exchanges, and more particularly to circuits and methods for multiplexing and demultiplexing highways.

In general, the exchange is implemented in the form of a cabinet, and the inside of the cabinet is composed of a plurality of shelves, each slot of the shelf performing various exchange functions required by the exchange. The cards are plugged in and mounted. For example, a card including a circuit for switching a subscriber signal is mounted on a control shelf of an exchange, and a card including a circuit for receiving a subscriber is mounted on a line shelf. have.

1A and 1B, it can be seen that the control shelf 10 and the line shelves 20 of the exchanger according to the related art are connected to each other via a highway using a series signal sequence of 2 Mb / s. In this case, since each line shelf 20 is generally designed to accommodate 256 subscribers and one 2Mb / s highway is to accommodate 32 subscribers, it is common to connect eight highways between the control shelf 10 and one line shelf 20. In addition, it can be seen that the lines for supplying various clock signals and control signals to be used in the system are further connected between the control shelf 10 and the line shelves 20. Lines and highways for supplying the clock signal and the control signal are accommodated in a single flat cable and connected between the control shelf 10 and the line shelves 20.

On the other hand, as the subscriber capacity of the exchange increases, the switching capacity and the number of line shelves of the switches included in the control shelf 10 will increase, and the number of highways required will increase in proportion. This will also increase the volume of the flat cable itself, resulting in lower overall exchange efficiency. This is because the cable occupies a large area instead of the cards (subscriber cards) that actually exchange in a limited sized exchange. In other words, as the cable area becomes larger, the necessary function of the exchange is required. Because it means that it is damaged.

It is therefore an object of the present invention to provide a circuit and a method for efficiently using the occupied area inside the exchanger.

Another object of the present invention is to provide a circuit and method for preventing the required thickness of the cable from increasing even when the subscriber capacity increases in the exchange.

Another object of the present invention is to provide a circuit and method for preventing the increase in the number of highways even when the subscriber capacity increases in the exchange.

The present invention for achieving the above object comprises at least one line shelf for subscriber acceptance and at least a control shelf for switching between the subscribers accommodated in the line shelf; Respectively connected to the line shelf and the control shelf and multiplexing a plurality of low speed highways provided from one shelf to one high speed highway and outputting the multiplexed highways to the plurality of low speed highways A multiplexing / demultiplexing circuit for restoring and applying the restored plurality of low speed highways to the other side shelf is proposed.

1a and 1b show a highway structure of an exchange according to the prior art;

2 shows a highway structure of an exchange according to the invention.

FIG. 3 is a diagram showing the configuration of the multiplexing / demultiplexing circuit shown in FIG. 2; FIG.

4 illustrates operation timing of a multiplexing / demultiplexing circuit according to the present invention.

5 is a view showing in more detail the configuration of the timer shown in FIG.

6A and 6B show an operation timing of the timer shown in FIG.

7 is a view showing in more detail the configuration of the shifter shown in FIG.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification.

2 is a diagram illustrating a configuration of a multiplexing / demultiplexing circuit according to the present invention, which outputs multiplexed multiplexed highways to one high-speed highway, and conversely demultiplexes the high-speed highway to multiple highways. And recovering the highway. More specifically, the multiplexing / demultiplexing circuit according to the preferred embodiment of the present invention multiplexes four 2Mb / s highways into one 8Mb / s fast highway (MUX: Multiplexing) to total eight 2Mb / s highways. Multiplex and transmit to 8Mb / s high speed highway. At the same time, two 8Mb / s fast highways received at the same time are demultiplexed into eight 2Mb / s (DEMUX) to be provided to the control shelf 10 or the line shelf 20 in a state restored to the original highway. . Such highway multiplexing / demultiplexing circuits (MUX / DEMUX) circuits 30 are on the control shelf 10 side and the line shelf 20 side, that is, between the control shelf 10 and the multiplexing / demultiplexing circuit 30 and between the lineshelf 20 and the multiplexing / demultiplexing circuit 30. Are respectively provided. As a result, the thickness of the cable connected between the control shelf 10 and the line shelf 20 is reduced to one quarter compared to the prior art. Because, according to the prior art, a cable having a thickness capable of accommodating eight highways is connected between the control shelf 10 and the line shelf 20, but according to the present invention, a cable having a thickness capable of accommodating two highways is controlled shelf 10. This is because it is connected between and the line shelf 20.

FIG. 3 is a diagram illustrating the configuration of the multiplexing / demultiplexing circuit 30 shown in FIG. 2 in more detail, and includes a timer 310 and a shifter 320. The shifter 320 multiplexes four highways hwin0 to hwin3 to output one high speed highway mhwout, and demultiplexes the received high speed highway mwwin to output four highways hwout0 to hwout3. In this case, signals / LD, fetch0, and fetch1 for determining the multiplexing / demultiplexing operation timing of the shifter 320 are generated by the timer 310. The timer 310 generates the multiplexing / demultiplexing operation timing determination signals using a system clock 16mclk and a frame pulse / fp. The system clock 16mclk is also provided to the shifter 320.

FIG. 4 is a diagram illustrating an operation timing of a multiplexing / demultiplexing circuit according to the present invention as shown in FIG. 3.

Referring to FIG. 4, assuming that an exchange to which the present invention is applied uses a serial signal sequence of 2 Mb / s and a system top clock of 16.384 MHz, one bit period of the 2 Mb / s highway is T = 488 nsec (1 / T = 2.048 Mb / s). In this case, the multiplexing circuit according to the present invention multiplexes a, b, c, d, which are the bit values hwin0 to 3, and outputs the multiplexed data on the output highway mhwout for 244 nsec corresponding to a half period of 488 nsec. At this time, the multiplexed data output on the output highway mhwout is output in the order of a, b, c, and d. Each multiplexed bit value is output in units of about 62 nsec (1 / 16.384 MHz). On the other hand, the demultiplexing circuit receives the highway mhwin containing the multiplexed data, demultiplexes the values of mhwout at each time point t1, t2, t3, and t4, and outputs the demultiplexed values to highways hwout0 to 3 phase, respectively. . At this time, since the bit values of a, b, c, and d are output to the highways hwout0 to 3 phases, four original 2Mb / s highways are restored and output as a result.

FIG. 5 is a diagram illustrating in detail the configuration of the timer 310 shown in FIG. 3, and receives sel0, fetchclk0, and fetchclk1 for multiplexing / demultiplexing operations of the shifter 320 by receiving an externally provided frame pulse / fp and a system clock 16mclk. Perform an operation to generate a signal.

Referring to FIG. 5, the timer 310 according to the present invention includes at least the flip-flops 311 to 313, 323, and 324. Each clock terminal of the flip-flops is applied with a system clock of 16 mclk of 16 MHz. The deflip-flop 311 inputs the frame pulse / fp to the input terminal D and outputs it to the output terminal Q. The deflip-flop 312 inputs the output of the flip-flop 311 to the input terminal D and outputs it to the output terminal Q. The flip-flop 313 inputs the output of the flip-flop 312 to the input terminal D and outputs the output to the output terminal Q. The output of the flip-flop 312 is applied to one input of the NAND gate 315 via the inverter 314, and the output of the flip-flop 313 is applied to the other input of the NAND gate 315. The NAND gate 315 performs a NAND gating operation by inputting the output of the inverter 314 and the output of the flip-flop 313, and then outputs the calculation result as a / cclr signal. The / cclr signal is applied to the negative clear terminal CLRN of the counter 317 to clear the count operation of the counter 317. The counter 317 performs a hexadecimal count operation according to 16 mclk applied to its clock terminal CLK via the inverter 316. That is, the counter 317 outputs clocks of 8 mclk, 4 mclk, and 2 mclk to the QA terminal and the QC terminal, respectively. At this time, the clocks of 8mclk, 4mclk, and 2mclk are inverted (inverted) by the inverters 318 to 320, respectively, and then applied to the input of the NAND gate 321. In addition, 4mclk, which is an output of the inverters 318,320 and an output of the counter 317, is applied as an input of the NAND gate 322. The operation result of the NAND gated by the NAND gate 321 is output as a sel0 signal, and is also applied as the D input terminal of the flip-flop 323 and then output as a fetchclk0 signal. Sel1, which is the result of the NAND gated operation by the NAND gate 322, is applied to the D input terminal of the flip-flop 324 and then output as a fetchclk1 signal. The sel0 signal, the fetchclk0 signal, and the fetchclk1 signal are each applied as / LD signals, fetchclk0 signals, and fetchclk1 signals of the shifter 320 for performing a multiplexing / demultiplexing operation.

6A and 6B illustrate an operation timing of the timer 310 configured as shown in FIG. 5.

Referring to FIG. 6A, the rising edge of the system clock 16 mclk and the falling edge of the output clocks 8 mclk, 4 mclk, and 2 mclk by the flip-flops 311 to 313 at the frame boundary indicated by / fp. The / cclr signal for matching the edges) is generated and input to the counter 317 which is a division circuit.

Referring to FIG. 6B, it can be seen that the falling edges of the 16 mclk, 8 mclk, 4 mclk, and 2 mclk clocks coincide with each other at the boundary (488 nsec) of each bit. The sel0 signal falls to the "low" level during one period of the 16 mclk clock at the beginning of the bit boundary. This sel0 signal outputs hwin0 'a' in mhwout and hwin1 'b' and hwin2 'c'. And a shift circuit (deflip-flops 326, 330, 334 in FIG. 7) which causes the value 'd' of hwin3 to be output to mhwout. fetchclk0 and fetchclk1 are input to the demultiplexing unit of the multiplexing / demultiplexing circuit, as shown in FIG. 7, wherein the demultiplexing unit is fetched from the falling edge t1 of fetchclk0 and output to hwout0. At fetch edge t2 of fetchclk0, mhwin fetches the value 'b' and outputs it to hwout1, and at fetchclk1 descending edge t3, the mhwin value 'c' is fetched and output to hwout2, and fetchclk1 rise edge t4 to the mhwin value 'd' Is fetched and output to hwout3.

FIG. 7 is a diagram illustrating in detail the configuration of the shifter 320 illustrated in FIG. 3, and is roughly divided into a multiplexer and a demultiplexer as described with reference to FIG. 6.

Referring to FIG. 7, the multiplexer inputs a signal applied through the highways hwin0 to hwin3 to perform multiplexing, and then outputs the multiplexed signal on the highway mhwout. That is, the multiplexer performs a function of multiplexing four highways into one highway and outputting the multiple highways. The multiplexer for this operation is composed of components shifting hwin1 largely, components shifting hwin2, and components shifting hwin3. In FIG. 7, the AND gates 323, 324 and the OR gate 325, the flip-flop 326 are responsible for shifting hwin1, the AND gates 327, 328, or gate 329, and the flip-flop 330 are responsible for shifting hwin2. The AND gates 331 and 332, the OR gate 333, and the flip-flop 334 are responsible for shifting hwin3.

One input terminal of the AND gate 323 is applied with Vcc, and the other input terminal is generated by the timer 310 configured as shown in FIG. 5, and then the load signal / LD through the inverters 321 and 322 is applied. One input terminal of the AND gate 324 is applied with the load signal / LD via the inverter 321, and the other input terminal is applied with the hwin1 signal. The outputs of the AND gate 323 and the AND gate 324 are gated by the or gate 325 and then applied to the D input terminal of the def flip-flop 326. Then, the flip-flop 326 outputs the signal applied from the or gate 325 through the Q output terminal according to the system clock 16mclk applied to the clock terminal.

The output of the flip-flop 326 is applied to one input terminal of the AND gate 327, and the load signal / LD through inverters 321 and 322 is applied to the other input terminal. One input terminal of the AND gate 328 is applied with the load signal / LD via the inverter 321, and the other input terminal is applied with the hwin2 signal. The outputs of the AND gate 327 and the AND gate 328 are gated by the OR gate 329 and then applied to the D input terminal of the def flip-flop 330. The flip-flop 330 then outputs the signal applied from the OR gate 329 through the Q output terminal according to the system clock 16 mclk applied to the clock terminal.

The output of the flip-flop 330 is applied to one input terminal of the AND gate 331, and the load signal / LD through the inverters 321 and 322 is applied to the other input terminal. One input terminal of the AND gate 332 is applied with the load signal / LD via the inverter 321, and the other input terminal is applied with the hwin3 signal. The outputs of the AND gate 331 and the AND gate 332 are orgated by the OR gate 333 and then applied to the D input terminal of the def flip-flop 334. The flip-flop 334 then outputs the signal applied from the or gate 333 through the Q output terminal according to the system clock 16mclk applied to the clock terminal.

The signal output from the flip-flop 334 is a serial signal and is applied to the D input terminal of the flip-flop 336, and the flip-flop 336 Q is applied to the applied signal according to 16 mclk applied to its clock terminal through the inverter 335. Output to one input terminal of ANDGATE 339 through the output terminal. The other input terminal of the AND gate 339 is applied with the load signal / LD from the timer 310, and the AND gate 339 is applied to one input of the OR gate 340 after ANDing two applied signals. An output of the AND gate 338 is applied to the other input of the OR gate 340, and hwin0 is applied to one input of the AND gate 338, and a load signal / LD through the inverter 337 is applied to the other input. The OR gate 340 then orchestrates the outputs of the AND gates 338 and 339 and outputs the result of the operation as the mhwout signal. At this time, the output mhwout signal is a signal that is sequentially multiplexed with 'a' value of hwin0, 'b' value of hwin1, 'c' value of hwin2, and 'd' value of hwin3. That is, four high speed highways are output as multiplexed with one high speed highway.

Referring to FIG. 7 again, the demultiplexing unit includes at least a series of flip-flops 342, 343, 345, and 346. At this time, all of the flip-flops have mhwin, the highway signal multiplexed to their D input terminals. The deflip-flop 342 is generated by the timer 310 configured as shown in FIG. 5 and latches the mhwin according to the fetchclk0 signal applied to the clock terminal through the inverter 341, and outputs the latch result as a hwout0 signal. The deflip-flop 343 latches the mhwin according to the fetchclk0 signal generated by the timer 310 and applied to the clock terminal, and outputs the latch result as a hwout1 signal. The deflip-flop 345 latches the mhwin according to the fetchclk1 signal generated by the timer 310 and applied to the clock terminal through the inverter 344, and outputs the latch result as a hwout2 signal. The deflip-flop 346 latches the mhwin according to the fetchclk1 signal generated by the timer 310 and applied to the clock terminal, and outputs the latch result as a hwout3 signal. At this time, the output highway signals hwout0 to hwout3 are signals that are multiplexed by the multiplexed highway signal mhwin at times t1 to t4 as shown in FIG. 4. That is, one high speed multiplexed highway is demultiplexed into four low speed highways and output.

As described above, the present invention provides an exchanger having a multiplexing / demultiplexing circuit provided on the control shelf side and the line shelf side, respectively. Using this multiplexing / demultiplexing circuit, the transmitting side can multiplex four low speed highways into one high speed highway, and the receiving side can demultiplex one high speed highway to restore four low speed highways. As a result, the cable thickness between the control shelf and the line shelf can be reduced to 1/4, and even if the subscriber capacity of the exchange becomes large, the volume of the cable does not increase significantly in proportion to the occupancy inside the exchange. There is an advantage that the area can be used efficiently.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (2)

An exchange comprising at least one line shelf for subscriber acceptance and at least a control shelf for switching between subscribers accommodated in the line shelf, Respectively connected to the line shelf and the control shelf and multiplexing a plurality of low speed highways provided from one shelf to one high speed highway and outputting the multiplexed highways to the plurality of low speed highways And multiplexing the restored plurality of low speed highways to the other side shelf. At least one line shelf for subscriber acceptance and at least a control shelf for switching between subscribers accommodated in the line shelf, wherein between the control shelf and the line shelf accommodates a certain number of highways In a method for reducing the thickness of the cable in the exchange to be connected, The thickness of the cable is reduced by the number of times of the highway, and instead, the transmitting side multiplexes the signals included in the number of highways into signals on one highway within the same time, and the transmitting side multiplexes the signals. And demultiplexing the multiplexed signal on one highway output from the side shelf and restoring the signals on the number of highways.

Images