KR19980028730A - A device for programmably converting the driving voltage of a CPU and a chip set - Google Patents

Abstract

The present invention relates to an apparatus for converting a driving voltage of a CPU and a chip set by firmware that programmably sets a driving voltage instead of adjusting a jumper. The apparatus of the present invention includes an address decoder unit, a programmable data memory, a DC to DC converter, and a feedback resistor switching circuit. In operation, the computer inputs to the address decoder unit the address and data signals necessary to vary the drive voltage. After decoding, the data is written to a programmable data memory. The programmable data memory converts the output voltage of the DC to DC converter by outputting a selection signal to change the internal resistance of the feedback resistor switching circuit.

Description

A device for programmably converting the driving voltage of a CPU and a chip set

The present invention relates to a device for programmably converting the driving voltage of a CPU and a chip set, and more particularly to a device for programmably converting a driving voltage of a CPU and a chip set by firmware instead of a jumper will be.

2. Description of the Related Art In recent years, specifications of driving voltages of a central processing unit (CPU) and a chip set have been varied due to an increase in computer manufacturers and different manufacturing techniques. For example, for a Pentium CPU used in personal computers, there is a difference in the driving voltage of CPUs manufactured by Intel, Shrixx, and AMD. CPUs are manufactured by one manufacturer, but they are different. For example, the SSS numbered on the back of a Pentium CPU represents a drive voltage of 3.3 volts, and the VMU represents a drive voltage of 3.45 volts. The Shrix CPU has a driving voltage, such as 3.3 volts and 3.52 volts, depending on its number. In addition, in the case of a high-frequency CPU requiring a voltage regulation module (VRM), it has a driving voltage such as 2.5 volts and 2.7 volts. As a result, in order to support the CPU, the manufacturer must provide a plurality of sets of jumpers or a voltage converter embedded in the computer so that the user can adjust the driving voltage of the CPU and chipset.

Figure 1 shows a schematic diagram of a conventional regulating circuit. The conventional regulating circuit consists of a DC to DC converter 10, a feedback resistor Rf and a fixed resistor R1. The feedback resistor Rf and a fixed resistor R1 is an output voltage V _out is the reference voltage V _ref the DC to DC converter 10, a resistance, a reference voltage of the feedback resistor Rf by allowing be applied to V _ref and DC versus through multiple circuit DC converter 10 to change the output voltage _Vout . In order to send out a group of various voltages from the structure, it is the most widely used method in recent years to use a jumper having resistors of different resistances in the regulating circuit. As shown in FIG. 2, which shows a schematic diagram of a conventional multistage regulation circuit according to the method, the regulation circuit uses three feedback resistors 21 connected in series with the jumper set 22, respectively.

In this arrangement, various feedback resistances are obtained and the driving voltage can be varied.

A third disadvantage is that the metal jumper can be aged and oxidized due to moisture and can cause defects in the connection. Therefore, there is a need to improve the device.

The present invention provides an improved apparatus for programmably converting the driving voltage of a CPU and chip set to solve and / or eliminate the above problems. In another aspect of the present invention, a feedback resistor switching circuit is provided, And the base electrode of each transistor serves as a signal input connected to a programmable data memory.

According to a further aspect of the present invention, an apparatus for programmably converting a driving voltage of a CPU and a chipset is coupled to an address / decoder for decoding and transferring input address data, an address / data bus of a CPU and a chip set A programmable data memory having a nonvolatile memory element for receiving, describing and locking a data signal input by an address decoder unit, an input of the address data for inputting digital data representative of a specific address and a driving voltage, And a feedback resistor switching circuit connected between the output of the DC to DC converter and the input of the reference voltage and having an input connected to the output of a programmable data memory for varying its internal equivalent resistance in accordance with the output state of the data memory .

Other objects, advantages and novel features of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.

1 is a schematic diagram showing a conventional regulating circuit;

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a CPU and a chip set, and more particularly,

5 is a circuit diagram showing in detail a preferred embodiment of an apparatus according to the present invention.

In Fig. 3, an apparatus for programmably converting the driving voltage of the CPU and chip set according to the present invention uses the impedance conversion circuit 40 instead of the feedback register Rf shown in Figs. 1 and 2. _out memory, so that the data is not deformed before rerun.

The address decoder unit 41 receives and decodes the address and digital data input by the CPU and chip set 50. After ascertaining the address data, the address decoder unit 41 generates a start signal and writes the input data of the drive voltage in the programmable data memory 42. Since the contents of the programmable data memory 42 can be changed in the above manner, the switching states and the resistances of the internal feedback resistors of the feedback resistor switching circuit 43 are changed by changing the output signals of the memory 42, The voltage input to the DC to DC converter 10 and the output drive voltage V _out are changed.

5 is a circuit diagram showing in detail a preferred embodiment of an apparatus according to the present invention. The address decoder unit 41 receives the address data input by the CPU and the chip set 50. The decoder output acts as a sequence signal to activate the programmable data memory 42. The programmable data memory 42 includes a programmable burner 421 and a register 422. The decode output unit of the address decoder unit 41 is connected to the order input unit of the data register 422. The data input part of the data register 422 is connected to the data bus and receives data indicating the driving voltage on the bus. Programmable burner 421 is a programmable memory EEPROM. The signal input SIN, the order input SCLK, and the mode input MODE of the programmable QJSJ 421 are connected to respective output signals of the data register 422.

The feedback resistor switching circuit 43 includes a plurality of transistors 435-438 connected in series with corresponding resistors 431-434. The base electrodes of each of the transistors 435-438 are connected to respective outputs of a programmable burner 421.

By virtue of the combination of the respective resistors 431-434, the actual internal resistance thereof can be varied, thereby changing the voltage output by the DC to DC converter 10. [

Accordingly, the present invention provides an apparatus for programmably converting the driving voltage of a CPU and a chip set by setting on a screen of a computer, instead of changing or adjusting a plurality of jumpers. In other words, it is possible to omit a series of steps such as disassembling the computer, finding the handbook, adjusting the jumper, and so on, as well as problems related to conventional devices such as error control, unstable host and shortened operating life of the CPU Can be removed. Further, the present invention is controlled by a program, and its switching control circuit is entirely in electronic design to prevent defects in oxidation and control.

While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (13)

And an impedance conversion circuit connected between the output of the DC to DC converter and the input of the reference voltage so that the input of the impedance conversion circuit is connected to the address / data bus of the CPU and chip set, And the impedance conversion circuit converts the actual impedance according to the data by inputting digital data representing the voltage, thereby programmably converting the driving voltage of the CPU and the chip set. 2. The apparatus of claim 1, wherein the impedance conversion circuit further comprises: an address data unit for decoding and transmitting input address data; A programmable data memory having a nonvolatile memory element for receiving, writing and locking a data signal input by an address decoder unit; And a feedback resistor switching circuit having an input section connected to an output section of a programmable data memory for changing an internal equivalent resistance thereof in accordance with an output state of the data memory, . 3. The apparatus of claim 2, wherein the address decoder unit is a decoder, and programmably converts a driving voltage of a CPU and a chip set. 4. The apparatus of claim 3, wherein the output of the adder decoder unit is provided for inputting a sequence signal into a programmable data memory to programmably convert the drive voltage of the CPU and chipset. 3. The apparatus of claim 2, wherein the programmable data memory comprises a data register and an EEPROM. 3. The apparatus of claim 2, wherein the programmable data memory comprises a data register and a rechargeable battery. 3. The semiconductor memory device according to claim 2, wherein the feedback resistor switching circuit is constituted by a plurality of transistors each connected in series with a resistor, and the base electrode of each transistor acts as a signal input connected to a programmable data memory, To a programmable output voltage. An address decoder unit for decoding and transferring input address data, the input unit being connected to an address / data bus of a CPU and a chip set, the bus inputting digital data representing a specific address and a driving voltage, respectively; A programmable data memory having a nonvolatile memory element for receiving, writing and locking a data signal input by an address decoder unit; And a feedback resistor switching circuit coupled between the output of the DC to DC converter and an input of the reference voltage and having an input connected to the output of the programmable data memory for varying its internal equivalent resistance in accordance with the output state of the data memory And a programmable conversion of the driving voltage of the CPU and the chip set. 9. The apparatus of claim 8, wherein the address decoder unit is a decoder, and programmably converts a driving voltage of a CPU and a chip set. 9. The apparatus of claim 8, wherein the output of the address decoder unit is provided for inputting an order signal into a programmable data memory, Possibly converting. 9. The apparatus of claim 8, wherein the programmable data memory comprises a data register and an EEPROM. 9. The apparatus of claim 8, wherein the programmable data memory includes a data register and a battery to programmably convert a drive voltage of the CPU and chipset. The semiconductor memory device according to claim 8, wherein the feedback resistor switching circuit is constituted by a plurality of transistors each connected in series with a resistor, and the base electrode of each transistor acts as a signal input connected to a programmable data memory, To a programmable output voltage.