JP4559148B2 - Microcontroller and power supply method for microcontroller - Google Patents

Description

  The present invention relates to a microcontroller having a plurality of circuit blocks, and more particularly to power supply to individual circuit blocks.

In the semiconductor integrated circuit disclosed in Patent Document 1, the regulator unit (1) for supplying the power supply voltage VDD1 to the logic circuit and the regulator unit (2) for supplying the power supply voltage VDD2 to the oscillation circuit are respectively provided. The power supply voltage fluctuations are appropriately suppressed and stably maintained at a predetermined power supply voltage.
Patent Documents 2 and 3 are disclosed as the above-described related art.

JP-A-8-272463 JP 2001-216780 A JP 7-105682 A

  In the above background art, the power supply voltage supplied to each circuit block is hardly affected by the mutual voltage fluctuation by providing the regulator unit individually for each logic circuit, oscillation circuit, or other circuit block. The power supply voltage is stable at each voltage value.

  However, the power supply voltage supplied to each circuit block is fixed to a predetermined voltage value determined by each regulator unit. In a microcontroller or the like having a plurality of circuit blocks, there are a variety of operation states, and it is conceivable that activated circuit blocks differ for each operation state. In each circuit block, the degree of activation from the active state to the inactive state differs depending on the operating state, and the necessary and sufficient power supply voltage may differ depending on this. For example, a higher power supply voltage needs to be supplied to the active circuit block, and conversely, it is sufficient to supply a low power supply voltage to the resting circuit block.

  If the technique of Patent Document 1 is applied to each circuit block in the microcontroller having such circumstances, the operation state of the microcontroller cannot be optimized.

  That is, if a power supply voltage that is higher than the supplied power supply voltage is supplied, the degree of activity is limited by the supplied power supply voltage for a circuit block that can have a higher activity state. As a result, the circuit performance inherent in the circuit block cannot be fully exploited.

  Further, even when it is sufficient to supply a power supply voltage that is lower than the power supply voltage supplied in the rest state, an excessive power supply voltage is applied, and the circuit block originally has As a result, a large amount of current consumption flows compared to the current consumption.

  The present invention has been made to solve at least one of the above-described problems of the background art, and in supplying each power supply voltage individually to each of a plurality of circuit blocks constituting a microcontroller, each circuit block is provided. An object of the present invention is to provide a microcontroller capable of adjusting a power supply voltage value in accordance with the operation state of the device and a power supply method for the microcontroller.

In order to achieve the above object, a microcontroller according to the present invention is a microcontroller comprising a plurality of circuit blocks and a bus connecting circuit blocks, and individually supplies a power supply voltage to each circuit block and each bus. Interface between the circuit block and / or between the circuit block and the bus, and the power control unit that varies the output power supply voltage for each power supply unit according to the operating state of the microcontroller When the determination unit determines that the amplitude levels of the signal lines between the interfaced circuit blocks or / and between the circuit block and the bus coincide with each other, The level converter unit that converts Characterized in that it comprises a scan unit.

Further, a power supply method for a microcontroller according to the present invention is a power supply method for a microcontroller comprising a plurality of circuit blocks and a bus connecting the circuit blocks, and each of the circuit blocks and the bus is individually provided. A step of supplying a power supply voltage, a step of varying a power supply voltage output in the step of supplying a power supply voltage according to an operating state of the microcontroller, and a circuit block and / or a circuit block and a bus. When interfacing, the step of determining the coincidence of the amplitude level of each signal line between the circuit blocks to be interfaced and / or between the circuit block and the bus, and the amplitude when the discriminating step determines that there is a mismatch It is determined as a match by the level conversion step and the determination step. The case, and having a step of directly connecting the signal line.

  According to the microcontroller and the power supply method for the microcontroller of the present invention, the power supply voltage is individually supplied to a plurality of circuit blocks constituting the microcontroller and a bus connecting the circuit blocks. The voltage value of the power supply voltage supplied to each circuit block and bus is variable according to the state.

According to the present invention, the power supply voltage can be individually supplied for each circuit block or bus. However, since the voltage value of each power supply voltage is variably adjusted according to the operation state of the microcontroller, the active state For the blocks in the circuit block, a high power supply voltage can be supplied to sufficiently bring out the operation performance of the circuit block, and for the blocks in the dormant state, the power supply voltage must be low. Therefore, unnecessary current consumption can be suppressed. And since the voltage value of the power supply voltage can be adjusted according to the operating state even during the operation of the microcontroller, it always operates at high speed and with high functionality for microcontrollers with various operating states. It is possible to operate with both performance and low current consumption performance.
Further, when the signal amplitude level between the terminals of the level converter is the same potential, by providing a bypass path, it is possible to transmit a signal without going through the level converter at the same potential, and high-speed transmission can be achieved.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail based on FIGS. 1 to 4 with reference to the drawings.

  FIG. 1 is a circuit block diagram of a microcontroller according to an embodiment. The microcontroller includes a circuit block including a CPU unit 51, a memory unit 52, a peripheral circuit unit (1) 53, and a peripheral circuit unit (2) 54. Each circuit block is a block that performs a unique function in the microcontroller. The CPU unit 51 corresponds to the heart of a microcontroller that performs various controls. The memory unit 52 stores program codes and various data and is used according to the control of the CPU unit 51. The peripheral circuit (1) 53 and the peripheral circuit (2) 54 include a logic function unique to each microcontroller and other peripheral functions. For example, a user-specific customization function, a PLL function, an AD / DA conversion function, an addition / multiplication function, and the like can be considered.

  The power supply terminals (VCC) of the circuit blocks 51 to 54 are supplied with the internal power supply voltages VR1 to VR4 from the regulator units (1) 11 to (4) 14, respectively. The internal power supply voltages VR1 to VR4 have voltage values obtained by stepping down the voltage VCC0 supplied to the power supply terminals (VCC) of the regulator units (1) 11 to (4). The output voltage value is set in accordance with setting signals SVR (1) to SVR (4) set in the voltage setting register unit 2. Since the power supply voltage VCC0 is supplied to the power supply terminal (VCC) of the voltage setting register unit 2, the high potential levels of the setting signals SVR (1) to SVR (4) become the voltage VCC0, and the signal amplitude level of the power supply voltage VCC0 Become. Further, the regulator units (1) 11 to (4) 14 are controlled in an active state and a pause state in response to pause signals / ST1 to / ST4 input to the inhibition terminal (INH).

  Each of the circuit blocks of the CPU unit 51, the memory unit 52, the peripheral circuit unit (1) 53, the peripheral circuit unit (2) 54, and the voltage setting register unit 2 perform signal transmission with each other via the bus line 56. The bus line 56 is set with a pull-up potential by the signal level adjustment unit 55. The pull-up potential is set according to the internal power supply voltage VRN input to the power supply terminal (VCC). The internal power supply voltage VRN is set by a regulator unit (N) 1N having the same configuration as the regulator units (1) 11 to (4). The regulator unit (N) is controlled to be activated or deactivated according to the pause signal / STN, and the voltage value VRN output by the setting signal SVR (N) set in the voltage setting register unit 2 Is set.

  At this time, level converters (0) 30 to (4) 34 are provided between the circuit blocks 51 to 54 and the voltage setting register unit 2 and the bus line 56 in order to absorb differences in signal amplitude levels. Has been placed. Of the level converters (0) 30 to (4) 34, the internal power supply voltages VR1 to VR4 and VCC0 are connected to the power supply terminals (VCCA) supplied to the interface portions with the circuit blocks 51 to 54 and the voltage setting register unit 2, respectively. Is supplied. The internal power supply voltage VRN is supplied to the power supply terminal (VCCB) that supplies power to the interface portion with the bus line 56.

  The level converters (1) 31 to (4) 34 have a control terminal (BPS) for inputting a control signal for bypassing the level shift function when the circuit blocks 51 to 54 and the bus line 56 are at the same potential. Is provided. The output terminals of the AND gates A1 to A4 are connected to the control terminals (BPS) of the level converters (1) 31 to (4) 34, respectively. A set signal SVR (N) for setting a pull-up potential of the bus line 56 is commonly input to each of the AND gates A1 to A4, and each of the level converters (1) 31 to (4) 34 is connected. Setting signals SVR (1) to SVR (4) for setting voltage values of the internal power supply voltages VR1 to VR4 of the circuit blocks 51 to 54 are input. Here, the power supply voltage VCC0 is supplied to the power supply terminal (VBG) as a back gate voltage of a transistor constituting a bypass path to be described later.

  FIG. 2 is a diagram illustrating a specific configuration of the voltage setting register unit 2. This is a case where a 2-bit signal is assigned to each of the regulator units (1) 11 to (N) 1N. Four types of settings are possible depending on the combination of each bit signal of the 2-bit signal, and FIG. 2 shows a circuit configuration when each setting of 3.3 V, 2.5 V, and 1.8 V is performed. . When both (bit 1) and (bit 0) are at a low level, S33 (x) is selected and a setting signal of 3.3V is output. When (bit 1) is at a low level and (bit 0) is at a high level, S25 (x) is selected and a setting signal of 2.5V is output. When (bit 1) is at a high level and (bit 0) is at a low level, S18 (x) is selected and a setting signal of 1.8V is output.

  A register area having a 2-bit configuration is allocated to each of the regulator units 11 to 1N, and setting of register information having a 10-bit configuration as a whole is performed, for example, from the CPU unit 51 via the level converter (1) 31 to the bus line 56. And is stored in the voltage setting register section 2 via the level converter (0) 30. The setting information of the power supply voltage is appropriately rewritten from the CPU unit 51 according to the operation state of each circuit block 51 to 54 and the bus line 56 determined by the control of the CPU unit 51. The output voltage can be individually set for each of the regulator units 11 to 1N according to the operation state.

  FIG. 3 is a circuit example of the regulator units (1) 11 to (N) 1N. A reference voltage generation circuit REG and an operational amplifier OP1 to which a power supply voltage VCC0 (for example, 5 V) is supplied are provided, and the reference voltage VRF output from the reference voltage generation circuit REG is applied to the inverting input terminal of the operational amplifier OP1. Have been entered. The internal power supply voltage VRx (x = 1 to 4, N) output from the regulator unit is connected to the ground potential via the resistance element R1 and the resistance elements R2 to R4 and the NMOS transistors T11 to T13. A connection point between the element R1 and the resistance elements R2 to R4 is connected to a non-inverting input terminal of the operational amplifier OP1. The output terminal of the operational amplifier OP1 is connected to the gate terminal of the PMOS transistor T1, and performs conduction control of the PMOS transistor T1 connected between the power supply voltage VCC0 and the internal power supply voltage VRx.

  The gate terminals of the NMOS transistors T11 to T13 are connected to the output terminals of the AND gates A11 to A13. A pause signal / STx (x = 1 to 4, N) is commonly input to the AND gates A11 to A13, and setting signals S18 (x) and S25 (x) are provided for each of the AND gates A11 to A13. , S33 (x) (x = 1 to 4, N) is input. The reference voltage generating circuit REG and the operational amplifier OP1 are connected to the installation potential via the NMOS transistor T2 controlled by the pause signal / STx.

  When the pause signal / STx becomes a high level and an activation state of the corresponding circuit block 51 to 54 or bus line 56 is instructed, the regulator units (1) 11 to (N) 1N are activated. The reference voltage generating circuit REG and the operational amplifier OP1 are connected to the ground potential via the NMOS transistor T2, and the circuit operation is activated. At this time, NMOS transistors T11 to T13 are selected in response to selection of any one of the setting signals S18 (x), S25 (x), and S33 (x) set in the voltage setting register unit 2 shown in FIG. Any one of them conducts. As a result, the internal power supply voltage VRx is divided by the resistance element R1 and the resistance elements R2 to R4 and returned to the operational amplifier OP1, and the internal power supply voltage VRx is controlled to a predetermined voltage.

  When the setting signal S18 (x) is selected, the voltage is divided between the resistance elements R1 and R2. If the reference voltage value VRF and the resistance values R1 and R2 are selected according to the relationship VRx = VRF × (R1 + R2) / R2 by constant voltage control by the operational amplifier OP1, 1.8V is output as the internal power supply voltage VRx. . Similarly, when the setting signal S25 (x) is selected, if the reference voltage value VRF and the resistance values R1 and R3 are selected according to the relationship VRx = VRF × (R1 + R3) / R3, the internal power supply voltage VRx is obtained. When 2.5V is output and the setting signal S33 (x) is selected, if the reference voltage value VRF and the resistance values R1 and R4 are selected according to the relationship VRx = VRF × (R1 + R4) / R4, the internal 3.3V is output as the power supply voltage VRx.

  When the pause signal / STx is at a low level, the path to the ground potential of the reference voltage generation circuit REG and the operational amplifier OP1 is cut off, and the circuit enters a pause state. As a result, the internal power supply voltage VRx is not output.

  The output internal power supply voltage value can be adjusted for each regulator unit according to the pause signal / STx and the setting signals S18 (x), S25 (x), and S33 (x). Specifically, 1.8V, 2.5V, 3.3V, and 0V can be selected as the internal power supply voltage VRx according to the setting signal. For each of the plurality of circuit blocks 51 to 54 provided in the microcontroller, further including the bus line 56, the necessary circuit blocks and bus lines can be driven with a desired voltage according to the operation state. For example, 3.3 V, which is a sufficient internal power supply voltage, is supplied to a block that requires high-speed processing, and a low voltage is applied to a circuit block that is in a sleep state when a low-speed operation is sufficient. Adjustments such as supplying 1.8 V as a power source can be performed. According to the difference in the operating state, it is possible to individually supply a power supply voltage that can provide necessary and sufficient circuit performance required for each of the circuit blocks 51 to 54 and the bus line 56, and sufficient circuit performance. Can be realized with low current consumption.

  FIG. 4 is a specific example of the level converters (1) 31 to (4). It is composed of a level shift function part and a bypass function part.

  The level shift function part has a bidirectionally symmetric configuration. Input signals from the circuit blocks 51 to 54 and the bus line 56 are input to inverter gates I1 and I2, which are driven by the same internal power supply voltage as the respective signal amplitude levels. Each internal power supply voltage is supplied from power supply terminals (VCCA) and (VCCB). The output terminals of the inverter gates I1 and I2 are connected to the gate terminals of the NMOS transistors T3 and T4. NMOS transistors T3 and T4 are provided between one end of pull-up resistors RU1 and RU2 and the ground potential. The other ends of the pull-up resistors RU1 and RU2 are connected to the same internal power supply voltage as the signal amplitude level in the bus line 56 and the circuit blocks 51 to 54 that output signals. Each internal power supply voltage is supplied from power supply terminals (VCCB) and (VCCA).

  As a result, even when there is a difference in the operating power supply voltage between the circuit blocks 51 to 54 and the bus line 56, the amplitude level of the signal is converted to an amplitude level suitable for the internal power supply voltage of each part, and the signal Propagation is possible.

  The bypass function portion includes a transfer gate TG1 connected between the circuit blocks 51 to 54 and the bus line 56, and an inverter gate I3 which is a logic control portion for controlling conduction of the transfer gate TG1. Has been. The output terminal of the inverter gate I3 is connected to the gate terminal of the PMOS transistor in the transfer gate TG1. A bypass terminal (BPS) is connected to the input terminal of the inverter gate I3 and the gate terminal of the NMOS transistor in the transfer gate TG1. In response to a high level signal being input to the bypass terminal (BPS), the transfer gate TG1 is turned on.

  As shown in FIG. 1, signals input to the bypass terminal (BPS) are output signals of the AND gates A1 to A4. As described above, the AND gates A1 to A4 have the setting signal SVR (N) for setting the pull-up potential of the bus line 56 and the setting signal SVR for setting the internal power supply voltages VR1 to VR4 of the circuit blocks 51 to 54, respectively. Performs a logical product operation with (1) to SVR (4). The setting signal SVR (N) and the setting signals SVR (1) to SVR (4) are specifically signals shown in FIG. A combination of the setting signal S33 (N) and the setting signals S33 (1) to (4), a combination of the setting signal S25 (N) and the setting signals S25 (1) to (4), and a setting signal S18 (N ) And the setting signals S18 (1) to (4) are set, a high level signal is input to the bypass terminal (BPS), and the bypass path becomes conductive.

  Here, the power supply voltage VCC0 is supplied to the back gate terminal of the PMOS transistor in the transfer gate TG1. The back gate terminal of the NMOS transistor is connected to the ground potential. Accordingly, the signal applied between the terminals of the transfer gate TG1 under the condition that the voltage value of the power supply voltage VCC0 is higher than the voltage of the internal power supply voltage of the circuit blocks 51 to 54 and the bus line 56. Regardless of the amplitude level, the PN junction does not conduct in the PMOS transistor of the transfer gate TG1. Regardless of the amplitude level of the signal applied to each terminal, an unexpected current path is not formed, and a bypass path can be formed when the signal amplitude level between the terminals is the same potential.

  Note that the level converter (0) 30 is configured to include only the level shift function portion without the bypass function portion. The level shift function part has the same configuration as the level converters (1) 31 to (4) 34 and exhibits the same operations and effects, so the description thereof is omitted here.

  As described above in detail, according to the microcontroller and the power supply method for the microcontroller according to the present embodiment, the internal power supply voltages VR1 to VR4 and VRN are individually supplied to each of the circuit blocks 51 to 54 and the bus line 56. can do. At this time, the voltage values of the internal power supply voltages VR1 to VRN can be individually adjusted by setting from the CPU unit 51 in accordance with the operation state of the microcontroller. For the block in the active state, a high power supply voltage can be supplied to sufficiently bring out the operation performance of the circuit block, and for the block in the dormant state, the low power supply voltage By doing so, unnecessary current consumption can be suppressed. The voltage value of the power supply voltage can be adjusted according to the operating state even during the operation of the microcontroller. Therefore, high-speed and high-functional operation performance is always achieved for microcontrollers with various operating states. It is possible to achieve both low current consumption operation.

The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the present embodiment, a case has been described in which the power supply voltage VCC0 is a 5V power supply, and 3.3V, 2.5V, and 1.8V can be individually set in each regulator unit. However, the present invention is not limited to this. It is not something. Further, various voltage values can be set to be selectable. In addition, it is not always necessary to individually set the voltage value for each circuit block, and a plurality of circuit blocks can be set together.
In the specific example of the regulator unit shown in FIG. 3, the case where the reference voltage generation circuit REG is provided for each regulator unit has been described. However, one circuit is provided as the reference voltage generation circuit REG, and the reference voltage is supplied to each regulator unit. A configuration in which VRF is supplied can also be adopted.

Here, the means for solving the problems in the background art according to the technical idea of the present invention are listed below.
(Supplementary note 1) In a microcontroller comprising a plurality of circuit blocks and a bus connecting the circuit blocks,
A power supply unit that individually supplies a power supply voltage for each of the circuit blocks and the bus;
A microcontroller comprising: a voltage control unit configured to vary an output power supply voltage for each of the power supply units according to an operating state.
(Supplementary Note 2) When interfacing between the circuit blocks or / and between the circuit block and the bus, a determination unit that determines whether the amplitude levels of the signal lines match,
A level converter unit that converts the amplitude level when the determination unit determines that there is a mismatch;
The microcontroller according to appendix 1, further comprising a bypass unit that directly connects the signal lines when the determination unit determines that they match.
(Additional remark 3) The said bypass part is provided with the transfer gate which can apply a voltage independently to a back gate terminal, The microcontroller of Additional remark 2 characterized by the above-mentioned.
(Supplementary Note 4) The microcontroller according to any one of Supplementary Notes 1 to 3, wherein a primary voltage is input to the power supply unit, and the power supply voltage is output as a stepped down voltage.
(Supplementary Note 5) The voltage control unit
A control unit for setting a voltage value to be output by the power supply unit according to the operation state;
A voltage setting storage unit that stores setting information by the control unit;
The microcontroller according to appendix 4, wherein the voltage setting storage unit is supplied with the primary voltage as a power supply voltage.
(Additional remark 6) The said determination part performs a coincidence determination based on the said setting information stored in the said voltage setting storage part, The microcontroller of Additional remark 5 characterized by the above-mentioned.
(Supplementary note 7) A power supply method for a microcontroller comprising a plurality of circuit blocks and a bus connecting the circuit blocks,
Monitoring the operating state of the microcontroller;
A power supply method for a microcontroller, wherein a power supply voltage corresponding to the operation state is individually supplied for each of the circuit block and the bus.

It is a circuit block diagram of an embodiment. It is a circuit part which shows the specific example of a voltage setting register. It is a circuit diagram which shows the specific example of a regulator part. It is a circuit diagram which shows the specific example of a level converter.

2 Voltage setting register units 11 to 14, 1N regulator units (1) to (4), (N)
30 to 34 level converters (0) to (4)
51 CPU 52 Memory 53 Peripheral Circuit (1)
54 Peripheral circuit (2)
55 Signal level adjustment unit 56 Bus lines A1 to A4 AND gate OP1 Operational amplifier REG Reference voltage generation circuits SVR (1) to SVR (4), SVR (N), S18 (x), S25 (x), S33 (x ) (X = 1 to 4, N) Setting signal / ST1 to / ST4, / STN Pause signal VCC0 Power supply voltage VR1 to VR4, VRN Internal power supply voltage VRF Reference voltage

Claims (4)

In a microcontroller comprising a plurality of circuit blocks and a bus connecting the circuit blocks,
A power supply unit that individually supplies a power supply voltage for each of the circuit blocks and the bus;
According to the operation state of the microcontroller, for each of the power supply units, a voltage control unit that makes the output power voltage variable,
When interfacing between the circuit blocks or / and between the circuit block and the bus, the amplitude level of each signal line between the interfaced circuit blocks or / and between the circuit block and the bus A determination unit for performing a match determination;
A level converter unit that converts the amplitude level when the determination unit determines that there is a mismatch;
A microcontroller comprising: a bypass unit that directly connects the signal lines when the determination unit determines that they match . The microcontroller according to claim 1, wherein a primary voltage is input to the power supply unit, and the power supply voltage is output as a stepped down voltage. The voltage controller is
A control unit for setting a voltage value to be output by the power supply unit according to the operation state;
A voltage setting storage unit that stores setting information by the control unit;
The microcontroller according to claim 2 , wherein the primary voltage is supplied as a power supply voltage to the voltage setting storage unit. A power supply method for a microcontroller comprising a plurality of circuit blocks and a bus connecting the circuit blocks,
Supplying a power supply voltage individually for each of the circuit blocks and the bus;
Varying the power supply voltage output in the step of supplying the power supply voltage according to the operating state of the microcontroller;
When interfacing between the circuit blocks or / and between the circuit block and the bus, the amplitude level of each signal line between the interfaced circuit blocks or / and between the circuit block and the bus Performing a match determination;
Converting the amplitude level when it is determined to be inconsistent by the determination step;
A method for supplying power to a microcontroller , comprising: directly connecting the signal lines when it is determined to be coincident in the determining step .

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