KR19980028404A - Method of manufacturing Cmos device - Google Patents
Method of manufacturing Cmos device Download PDFInfo
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- KR19980028404A KR19980028404A KR1019960047453A KR19960047453A KR19980028404A KR 19980028404 A KR19980028404 A KR 19980028404A KR 1019960047453 A KR1019960047453 A KR 1019960047453A KR 19960047453 A KR19960047453 A KR 19960047453A KR 19980028404 A KR19980028404 A KR 19980028404A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 22
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims description 42
- 230000000694 effects Effects 0.000 abstract description 7
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 25
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 101000831940 Homo sapiens Stathmin Proteins 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 102100024237 Stathmin Human genes 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Abstract
본 발명은 CMOS 소자에 관한 것으로, 특히 공정 단순화 및 숏 채널(Short Channel Effect)효과를 개선하기에 적당한 CMOS 소자의 제조방법에 관한 것이다.The present invention relates to a CMOS device, and more particularly, to a method of manufacturing a CMOS device suitable for improving process simplification and short channel effect.
이를위한 본 발명의 CMOS 소자의 제조방법은 제 1 도전형 반도체 기판에 선택적으로 제 1 도전형 웰 및 제 2 도전형 웰을 형성하는 공정과 상기 제 2 도전형 웰 영역에 펀치스루 방지용 제 2 도전형 제 1 매몰층을 형성하는 공정과 상기 제1 도전형 웰 및 제 2 도전형 웰 영역의 표면에 문턱전압 조절용 제 1 도전형 제 1매몰층 및 제 2 도전형 제 2 매몰층을 형성하는 공정과 상기 제 1 도전형 웰 및 제 2 도전형 웰에 선택적으로 게이트 전극을 형성하는 공정과 상기 제 1 도전형 웰 영역에 게이트 전극 밑으로 저농도 제 1 도전형 불순물 영역과 제 1 도전형 할로영역을 형성하는 공정과 상기 제 2 도전형 웰 영역에 게이트 전극 밑으로 저농도 제 2 도전형 불순물 영역과 제 2 도전형 할로영역을 형성하는 공정과 상기 게이트 측면에 제 1 절연막 측벽을 형성하는 공정과 상기 제 1 도전형 웰 영역에 제 1 절연막 측벽 밑으로 고농도 제 1 불순물 영역을 형성하는 공정과 상기 제 2 도전형 웰 영역에 측벽 스페이서 밑으로 고농도 제 2 불순물 영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.A method for fabricating a CMOS device includes forming a first conductivity type well and a second conductivity type well in a first conductivity type semiconductor substrate, forming a second conductivity type well in the second conductivity type well region, Forming a first buried layer for a threshold voltage and a second buried layer for a second conductivity type on a surface of the first conductive type well and the second conductive type well region; Forming a first conductive type impurity region and a first conductive type halo region under the gate electrode in the first conductive type well region, forming a first conductive type well region and a second conductive type well region, Forming a second conductive type impurity region and a second conductive type halo region below the gate electrode in the second conductive type well region; forming a sidewall of the first insulating film on the side surface of the gate; Forming a high-concentration first impurity region below the sidewalls of the first insulating film in the first conductive type well region and forming a second high-concentration impurity region below the sidewall spacer in the second conductive type well region; .
Description
본 발명은 CMOS 소자에 관한 것으로, 특히 공정 단순화 및 숏 채널(Short Channel Effect)효과를 개선하기에 적당한 CMOS 소자의 제조방법에 관한 것이다.The present invention relates to a CMOS device, and more particularly, to a method of manufacturing a CMOS device suitable for improving process simplification and short channel effect.
일반적으로 CMOS 소자는 p채널 MOS FET와 n채널 MOS FET를 하나의 칩속에 구성하여 상보동작(Complementary) 시키도록 한 것이다.Generally, a CMOS device is formed by arranging a p-channel MOS FET and an n-channel MOS FET in a single chip so as to be complementary.
상기 소자는 이온주입(Ion-implantation) 기술의 실용화로 가능해졌으며 소비전력이 낮고 바이폴라(Bipolar) 소자에 가까운 고속동작이 가능하여 메가비트급이 주류를 이루고 있다.The device is made possible by the practical use of ion-implantation technology, and the megabit class is mainstream because of its low power consumption and high-speed operation close to that of a bipolar device.
모스(MOS : Metal 0xide Semiconductor) 소자의 고집적화 및 고속화를 위해 점차로 소자의 크기, 그중에서 채널(Channel)의 길이를 줄여 매우 적게 제조하였다.In order to increase the integration and the speed of MOS (Metal Oxide Semiconductor) devices, the size of the device and the length of the channel have been reduced to be very small.
모스 트랜지스터의 미세화는 스케일링(Scaling) 원칙을 지표로 진행된다. 즉, 스케일링 팩터를 K라 하면 소자(Device)의 가로 방향, 세로 방향 치수를 K만큼 축소함과 동시에 기판 불순물 농도를 K만큼 증가시키고 소오스/드레인 깊이는 K만큼 감소한다.The miniaturization of the MOS transistor proceeds as a scaling principle. That is, if the scaling factor is K, the horizontal and vertical dimensions of the device are reduced by K, the substrate impurity concentration is increased by K, and the source / drain depth is reduced by K.
이 경우 내부관계를 유지하기 위해 전원전압을 K만큼 낮춤으로써 디바이스의 특성을 열화 시키는 일없이 고집적 소자로서의 신호전달 지연시간을 K만큼 감소하고 전력소비는 K2만큼 감소시킬수 있다.In this case, by lowering the power supply voltage by K in order to maintain the internal relation, the signal transmission delay time as a highly integrated device can be reduced by K and the power consumption can be reduced by K 2 without deteriorating the characteristics of the device.
그러나, 실제로는 시스템(System)과의 정합성 때문에 전원전압은 일정한 상태로 소자의 미세화가 진행되고 있다.However, in reality, due to the compatibility with the system, the power supply voltage is kept constant and the device is being miniaturized.
그 결과 채널길이의 축소(Short Channel)에 따른 드레인 공핍영역의 증가에 따라 채널접합과 상호 작용하여 전위장벽을 낮추는 드레인 유기장벽 감소(DIBL : Drain Induced Barrier Lowering)의 문제가 발생한다.As a result, there arises a problem of Drain Induced Barrier Lowering (DIBL) which lowers the potential barrier by interacting with the channel junction in accordance with the increase of the drain depletion region due to the reduction of the channel length (Short Channel).
또한, 소오스와 드레인 공핍영역의 침투가 심해져 두 공핍영역이 만나는 펀치스루(Punch Through) 효과가 발생하여 누설(Leakage) 전류가 증가한다.In addition, the penetration of the source and drain depletion regions becomes severe, and a punch through effect in which the two depletion regions meet causes a leakage current to increase.
그러한, 숏 채널 효과에 의한 드레인 유기장벽 감소 및 펀치스루 효과에 대한 방지책으로 채널의 깊은 영역에 대한 임계전압(Threshold Voltage) 조절이온 및 펀치스루 방지용 이온주입이 필요하게 되었다.As a countermeasure against the reduction of the drain organic barrier due to the short channel effect and the prevention of the punch through effect, ion implantation for controlling the threshold voltage for the deep region of the channel and for preventing punchthrough has been required.
그리고, 임계전압 조절이온 및 펀치스루 방지용 이온으로 인해 발생하는 전류구동력 저하도 해결해야할 문제이다.Also, the current driving force reduction caused by ions for preventing threshold voltage adjustment and ions for preventing punchthrough is a problem to be solved.
이하, 첨부된 도면을 참조하여 종래의 CMOS 소자 제조방법을 설명하면 다음과 같다.Hereinafter, a conventional CMOS device manufacturing method will be described with reference to the accompanying drawings.
도 1a 내지 도 1k는 종래의 CMOS 소자 제조방법을 나타낸 공정 단면도이다. 먼저, 도 1a에 도시한 바와같이 반도체 기판(1)의 특정영역에 활성영역(Active) 이외의 부분에 LOCOS 또는 STI (Shallow Trench Isolation) 공정으로 소자격리층으로 이용되는 필드 산화막(2)을 형성한다.FIGS. 1A to 1K are process cross-sectional views illustrating a conventional method of manufacturing a CMOS device. First, as shown in FIG. 1A, a field oxide film 2 used as a device isolation layer in a LOCOS or STI (Shallow Trench Isolation) process is formed in a specific region of the semiconductor substrate 1 in a portion other than the active region Active do.
이어, 도 1b에 도시한 바와같이 상기 반도체 기판(1)에 선택적으로 p형 웰(3)과 n형 웰(4)을 형성한다.Then, the p-type well 3 and the n-type well 4 are selectively formed in the semiconductor substrate 1 as shown in FIG. 1B.
이때, p형 웰(3) 영역에 B(Boron)이온을 주입하고, n형 웰(4) 영역에 P(Phosphorus)이온을 주입한다. 그리고 p형 웰(3)과 n형 웰(4) 형성시 열처리를 하며, 열처리시 온도는 1000∼1100℃이다.At this time, B (Boron) ions are implanted into the p-type well 3 region and P (Phosphorus) ions are implanted into the n-type well 4 region. Then, the p-type well 3 and the n-type well 4 are heat-treated at a temperature of 1000 to 1100 ° C.
이어서, 도 1c에 도시한 바와같이 필드 산화막(2)을 제외한 p형 웰(3) 영역과 n형 웰(4)상에 패드 산화막(5)을 형성한 후, 기판(1) 전면에 포토레지스트를 형성하고 상기 n형 웰(4) 영역에만 남도록 패터닝하여 제 1 포토레지스트 패턴(PR1)을 형성한다.1C, a pad oxide film 5 is formed on the p-type well 3 and the n-type well 4 except for the field oxide film 2. Thereafter, And is patterned to remain only in the region of the n-type well 4 to form a first photoresist pattern PR1.
그리고 p형 웰(3) 영역내에 p형 펀치스루 방지용 불순물 이온 및 문턱전압 조절용 불순물 이온을 주입하여 p형 제 1 매몰층(6) 및 p형 제 2 매몰층(7)을 차례로 형성한다. 이때, p형 제 1 매몰층(6)은 펀치스루(punch Through) 현상을 방지하기 위한 것으로 p형 제 2 매몰층(7) 보다 p형 웰(3) 영역내에 깊이 형성한다.Then, p-type punch-through preventing impurity ions and threshold voltage controlling impurity ions are implanted into the p-type well 3 region to form a first p-type buried layer 6 and a second p-type buried layer 7 in this order. At this time, the p-type first buried layer 6 is formed deep within the region of the p-type well 3 rather than the p-type second buried layer 7 in order to prevent punch through phenomenon.
또한, p형 제 2 매몰층(7)에 주입하는 이온은 BF2이온이고, 패드 산화막(5)의 두께는 100∼200Å이다.The ions implanted into the p-type second buried layer 7 are BF 2 ions, and the thickness of the pad oxide film 5 is 100 to 200 Å.
이어, 도 1d에 도시한 바와같이 상기 제 1 포토레지스트 패턴(PR1)을 제거한후, p형 웰(3) 영역에만 남도록 제 2 포토레지스트 패턴(PR2)을 형성하여 n형 웰(4) 영역내에 n형 펀치스루 방지용 이온을 주입하여 n형 제 1 매몰층(8)을 형성하고, n형 문턱전압 조절용 이온을 주입하여 n형 제 2 매몰층(9)을 형성한다.After the first photoresist pattern PR1 is removed as shown in FIG. 1D, a second photoresist pattern PR2 is formed so as to remain only in the p-type well 3 region, the n-type first buried layer 8 is formed by injecting ions for preventing n-type punchthrough, and the n-type second buried layer 9 is formed by implanting ions for controlling the n-type threshold voltage.
이때, n형 제 1 매몰층(8)은 n형 제 2 매몰층(9) 보다 n형 웰(4) 영역내에 깊이 형성한다.At this time, the n-type first buried layer 8 is formed deeply in the n-type well 4 region than the n-type second buried layer 9.
그리고 상기 n형 제 1 매몰층(8) 주입하는 이온으로는 As이고, n형 제 2 매몰층(9)에 주입하는 이온은 BF2이다.The ions to be implanted into the n-type first buried layer 8 are As and the ions to be implanted into the n-type buried layer 9 are BF 2 .
이어서, 도 1e에 도시한 바와같이 상기 제 2 포토레지스트 패턴(PR2)을 제거한 후, 패드 산화막(5)을 제거한다. 그리고 기판(1) 전면에 게이트 산화막(10), 폴리 실리콘층 및 캡 질화막(12)을 차례로 형성하고 선택적으로 패터닝(포토리소그래피 공정과 식각공정)하여 게이트 전극(11a,11b)을 형성한다.Next, as shown in FIG. 1E, the second photoresist pattern PR2 is removed, and then the pad oxide film 5 is removed. Then, a gate oxide film 10, a polysilicon layer and a cap nitride film 12 are sequentially formed on the entire surface of the substrate 1 and the gate electrodes 11a and 11b are formed by selective patterning (photolithography process and etching process).
이어, 도 1f에 도시한 바와같이 n형 웰(4) 영역에 제 3 포토레지스트 패턴(PR3)을 형성하고, 상기 게이트 전극(11a)을 마스크로 하여 노출된 p형 웰(3) 영역에 저농도 n불순물 이온을 주입하여 n형 LDD 영역(13)을 형성한다.Next, as shown in FIG. 1F, a third photoresist pattern PR3 is formed in the region of the n-type well 4, and a lightly doped region 3 is formed in the exposed region of the p-type well 3 using the gate electrode 11a as a mask. n impurity ions are implanted to form the n-type LDD region 13.
이어서, 도 1g에 도시한 바와같이 상기 제 3 포토레지스트 패턴(PR3)을 제거한 후, p형 웰(3) 영역에 제 4 포토레지스트 패턴(PR4)을 형성한다.Next, as shown in FIG. 1G, after the third photoresist pattern PR3 is removed, a fourth photoresist pattern PR4 is formed in the p-type well 3 region.
그리고 노출된 n형 웰(4) 영역에 게이트 전극(11b)을 마스크로 하여 저농도 p형 불순물 이온을 주입하여 p형 LDD 영역(14)을 형성한다.The p-type LDD region 14 is formed by implanting low-concentration p-type impurity ions in the exposed n-type well 4 region using the gate electrode 11b as a mask.
이어, 도 1h에 도시한 바와같이 상기 제 4 포토레지스트 패턴(PR4)을 제거하고, 게이트 전극(11a)(11b)을 포함한 전면에 절연막을 증착한 다음 에치백 하여 게이트 전극(11a) (11b) 측면에 절연막 측벽(15a)(15b)을 형성한다. 이때, 절연막 측벽(15a,15b) 은 질화막을 사용한다.Next, as shown in FIG. 1H, the fourth photoresist pattern PR4 is removed, an insulating film is deposited on the entire surface including the gate electrodes 11a and 11b, and then the gate electrodes 11a and 11b are etched back, Insulating film side walls 15a and 15b are formed on the side surfaces. At this time, the insulating film side walls 15a and 15b use a nitride film.
이어서, 도 1i에 도시한 바와같이 n형 웰(4) 영역에 제 5 포토레지스트 패턴(PR5)을 형성하고, 노출된 p형 웰(3) 영역에 절연막 측벽(15a)을 마스크로하여 고농도 n형 불순물 이온을 주입하여 n형 소오스/드레인 영역(16)을 형성한다.Next, as shown in FIG. 1I, a fifth photoresist pattern PR5 is formed in the n-type well 4 region, and a high concentration n (n) is formed in the exposed p-type well 3 region using the insulating film side wall 15a as a mask Type impurity ions are implanted to form an n-type source / drain region 16.
이어, 도 1j에 도시한 바와같이 제 5 포토레지스트 패턴(PR5)을 제거하고, p형 웰(3) 영역에 제 6 포토레지스트 패턴(PR6)을 형성한다.Next, as shown in FIG. 1J, the fifth photoresist pattern PR5 is removed and a sixth photoresist pattern PR6 is formed in the p-type well 3 region.
그리고 노출된 n형 웰(4) 영역에 절연막 측벽(15b)을 마스크로하여 고농도 p형 불순물 이온을 주입하여 p형 소오스/드레인 영역(17)을 형성한다.The p-type source / drain region 17 is formed by implanting high-concentration p-type impurity ions using the insulating film side wall 15b as a mask in the exposed n-type well 4 region.
이어서, 도 1k에 도시한 바와같이 상기 제 6 포토레지스트 패턴(PR6)을 제거하여 기판(1)에 두개의 웰(p형 웰, n형 웰)을 가진 CMOS 소자 제조공정을 완성한다.Next, as shown in FIG. 1K, the sixth photoresist pattern PR6 is removed to complete a CMOS device fabrication process having two wells (p-type well, n-type well) on the substrate 1.
그러나 상기와 같은 종래의 CMOS 소자 제조방법은 다음과 같은 문제점이 있었다.However, the conventional method of manufacturing a CMOS device has the following problems.
첫째, p형 웰과 n형 웰 영역에 각각의 채널을 형성하기 위한 포토레지스트공정이 두번 이루어지므로 공정이 복잡하다.First, the photoresist process for forming the respective channels in the p-type well and the n-type well regions is performed twice, complicating the process.
둘째, p형 웰 채널 형성후 포토레지스를 제거시 패드 산화막도 일부 식각되므로, n형 웰에 문턱전압을 위한 이온주입 공정시 p형 웰과 n형 웰에 주입되는 불순물량이 달라져서 문턱전압의 변화가 있게된다.Secondly, when the photoresist is removed after forming the p-type well channel, the pad oxide film is partially etched. Therefore, the amount of impurities implanted into the p-type well and the n-type well differs during the ion implantation process for the threshold voltage in the n- .
셋째, n형 웰에 숏 채널을 형성하기 위해 펀치스루 방지용 이온주입되는 As의 불순물량이 커야하는데 이럴경우 소오스/드레인간의 누절전류와 게이트와 드레인간의 누설전류가 증가하여 소자의 특성을 저하시킨다.Third, in order to form a short channel in the n-type well, the impurity amount of As ions to be ion-implanted for punchthrough prevention must be large. In this case, the leakage current between the source and the drain and the leakage current between the gate and drain are increased to deteriorate the characteristics of the device.
본 발명은 이와같은 문제점을 해결하기 위하여 안출한 것으로, p형 웰과 n형웰 동시에 문턱전압 조절을 위한 블랭킷(Blanket) 매몰층을 형성하여 공정의 단순화 및 n형 웰에 숏 채널 효과을 개선하여 문턱전압 변화를 최소 하는데 적당한 CMOS 소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, comprising: forming a blanket buried layer for controlling a threshold voltage simultaneously with a p- And it is an object of the present invention to provide a method of manufacturing a CMOS device suitable for minimizing variations.
도 1a 내지 도 1k는 종래의 CMOS 소자의 제조공정 단면도Figs. 1A to 1K are cross-sectional views of a conventional CMOS device manufacturing process
도 2a 내지 도 2j는 본 발명의 CMOS소자의 제조공정 단면도2A to 2J are cross-sectional views of a manufacturing process of a CMOS device of the present invention
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
20 : 반도체 기판 21 : 필드 산화막20: semiconductor substrate 21: field oxide film
22 : p형 웰 영역 23 : n형 웰영역22: p-type well region 23: n-type well region
24 : n형 제 1 매몰층 25 : 패드 산화막24: n-type first buried layer 25: pad oxide film
26a : p형 제 1 매몰층 26b : n형 제 2 매몰층26a: p-type first buried layer 26b: n-type second buried layer
27 : 게이트 산화막 28a,28b : 게이트 전극27: gate oxide film 28a, 28b: gate electrode
29 : 캡 질화막 30 : p형 LDD 영역29: cap nitride film 30: p-type LDD region
31 : p형 할로영역 32 : n형 LDD 영역31: p-type halo region 32: n-type LDD region
33 : n형 할로영역 34a,34b : 절연막 측벽33: n-type halo regions 34a and 34b:
35 : p형 소오스/드레인 영역 36 : n형 소오스/드레인 영역35: p-type source / drain region 36: n-type source / drain region
상기의 목적을 달성하기 위한 본 발명의 CMOS 소자의 제조방법은 반도체 기판에 선택적으로 제 1 도전형 웰 및 제 2 도전형 웰을 형성하는 공정과, 상기 제 2도전형 웰 영역에 편치스루 방지용 제 2 도전형 제 1 매몰층을 형성하는 공정과, 상기 제 1 도전형 웰 및 제 2 도전형 웰 영역의 표면에 문턱전압 조절용 제 1 도전형 제 1 매몰층 및 제 2 도전형 제 2 매몰층을 형성하는 공정과, 상기 제 1 도전형 웰 및 제 2 도전형 웰에 선택적으로 게이트 전극을 형성하는 공정과, 상기 제 1 도전형 웰 영역에 게이트 전극 밑으로 저농도 제 1 도전형 불순물 영역과 제 1 도전형 할로영역을 형성하는 공정과, 상기 제 2 도전형 웰 영역에 게이트 전극 밑으로 저농도 제 2 도전형 불순물 영역과 제 2 도전형 할로영역을 형성하는 공정과, 상기게이트 측면에 제 1 절연막 측벽을 형성하는 공정과, 상기 제 1 도전형 웰 영역에 제 1 절연막 측벽 밑으로 고농도 제 1 불순물 영역을 형성하는 공정과, 상기 제 2도전형 웰 영역에 제 1 절연막 측벽 밑으로 고농도 제 2 불순물 영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.According to another aspect of the present invention, there is provided a method for fabricating a CMOS device, the method including forming a first conductive well and a second conductive well on a semiconductor substrate, Forming a first buried layer for controlling a threshold voltage and a second buried layer for a second conductivity type on a surface of the first conductive type well and the second conductive type well region; Forming a gate electrode on the first conductive type well and selectively forming a gate electrode on the first conductive type well and the second conductive type well; Forming a second conductive type impurity region and a second conductive type halo region under the gate electrode in the second conductive type well region; Type Forming a first high impurity concentration region under the sidewalls of the first insulating film in the first conductivity type well region; and forming a second high impurity concentration region below the sidewalls of the first insulating film in the second conductivity type well region And a step of forming a metal layer on the substrate.
이하, 첨부된 도면을 참조하여 본 발명의 CMOS 소자의 제조방법에 대하여 보다 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a CMOS device of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2j는 본 발명의 CMOS 소자의 제조공정을 나타낸 공정 단면도이다.2A to 2J are cross-sectional views illustrating a process for manufacturing a CMOS device of the present invention.
먼저, 도 2a에 도시한 바와같이 반도체 기판(20)의 특정영역에 활성영역(Active) 이외의 부분에 LOCOS 또는 STI(Shallow Trench Isolation) 공정으로 소자격리층으로 이용되는 필드 산화막(21)을 형성한다.First, as shown in FIG. 2A, a field oxide film 21 used as a device isolation layer is formed in a specific region of the semiconductor substrate 20 by a LOCOS or STI (Shallow Trench Isolation) process in a portion other than the active region Active do.
이어, 도 2b에 도시한 바와같이 상기 반도체 기판(20)에 선택적으로 p형 웰(22)과 n형 웰(23)을 형성한다. 그리고 상기 p형 웰(22) 영역내에 p형 펀치스루 방지용 불순물 이온을 주입하여 p형 제 1 매몰층(24)을 형성한다.Next, as shown in FIG. 2B, the p-type well 22 and the n-type well 23 are selectively formed in the semiconductor substrate 20. The p-type first buried layer 24 is formed by implanting impurity ions for preventing p-type punch through into the p-type well 22 region.
이때 p형 웰(22) 영역에 B(Boron)이온을 주입하고, n형 웰(23) 영역에 P(Phosphorus)이온을 주입한다. 또한 p형 웰(22)과 u형 웰(23) 형성시 열처리를 하며, 열처리시 온도는 1000∼1100℃이다.At this time, B (Boron) ions are implanted into the p-type well 22 and P (Phosphorus) ions are implanted into the n-type well 23. Type well 23 and the p-type well 22 and the u-type well 23, and the temperature during the heat treatment is 1000 to 1100 占 폚.
그리고 p형 제 1 매몰층(24)은 펀치스루 현상을 방지하기 위한 것으로, p형 제 1 매몰층(24)에 주입하는 이온은 As 이온이며, As 이온의 에너지는 80∼120KeV, 불순물량은 1.0*1012~1.0*1013㎝-2이다.The p-type first buried layer 24 is for preventing punch through phenomenon. The ions injected into the p-type first buried layer 24 are As ions, the energy of As ions is 80 to 120 KeV, the amount of impurities is 1.0 * 10 12 - 1.0 * 10 13 cm -2 .
이어, 도 2c에 도시한 바와같이 상기 제 1 포토레지스트 패턴(PR20)을 제거한 후, 필드 산화막(21)을 제외한 p형 웰(22) 영역과 n형 웰(23) 영역에 패드 산화막(25)을 형성하고, p형 웰(22) 영역과 n형 웰(23) 영역에 문턱전압 조절용 이온을 주입하여 p형 웰(22) 영역 표면에 p형 제 1 매몰층(26a) 및 n형 웰(23) 영역 표면에 n형 제 2 매몰층(26b)을 형성한다.2C, a pad oxide film 25 is formed on the p-type well 22 and the n-type well 23 except for the field oxide film 21 after removing the first photoresist pattern PR20. And a threshold voltage adjusting ion is implanted into the p-type well 22 and the n-type well 23 to form a p-type first buried layer 26a and an n-type well 23 on the surface of the p- 23) region on the surface of the n-type second buried layer 26b.
이때, 문턱전압 조절용 이온을 블랭킷(Blanket) 불순물이라 하며, p형 제 1매몰층(26a) 및 n형 제 2 매몰층(26a)에 주입하는 이온은 BF2이온이다. 그리고 패드 산화막(25)의 두께는 100∼200Å이고, n형 제 2 매몰층(26b)은 상기 n형 제 1매몰층(24)보다 n형 웰(23) 영역 표면에 형성한다.At this time, the threshold voltage controlling ion is referred to as a blanket impurity. The ions injected into the p-type first buried layer 26a and the n-type second buried layer 26a are BF 2 ions. The thickness of the pad oxide film 25 is 100 to 200 angstroms and the n-type second buried layer 26b is formed on the surface of the n-type well 23 region than the n-type first buried layer 24.
이어, 도 2d에 도시한 바와같이 상기 패드 산화막(25)을 제거하고, 기판(20) 전면에 게이트 산화막(27), 폴리 실리콘층 및 캡 질화막(29)을 차례로 형성한 후 선택적으로 패터닝하여 게이트 전극(28a)(28b)을 형성한다.2D, the pad oxide film 25 is removed and a gate oxide film 27, a polysilicon layer and a cap nitride film 29 are sequentially formed on the entire surface of the substrate 20, Thereby forming electrodes 28a and 28b.
이어서 도 2e에 도시한 바와같이, n형 웰(23) 영역에 제 2 포토레지스트 패턴(PR21)을 형성한 후 상기 게이트 전극(28a)을 마스크로 하여 노출된 p형 웰(22)영역에 저농도 p형 불순물 이온을 주입하여 LDD 영역(30)을 형성한다. 그리고 상기 노출된 p형 웰(23) 영역에 n형 불순물 이온을 주입하여 p형 할로영역(31)을 형성한다.Next, as shown in FIG. 2E, a second photoresist pattern PR21 is formed in the n-type well 23 region, and then a low concentration n-type impurity is implanted into the exposed p-type well 22 using the gate electrode 28a as a mask p-type impurity ions are implanted to form the LDD region 30. [ Then, n-type impurity ions are implanted into the exposed p-type well 23 region to form a p-type halo region 31.
이때, 할로영역(31)은 n형 불순물 이온으로 형성하므로 상기 LDD영역(30) 보다 바깥쪽에 형성한다.At this time, since the halo region 31 is formed of n-type impurity ions, the halo region 31 is formed outside the LDD region 30.
이어, 도 2f에 도시한 바와같이, 상기 제 2 포토레지스트 패턴(PR21)을 제거한 후, p형 웰(22) 영역에 제 3 포토레지스트 패턴(PR22)을 형성한다. 그리고 노출된 n형 웰(23) 영역에 게이트 전극(28b)을 마스크로 하여 저농도 n형 불순물 이온을 주입하여 LDD 영역(32)을 형성하고, 상기 노출된 n형 웰(23) 영역에 p형 불순물 이온을 주입하여 n형 할로영역(33)을 형성한다.Next, as shown in FIG. 2F, after the second photoresist pattern PR21 is removed, a third photoresist pattern PR22 is formed in the p-type well 22 region. Thereafter, low-concentration n-type impurity ions are implanted into the exposed n-type well 23 using the gate electrode 28b as a mask to form an LDD region 32. In the exposed n-type well 23, Impurity ions are implanted to form the n-type halo region 33.
이때, 할로영역(33)은 p형 불순물 이온으로 형성하므로 상기 LDD영역(32)보다 바깥쪽에 형성한다.At this time, the halo region 33 is formed outside the LDD region 32 because it is formed of p-type impurity ions.
이어, 도 2g에 도시한 바와같이 상기 제 3 포토레지스트 패턴(PR22)을 제거한 후, 게이트 전극(28a)(28b)을 포함한 전면에 절연막을 증착한 다음 에치백하여 게이트 전극(28a) (28b) 측면에 절연막 측벽(34a) (34b)를 형성한다.Next, as shown in FIG. 2G, the third photoresist pattern PR22 is removed, an insulating film is deposited on the entire surface including the gate electrodes 28a and 28b, and then the gate electrodes 28a and 28b are removed. Insulating film side walls 34a and 34b are formed on the side surfaces.
이때, 절연막 측벽(34a)(34b)은 질화막을 사용한다.At this time, the insulating film side walls 34a and 34b use a nitride film.
이어서, 도 2h에 도시한 바와같이 n형 웰(23) 영역에 제 4 포토레지스트 패턴(PR23)을 형성하고, 노출된 p형 웰(22) 영역에 절연막 측벽(34a)을 마스크로 하여 고농도 p형 불순물 이온을 주입하여 소오스/드레인 영역(35)을 형성한다.Next, as shown in FIG. 2H, a fourth photoresist pattern PR23 is formed in the n-type well 23 and a high concentration p (n) is formed in the exposed p-type well 22 region using the insulating film side wall 34a as a mask -Type impurity ions are implanted to form the source / drain regions 35.
이어, 도 2i에 도시한 바와같이 상기 제 4 포토레지스트 패턴(PR23)을 제거한 후, p형 웰(23) 영역에 제 5 포토레지스트 패턴(PR24)을 형성한다. 그리고 노출된 n형 웰(23) 영역에 절연막 측벽(34b)을 마스크로 하여 고농도 n형 불순물 이온을 주입하여 소오스/드레인 영역(36)을 형성한다.Next, as shown in FIG. 2I, after the fourth photoresist pattern PR23 is removed, a fifth photoresist pattern PR24 is formed in the p-type well 23 region. Then, high-concentration n-type impurity ions are implanted into the exposed n-type well 23 using the insulating film side wall 34b as a mask to form the source / drain region 36. [
이어서, 도 2j에 도시한 바와같이 상기 제 5 포토레지스트 패턴(PR24)을 제기하여 기판(20)에 두개의 웰(p형 웰, n형 웰)을 가진 CMOS 소자 제조공정을 완성한다.Next, as shown in FIG. 2J, the fifth photoresist pattern PR24 is formed to complete a CMOS device fabrication process having two wells (p-type well, n-type well) on the substrate 20.
이상에서 설명한 바와같이 본 발명의 CMOS 소자의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of manufacturing a CMOS device of the present invention has the following effects.
첫째, p형 웰과 n형 웰 각각의 채널 형성하기 위한 포토레지스트 공정의 생략으로 공정이 단순화된다.First, the process is simplified by omitting the photoresist process for forming the channel of each of the p-type well and the n-type well.
둘째, 동시에 p형 웰 영역과 n형 웰 영역내에 문턱전압 조절용 블랭킷 매몰층을 형성하므로 포토레지스트 공정이 필요없다. 따라서 패드 산화막의 두께 변화가 없어 p형 웰과 n형 웰에 주입되는 문턱전압 조절용 불순물량의 변화가 없다.Secondly, a photoresist process is not necessary because a burying buried layer for threshold voltage adjustment is formed in the p-type well region and the n-type well region at the same time. Therefore, there is no change in the pad oxide film thickness and there is no change in the amount of impurity for controlling the threshold voltage to be injected into the p-type well and the n-type well.
셋째, p형 웰 영역에 As 이온을 사용한 펀치스루 방지용 매몰층와 n형 불순물을 사용한 할로영역으로 숏 채널 효과를 개선하고, 소오스/드레인 간의 누절전류를 감소시킨다.Third, the short channel effect is improved in the p-type well region using the buried layer for preventing punch-through using As ions and the halo region using the n-type impurity, and the leakage current between the source and the drain is reduced.
Claims (6)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100778862B1 (en) * | 2006-12-12 | 2007-11-22 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for manufacturing the same |
| KR100794094B1 (en) * | 2001-12-28 | 2008-01-10 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100794094B1 (en) * | 2001-12-28 | 2008-01-10 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
| KR100778862B1 (en) * | 2006-12-12 | 2007-11-22 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for manufacturing the same |
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