KR19980026504A - Low Decoder in Nonvolatile Semiconductor Memory Devices - Google Patents

Abstract

The present invention relates to a flash memory device, and more particularly, to a row decoder of a flash memory device for selecting and driving a word line in a memory cell array. A row decoder of a nonvolatile semiconductor memory device for selecting a word line in a memory cell array and driving the word line at a voltage required for reading, programming, erasing, and margin mode tests. An input unit for outputting a combined signal in response thereto; In response to the combined signal output from the input unit and the cut-off voltage and external voltages applied from the outside, the cut-off voltage of the power supply voltage level and the external voltage of the power supply voltage level and each operation mode during read operation, program operation, and margin mode operation. Outputting the external voltage in response to the external voltage at a predetermined voltage level required for the word line, and in response to the external voltage at the ground voltage level and the cutoff voltage and the external voltage at the erase voltage level. An output high voltage level transfer unit; The signal output from the high voltage level transfer unit and the external voltages are input, and in response thereto, when the output signal of the high voltage level transfer unit is high level in each operation mode, the external voltage applied in each operation mode is output and is low level. An inverting unit for outputting the external voltage applied in each operation mode during the operation; Each of the signals output from the high voltage level transfer unit and the inverting unit, the external voltages and the word line selection signal are inputted, and when the read operation is performed, the external voltage of the power supply voltage level and the external voltage of the ground voltage level and the boosting voltage level Outputting the boosting voltage in response to a voltage and a word line selection signal, and in response to the cut-off voltage of a power supply voltage level and the external voltage of a ground voltage level and the external voltage and a word line selection signal of a program voltage level during a program operation. Outputting the program voltage and outputting an erase voltage in response to the external voltage of the ground contact level, the word line selection signal, and the external voltage of the cutoff voltage and the erase voltage level during an erase operation; The breaking voltage of the level and the external voltage of the ground voltage level and the boosting voltage level of the In response to the negative voltage to a word line selection signal having a predetermined voltage level that requires the time of a test includes a plurality of word line selection and a driver for outputting a predetermined voltage level during the test.

Description

Row decoder of non volatile semicondutor memory device

The present invention relates to a flash memory device, and more particularly, to a row decoder of a flash memory device for selecting and driving a word line in a memory cell array.

In the case of a nonvolatile semiconductor memory device, particularly a flash memory device, which is one of the semiconductor memory devices, a state of a memory cell may be electrically programmed and erased. In this case, various voltages are required to perform the program or erase operation of the memory cell. The memory cell array includes a plurality of cells having a NAND structure, which is also referred to as a string or a NAND cell unit. The NAND cell unit includes memory cells connected in series between a second select transistor connected to a common source line corresponding to a source and a first select transistor connected to a bit line corresponding to a drain, and each memory cell is controlled. It has a gate and a floating gate. Each control gate of the memory cells is connected to a word line corresponding to the control gate, and the voltage for controlling the same is not only in the case of the read mode, the program mode, and the erase mode, but also in the case of the selected memory cell array block and the unselected memory cell array block. Accordingly, various voltages are used, such as negative high voltage and positive high voltage. The row decoder must be able to select the desired word lines in each mode and drive each word line at the voltage level required for each mode operation on the selected word line and the unselected word line.

1 is a circuit diagram illustrating a circuit of a row decoder of a conventional nonvolatile semiconductor memory device.

The memory cell array of the nonvolatile semiconductor memory device includes a plurality of memory cell array blocks, and each of the memory cell array blocks includes a plurality of row decoders shown in FIG. 1. Each row decoder includes a plurality of word line selection and driving units 18 for selecting and driving a plurality of word lines, and the row decoder illustrated in FIG. 1 is configured to select eight word lines. will be. The row decoder consists of an input 12 and a plurality of word line selection and drivers 18. The input unit 12 includes a NAND gate G1 and an NMOS transistor, and the NAND gate G1 receives external addresses Pi and Qi applied from the outside, and in response thereto, states of the external addresses Pi and Qi. Therefore, the combined signal S_C of a predetermined level is output to one terminal of the NMOS transistor MN1.

The NMOS transistor MN1 has an input terminal to which a source-drain channel is connected between an output terminal of the NAND gate G1 and an input terminal of each word line selector and driver 18, and to which a cutoff voltage shut-off is applied from the outside. The gate is connected to 3). When the blocking voltage shut-off is applied to the gate of the NMOS transistor, the predetermined voltage output from the NAND gate G1 is transmitted to each word line selection and driver 18 in response thereto. In addition, the word line selection and driving unit 18 is used as a reverse flow prevention transistor for blocking a high voltage from flowing back to the output terminal of the NAND gate G1. Here, the external addresses Pi and Qi are applied at a high level when selected, and the NAND gate G1 of the input unit 12 may be formed as a NOR gate or another logic gate.

Each word line selector driver 18 includes PMOS transistors MP1, MP2, and MP3 and NMOS transistors MN2 and MN3, and external voltages VPXi applied to different voltage levels in each operation mode from the outside; VEXi and Si are input through the first, second and third power supply terminals 1, 2 and 4, respectively. That is, in the read and program modes, the external voltages VPXi, VEXi, and Si are respectively supplied with a boosting voltage VPR, 0 volts, and the boosting voltage VPR, and a low level is output through the input unit 12 of the selected row decoder. As a result, the NMOS transistor MN2 and the PMOS transistor MP3 are turned on to apply the necessary voltage in each operation mode to the selected word line. In the erase mode, the external voltages VPXi, VEXi, and Si are applied with an erase voltage VERS of 0 volts, -10 volts, and 0 volts, respectively, so that the NMOS transistor MN3 is turned on so that the erase voltage is applied to all word lines. -10 volts is applied.

Each operation in the read mode, the program mode, and the erase mode of the semiconductor memory device will be described based on the row decoder of the semiconductor memory device shown in FIG. 1.

First, assume that the NAND gate G1 is selected by the high level external addresses Pi and Qi in the read mode. At this time, the external voltage VPXi is applied to the boosting voltage VPR through the first power supply terminal 1, and the external voltage VEXi is applied to 0 volts through the second power supply terminal 2, and the power supply voltage is applied to the gate of the NMOS transistor MN1 for preventing the reverse flow. A level breaking voltage is applied. The boosting voltage VPR is applied only to the selected word line selection and driver 18, and zero volts is applied to the remaining non-selected word line selection and driver 18. Accordingly, the non-return transistor MN1 and the NMOS transistor MN2 are turned on, the low level is transmitted to the node 1, and the NMOS transistor MN3 is turned off. The PMOS transistor MP3 having the gate connected to the node 1 is turned on and the boosting voltage VPR applied through the first power terminal 1 is transferred to the output terminal, that is, the selected word line, through the PMOS transistor MP3 to be read. The operation is performed. Here, the boosting voltage VPR is a voltage boosted higher than the power supply voltage Vcc to facilitate the read operation of the memory cell at a low power supply voltage (low VCC).

Next, in the program mode, the external voltage VPXi is applied to the program voltage VPGM of about 10 volts through the first power supply terminal 1, and the external voltage VEXi is 0 volts through the second power supply terminal 2, and the reverse flow prevention is performed. The shut-off voltage shut-off of the power supply voltage level is applied to the gate of the NMOS transistor MN1. In the word line selection signal Si, the program voltage VPGM is applied only to the selected word line selection and driver 18, and zero volts is applied to the unselected word line selection and driver 18. Accordingly, the non-return transistor MN1 and the NMOS transistor MN2 are turned on, the low level is transmitted to the node 1, and the NMOS transistor MN3 is turned off. The PMOS transistor MP3 having a gate connected to the node 1 is turned on and the program voltage VPGM applied through the first power supply terminal 1 is transferred to the output terminal, that is, the word line, through the transistor MP3 and selected word line. The program operation is performed only for.

Finally, the erase mode is executed in a block or sector unit composed of a plurality of cell arrays (hundreds of K-bits) in an erase operation. Therefore, when the erase operation is performed, all row decoders in the selected block are enabled and the power supply voltage Vcc is also applied to enable all of the word line selection signals Si. At this time, the external voltage VPXi is applied to the zero voltage through the first power supply terminal 1 and the external voltage VEXi is applied to the erase voltage VERS that is negative 10 volts through the second power supply terminal 2. Thus, -10 volts is applied to the source of the NMOS transistor MN3 of the word line selection and driver 18, and 0 volts is applied to the gate, so that the transistor MN3 is turned on. Thus, the erase voltage VERS of -10 volts is applied. The erase operation is performed by transferring to all word lines in the selected block. Here, the bulk and the source of the NMOS transistor MN3 are electrically connected to prevent the formation of a forward diode between the bulk and the source during the erase operation.

However, according to the row decoder of the semiconductor memory device as described above, after performing the program operation, to analyze whether the programmed memory cell is programmed to a desired threshold voltage (for example, 6 volts) or the threshold voltage distribution of the programmed cell. It is necessary to control the voltage of the word line. In addition, after performing the erase operation, it is necessary to control the voltage of the word line when the erased memory cell is properly erased to a desired threshold voltage (for example, 2 volts) or when the threshold voltage distribution of the erased cell is analyzed. . As such, the test mode for knowing the distribution of the threshold voltages of the memory cells is called a margin mode. For this purpose, the voltage of the word line must be controlled. However, there is a problem in that a margin mode test cannot be easily performed through a conventional row decoder. .

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a row decoder of a nonvolatile semiconductor memory device which selects and drives a word line in a memory cell array and easily performs a margin mode test.

1 is a circuit diagram showing a circuit of a conventional row decoder;

2 is a circuit diagram showing a circuit of a row decoder according to a preferred embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

12 input unit 14 high voltage level transfer unit

16: inverting unit 18: word line selection and driving unit

According to one aspect of the present invention for achieving the above object, a nonvolatile semiconductor for selecting a word line in a memory cell array and driving the word line at a voltage required for reading, programming, erasing, and margin mode testing. A row decoder of a memory device, comprising: an input unit for receiving external addresses applied from the outside and outputting a combined signal in response thereto; In response to the combined signal output from the input unit and the cut-off voltage and external voltages applied from the outside, the cut-off voltage of the power supply voltage level and the external voltage of the power supply voltage level and each operation mode during read operation, program operation, and margin mode operation. Outputting the external voltage in response to the external voltage at a predetermined voltage level required for the word line, and in response to the external voltage at the ground voltage level and the cutoff voltage and the external voltage at the erase voltage level. An output high voltage level transfer unit; The signal output from the high voltage level transfer unit and the external voltages are input, and in response thereto, when the output signal of the high voltage level transfer unit is high level in each operation mode, the external voltage applied in each operation mode is output and is low level. An inverting unit for outputting the external voltage applied in each operation mode during the operation; Each signal output from the high voltage level transfer unit and the inverting unit, the external voltages and the word line selection signal are inputted, and the cutoff voltage of the power supply voltage level, the external voltage of the ground voltage level and the external voltage of the boosting voltage level are read. And outputs the boosting voltage in response to a word line selection signal, and in response to the cutoff voltage at a power supply voltage level, the external voltage at a ground voltage level, the external voltage at a program voltage level, and the word line selection signal during a program operation. Outputting a program voltage and outputting an erase voltage in response to the external voltage of the ground contact level, the word line selection signal, and the external voltage of the cutoff voltage and the erase voltage level during an erase operation; The breaking voltage and the ground voltage level of the external voltage and the boosting voltage level of In response to the negative voltage to a word line selection signal having a predetermined voltage level that requires the time of a test includes a plurality of word line selection and a driver for outputting a predetermined voltage level during the test.

In a preferred embodiment of the device, the input is characterized in that it is provided with any one of a NAND gate, a NOR gate, and other logic gates.

In a preferred embodiment of the device, the high voltage level transfer section is provided with NMOS transistors and PMOS transistors.

In a preferred embodiment of the device, the NMOS transistor is characterized in that it is provided with a non-return transistor for blocking the back of the high voltage to the output terminal of the input unit.

In a preferred embodiment of the device, the inverting portion is provided with a CMOS inverter consisting of an NMOS transistor and a PMOS transistor.

In a preferred embodiment of the device, each word line selector driver comprises NMOS transistors and PMOS transistors.

In a preferred embodiment of the device, the boosting voltage is applied to the word line during a read operation and is about 4 to 5 volts boosted higher than the power supply voltage when the power supply voltage is low.

With such a device, a margin mode test can be performed through a row decoder that selects and drives a wordline in a memory cell array.

Hereinafter, the present invention will be described in detail with reference to FIG. 2. In FIG. 2, the same reference numerals are given to the components having the same functions as the components shown in FIG.

2 is a circuit diagram illustrating a circuit of a row decoder of a nonvolatile semiconductor memory device according to a preferred embodiment of the present invention.

The row decoder illustrated in FIG. 2 includes a word line selection and driving unit 18 capable of selecting a plurality of word lines, an input unit 12, a high voltage level transfer unit 14, and an inverter 16. When the input unit 12 provided as the NAND gate G1 is enabled by the high level external addresses Pi and Qi applied from the outside, the input unit 12 outputs a low level through the NAND gate G1. In addition, the high voltage level transfer unit 14 includes PMOS transistors MP4 and MP5 and NMOS transistors MN4 and MN5, and operates in each operation mode through the first, second, and third power terminals 1, 2, and 4. Different levels of external voltages VPXi, VEXi and shut-off voltage shut_off are applied. That is, in the read and program modes, a boosting voltage VPR and a program voltage VPGM are respectively applied to the external voltage VPXi, and the external voltage VEXi is applied at 0 volts. In the erase mode, the external voltage VEXi is applied to the erase voltage VERS of -10 volts, and the external voltage VPXi and the shutoff voltage shut_off are applied to 0 volts.

Thus, in the read and program modes, the NMOS transistor MN4 and the PMOS transistor MP5 are turned on so that the external voltage VPXi is transferred to an output terminal. In the erase mode, the NMOS transistor MN5 and the PMOS transistors MP4 and MP5 are turned on. 0 volt is output to the output terminal. Inverter 16 is provided with a CMOS inverter consisting of an NMOS transistor and a PMOS transistor. The inverting unit 16 receives the output of the high voltage level transfer unit 14, that is, the external voltage VPXi in each mode and outputs the external voltage VEXi in the read and program modes, and operates in reverse in the erase mode. The word line selector driver 18 includes a PMOS transistor MP7 and NMOS transistors MN7 and MN8. The gate of the NMOS transistor MN8 is connected to an input terminal of the inverter 16. It is connected to the output terminal of the inverting section 16.

In addition, external voltages VPXi, Si, and VEXi of different levels are applied to each operation mode through each input terminal. That is, in the read and program modes, a boosting voltage VPR and a program voltage VPGM are respectively applied to the external voltage VPXi, and the external voltage VEXi is applied at 0 volts. In the erase mode, the external voltage VEXi is applied to the erase voltage VERS of -10 volts, and the external voltage VPXi is applied to 0 volts. The external voltage VPXi in each mode is applied to the input terminal of the word line selection and driver 18 during read and program operations, and the external voltage VEXi is applied in the erase mode. The external voltage VPXi in each mode is applied to the gate of the NMOS transistor MN8 during the read and program operations, and the external voltage VEXi in the erase mode. The word line selection and driver 18 is performed by applying a required voltage to the external voltage Si in the margin mode test, applying a power supply voltage Vcc to the gate of the NMOS transistor MN8, and applying 0 volts to the gate of the PMOS transistor MP7.

Each operation in the read mode, the program mode, and the erase mode of the semiconductor memory device will be described based on the row decoder of the semiconductor memory device shown in FIG. 2.

First, assume that the NAND gate G1 is selected by the external addresses Pi and Qi in the read mode. At this time, the word line read boosting voltage VPR is applied through the first power supply terminal 1, and 0 volts is applied through the second power supply terminal 2, and the blocking voltage shut_off of the power supply voltage level is applied to the gate of the non-return transistor MN1. Is approved. The boosting voltage VPR is applied only to the selected word line selection and driver 18, and 0 volts is applied to the remaining word line selection and driver 18. Accordingly, 0 volts is applied to the gate of the PMOS transistor MP5 through the backflow prevention transistor MN4. Accordingly, an external voltage VPXi is applied to the input terminal of the inverter 16 through the PMOS transistor MP5 to turn on the PMOS transistor MP6. As a result, the PMOS transistor MP7 of the word line selection and driver 18 is turned on, and the boosting voltage VPR is transmitted to the output terminal, that is, the word line, and 0 volt is applied to the unselected word line.

Next, in the read mode, the word line program voltage VPGM is applied through the first power supply terminal 1, and 0 volts is applied through the second power supply terminal 2, and the gate of the non-return transistor MN1 is applied. The shut-off voltage shut_off of the power supply voltage level is applied. In the word line selection signal Si, the program voltage VPGM is applied only to the selected word line selection and driver 18, and zero volts is applied to the remaining unselected word line selection and driver 18. Accordingly, 0 volts is applied to the gate of the PMOS transistor MP5 through the backflow prevention transistor MN4. Accordingly, an external voltage VPXi is applied to the input terminal of the inverter 16 through the PMOS transistor MP5 to turn on the PMOS transistor MP6. Accordingly, the PMOS transistor MP7 of the word line selecting and driving unit 18 is turned on, and the VPGM voltage is transmitted to the output terminal, that is, the word line, and 0 volts is applied to the unselected word line, so that the program is executed only on the selected word line. do.

In the erase mode, a basic unit is executed in a block or sector unit composed of a plurality of cell arrays (hundreds of K-bits) during an erase operation. When the erase operation is performed, all row decoders in the selected block are enabled, and all of the word line select signals Si are also applied at 0 volts, and 0 volts through the first power supply terminal 1 and negative through the second power supply terminal 2. An erase voltage VERS of 10 volts is applied. Therefore, the NMOS transistor MN5 of the selected block is turned on at zero volts since the erase voltage VERS is applied, whose source is a negative voltage. The PMOS transistor MP4 is turned on by the NMOS transistor MN5, thereby applying an external voltage VPXi, that is, 0 volts to the gate of the PMOS transistor MP5. Accordingly, the NMOS transistor MN6 of the inverter 16 is turned on, and the erase voltage is applied to the word line selector driver 18 through the NMOS transistor MN6, thereby turning on the NMOS transistor MN7 to erase the voltage at the selected word line. VERS is applied to erase operation.

Finally, in the margin mode according to the present invention, the voltage control of the word line should be easy to analyze the threshold voltage distribution of the programmed memory cell or the threshold voltage distribution of the erased memory cell. At this time, the operation of the margin mode is basically the same as the operation of the read mode, only the voltage of the word line selection signal Si is different. Accordingly, the voltage level to be applied to the word line is first applied to the selection signal Si by using the PMOS transistor MP7 and the NMOS transistor MN8 of FIG. 2, and 0 volt is applied to the input terminal of the transistor MP7, and to the input terminal of the transistor MN8. The low decoder and the high voltage may be applied to a desired word line by enabling the row decoder to apply the power supply voltage Vcc. In addition, the layout area can be reduced by reducing the number of transistors in the word line selection and the driver 18 which are tied to a plurality of row decoders.

As described above, a margin mode test operation for determining a distribution of threshold voltages of a memory cell may be performed through a row decoder that selects and drives a word line in the memory cell array. In addition, the layout area can be reduced by reducing the word line selection and the number of transistors in the driver.

Claims (7)

A row decoder of a nonvolatile semiconductor memory device for selecting a word line in a memory cell array and driving the word line to a voltage required for read, program, erase, and margin mode tests. An input unit 12 which receives external addresses Pi and Qi (where i is a positive integer) and outputs a combined signal S_C in response thereto; The combination voltage S_C output from the input unit 12, the cutoff voltage shut_off applied from the outside, and the external voltages VPXi and VEXi are input, and the power supply voltage Vcc is used during the read operation, the program operation, and the margin mode operation. The external voltage VXi in response to the cutoff voltage shut_off and ground voltage Vss, and the external voltage VPXi at a predetermined voltage level required for the word line in each operation mode. VPXi) and outputs a ground voltage Vss in response to the external voltage VPXi and the shut-off voltage shut_off at the ground voltage Vss level and the external voltage VEXi at the erase voltage level during an erase operation. A high voltage level transfer section 14; In response to the signal output from the high voltage level transfer unit 14 and the external voltages VPXi and VEXi, the output signal of the high voltage level transfer unit 14 in each operation mode is high level in response thereto. An inverting unit 16 for outputting the external voltage VEXi applied in an operation mode and outputting the external voltage VPXi applied in each operation mode at a low level; A power supply voltage (Vcc) level during a read operation by receiving each signal output from the high voltage level transfer unit 14 and the inverter 16, the external voltages VPXi and VEXi, and a word line selection signal Si. The boosting voltage VPR in response to the external voltage VEXi of the cutoff voltage shutdown_off and the ground voltage Vss level, the external voltage VPXi of the boosting voltage level VPR, and the word line selection signal Si. Outputs the external voltage VEXi of the power supply voltage Vcc level, the external voltage VEXi of the ground voltage Vss level, and the external voltage VPXi and the word of the program voltage level VPGM during a program operation. The program voltage VPGM is output in response to a line selection signal Si, and the external voltage VPXi, the word line selection signal Si, and the shutoff voltage Shut-off at the ground contact voltage level Vss during an erase operation. Do not output the erase voltage (VERS) in response to the external voltage VEXi of the over erase voltage level. In the mode test operation, the cut-off voltage shut_off at the power supply voltage Vcc level, the external voltage VEXi at the ground voltage Vss level, and the external voltage VPXi at the boosting voltage level VPR are required for testing. And a plurality of word line selection and driver units 18 for outputting a predetermined voltage level during the test in response to a word line selection signal Si having a predetermined voltage level. . The method of claim 1, The input unit (12) is a nonvolatile semiconductor memory device, characterized in that any one of a NAND gate (G1), a NOR gate, and other logic gates. The method of claim 1, The high voltage level transfer unit (14) is provided with NMOS transistors (MP4, MN5) and PMOS transistors (MP4, MP5) row decoder of the nonvolatile semiconductor memory device. The method of claim 3, wherein The NMOS transistor (MN4) is a row decoder of the non-volatile semiconductor memory device, characterized in that provided as a reverse flow prevention transistor for preventing the high voltage from flowing back to the output terminal of the input unit (12). The method of claim 1, The inverting unit (16) is a row decoder of the nonvolatile semiconductor memory device, characterized in that provided with a CMOS inverter consisting of the NMOS transistor (MN6) and PMOS transistor (MP6). The method of claim 1, Each word line selector driver (18) comprises NMOS transistors (MN7, MN8) and PMOS transistors (MN8). The method of claim 1, The boosting voltage (VPR) is applied to the word line during a read operation, and when the low power supply voltage is a voltage of about 4 to 5 volts boosted higher than the power supply voltage, low row decoder of the nonvolatile semiconductor memory device.