KR100205244B1 - Row decoder in a nonvolatile semiconductor memory device - Google Patents

Abstract

The present invention relates to a flash memory device, and more particularly, to a row decoder of a flash memory device that selects and drives a word line in a memory cell array. A row decoder of a nonvolatile semiconductor memory device for selecting a word line in a memory cell array and driving the word line with a voltage required for reading, programming, erasing and margin mode testing, comprising: An input unit for outputting a combination signal in response thereto; And a control unit for receiving the external voltage of the cut-off voltage and the ground voltage level of the power supply voltage level and the external voltage of each operation mode, And outputting the external voltage in response to the external voltage at a predetermined voltage level required for the word line, and in response to the external voltage of the ground voltage level and the erasing voltage level during the erasing operation, A high voltage level transfer unit for outputting the high voltage level; And outputs the external voltage applied in each operation mode when the output signal of the high voltage level transfer unit is at a high level in each operation mode in response to the signal output from the high voltage level transfer unit and the external voltages, An inverting unit for outputting the external voltage applied in each operation mode when the external voltage is applied; The external voltage and the word line selection signal from the high voltage level transfer part and the inverting part, the external voltage and the word line selection signal from the inverting part, Outputting the boosting voltage in response to a voltage and a word line select signal and responsive to the external voltage and word line select signal of the program voltage level of the external voltage of the cutoff voltage and the ground voltage level of the power supply voltage level during a program operation A word line select signal, and an erase voltage in response to the external voltage of a cutoff voltage and an erase voltage level during an erase operation, wherein the power supply voltage Level of the cut-off voltage and the ground voltage level and the boosting voltage level In response to the negative voltage to a word line selection signal having a predetermined voltage level that requires the time of a test includes a plurality of word line selection and a driver for outputting a predetermined voltage level during the test.

Description

A row decoder of a nonvolatile semiconductor memory device of a nonvolatile semiconductor memory device,

The present invention relates to a flash memory device, and more particularly, to a row decoder of a flash memory device that selects and drives a word line in a memory cell array.

In a nonvolatile semiconductor memory device, particularly a flash memory device, which is one of the semiconductor memory devices, the state of the memory cell can be electrically programmed and erased. At this time, various voltages are required to perform the program or erase operation of the memory cell. The memory cell array is formed of a plurality of cells having a NAND structure, which is also referred to as a string or a NAND cell unit. The NAND cell unit includes memory cells connected in series between a second selection transistor connected to a common source line corresponding to a source and a first selection transistor connected to a bit line corresponding to the drain, A gate and a floating gate. Each of the control gates of the memory cells is connected to a corresponding word line, and the voltage for controlling the control gate is controlled not only in each of the read mode, the program mode and the erase mode, but also in the case of the selected memory cell array block and the non- Accordingly, various voltages such as a negative high voltage to a positive high voltage are used. The row decoder should be able to select the desired word line in each mode and drive each word line to the selected word line and the unselected word line at the voltage level required in each mode operation.

1 is a circuit diagram showing a circuit of a row decoder of a conventional nonvolatile semiconductor memory device.

The memory cell array of the nonvolatile semiconductor memory device is composed of a plurality of memory cell array blocks, and each of the memory cell array blocks is provided with a plurality of row decoders shown in FIG. Each of the row decoders includes a plurality of word line selecting and driving units 18 for selecting and driving a plurality of word lines, and the row decoder shown in FIG. 1 is configured to select eight word lines will be. The row decoder includes an input unit 12 and a plurality of word line selecting and driving units 18. The input unit 12 includes a NAND gate G1 and an NMOS transistor. The NAND gate G1 receives external addresses Pi and Qi applied from the outside, and responds to the external addresses Pi and Qi And outputs a combination signal S_C of a predetermined level to one end of the NMOS transistor MN1.

The NMOS transistor MN1 has an input terminal connected to an output terminal of the NAND gate G1 and an input terminal of each word line selecting and driving unit 18 and to which a source- 3 are connected to a gate. When the shutdown voltage shut-off is applied to the gate of the NMOS transistor, a predetermined voltage output from the NAND gate G1 is transmitted to the word line selecting and driving unit 18 in response to the shut-off voltage shut-off. It is used as a reverse current prevention transistor for preventing a high voltage from flowing back to the output terminal of the NAND gate G1 from each of the word line selecting and driving units 18. Here, it is obvious that the external addresses Pi and Qi are applied at a high level when selected, and the NAND gate G1 of the input unit 12 can be formed of a NOR gate or another logic gate.

The word line selecting and driving unit 18 includes PMOS transistors MP1, MP2, MP3 and NMOS transistors MN2, MN3. The word line selecting and driving unit 18 includes external voltages VPXi, VEXi, and Si are input through the first, second, and third power terminals 1, 2, and 4, respectively. That is, in the read and program modes, the external voltages VPXi, VEXi, and Si are respectively applied with boosting voltage VPR, 0 volt, and boosting voltage VPR, and a low level is output through the input unit 12 of the selected row decoder. As a result, the NMOS transistor MN2 and the PMOS transistor MP3 are turned on to apply the voltage required in each operation mode to the selected word line. In the erase mode, the external voltages VPXi, VEXi, and Si are 0 volts, -10 volts erase voltage VERS, and 0 volts, respectively, so that the NMOS transistor MN3 is turned on and the erase voltage -10 volts is applied.

The operations of the semiconductor memory device in the read mode, the program mode, and the erase mode will now be described with reference to the row decoder of the semiconductor memory device shown in FIG.

First, in the read mode, it is assumed that the NAND gate G1 is selected by the external addresses Pi and Qi of the high level. At this time, the external voltage VPXi is applied through the first power supply terminal 1 to the boosting voltage VPR, the external voltage VEXi is applied through the second power supply terminal 2 to 0 volt, and the gate of the backflow prevention NMOS transistor MN1 is supplied with the power supply voltage Level cut-off voltage is applied. Then, the word line selection signal Si is applied only to the selected word line selection and driving unit 18, and the other unselected word line selection and driving unit 18 is applied with 0 volt. Accordingly, the backflow prevention transistor MN1 and the NMOS transistor MN2 are turned on, so that the low level is transmitted to the node 1, and the NMOS transistor MN3 is turned off. The PMOS transistor MP3 connected to the node 1 is turned on so that the boosting voltage VPR applied through the first power supply terminal 1 is transferred to the output terminal, that is, the selected word line through the PMOS transistor MP3, Operation is performed. Here, the boosting voltage VPR is a boosted voltage higher than the power supply voltage Vcc in order to facilitate the read operation of the memory cell at a low power supply voltage (low VCC).

Next, in the program mode, the external voltage VPXi is applied through the first power supply terminal 1 to the program voltage VPGM of about 10 volts, the external voltage VEXi is supplied to the second power supply terminal 2 through the second power supply terminal 2 to 0 volt, The gate of the NMOS transistor MN1 is supplied with the cut-off voltage shut-off of the power supply voltage level. Then, the word line selection signal Si is applied only to the selected word line selection and drive unit 18 and the program voltage VPGM is applied to the selected word line selection and drive unit 18, and 0 volt is applied to the unselected word line selection and drive unit 18. Accordingly, the backflow prevention transistor MN1 and the NMOS transistor MN2 are turned on, so that the low level is transmitted to the node 1, and the NMOS transistor MN3 is turned off. Then, the PMOS transistor MP3 connected to the node 1 is turned on so that the program voltage VPGM applied through the first power supply terminal 1 is transferred to the output terminal, that is, the word line through the transistor MP3, Only the program operation is performed.

Finally, in the erase mode, the basic unit in the erase operation is executed in units of blocks or sectors made up of a plurality of cell arrays (several hundred K-bits). Therefore, when the erase operation is executed, all the row decoders in the selected block are enabled, and the word line selection signal Si is also enabled by applying the power supply voltage Vcc. At this time, the external voltage VPXi is applied through the first power supply terminal 1 to the zero voltage, and the external voltage VEXi is applied through the second power supply terminal 2 to the erase voltage VERS which is negative 10 volts. In this case, -10 volts is applied to the source of the NMOS transistor MN3 of the word line selecting and driving unit 18 and 0 volt is applied to the gate so that the transistor MN3 is turned on so that the erase voltage VERS of -10 volts And transferred to all the word lines in the selected block to perform the erase operation. By electrically connecting the bulk and the source of the NMOS transistor MN3, it is possible to prevent a forward diode from being formed between the bulk and the source during the erase operation.

However, according to the row decoder of the above-described semiconductor memory device, after the program operation, the programmed memory cell is programmed with the desired threshold voltage (for example, 6 volts) or the threshold voltage distribution of the programmed cell It is necessary to control the voltage of the word line. It is also necessary to control the voltage of the word line when the erased memory cell is properly erased to a desired threshold voltage (for example, 2 volts) or after analyzing the threshold voltage distribution of the erased cell after performing the erase operation . In this manner, the test mode for determining the distribution of the threshold voltage of the memory cell is called a margin mode. For this purpose, the voltage of the word line must be controllable. However, there is a problem that the margin mode test can not be easily performed through the conventional row decoder .

It is therefore an object of the present invention to provide a row decoder of a nonvolatile semiconductor memory device which selects a word line in a memory cell array, drives the same, and easily tests a margin mode.

1 is a circuit diagram showing a circuit of a conventional row decoder;

2 is a circuit diagram showing a circuit of a row decoder according to a preferred embodiment of the present invention,

DESCRIPTION OF REFERENCE NUMERALS

12: input unit 14: high voltage level transmission unit

16: inverting part 18: word line selection and driving part

According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device for selecting a word line in a memory cell array and driving the word line with a voltage necessary for reading, programming, erasing, A row decoder of a memory device, comprising: an input unit for receiving external addresses applied from outside and outputting a combination signal in response thereto; And a control unit for receiving the external voltage of the cut-off voltage and the ground voltage level of the power supply voltage level and the external voltage of each operation mode, And outputting the external voltage in response to the external voltage at a predetermined voltage level required for the word line, and in response to the external voltage of the ground voltage level and the erasing voltage level during the erasing operation, A high voltage level transfer unit for outputting the high voltage level; And outputs the external voltage applied in each operation mode when the output signal of the high voltage level transfer unit is at a high level in each operation mode in response to the signal output from the high voltage level transfer unit and the external voltages, An inverting unit for outputting the external voltage applied in each operation mode when the external voltage is applied; The external voltage and the word line selection signal of the high voltage level transmitter and the inverting unit, the external voltage of the boosting voltage level and the cut-off voltage of the power supply voltage level during the read operation, And in response to the external voltage and word line select signal of the external voltage and the program voltage level of the cut-off voltage and the ground voltage level of the power supply voltage level during the program operation in response to the word line select signal, A word line selection signal, and an erase voltage in response to the external voltage of the cut-off voltage and the erase voltage level during the erase operation. In the margin mode test operation, the power supply voltage level Of the external voltage and the boosting voltage level of the cut-off voltage and the ground voltage level In response to the negative voltage to a word line selection signal having a predetermined voltage level that requires the time of a test includes a plurality of word line selection and a driver for outputting a predetermined voltage level during the test.

In a preferred embodiment of the apparatus, the input unit is provided with one of a NAND gate, a NOR gate and other logic gates.

In a preferred embodiment of the device, the high voltage level transfer portion is provided with NMOS transistors and PMOS transistors.

According to a preferred embodiment of the present invention, the NMOS transistor is provided as a reverse current prevention transistor for blocking a high voltage from flowing back to an output terminal of the input unit.

In a preferred embodiment of the present invention, the inverting unit comprises a CMOS inverter including an NMOS transistor and a PMOS transistor.

In a preferred embodiment of the present invention, each of the word line selecting and driving units includes NMOS transistors and PMOS transistors.

In a preferred embodiment of the apparatus, the boosting voltage is a voltage of about 4 to 5 volts boosted to a higher voltage than the supply voltage when applied to a word line during a read operation and at a lower supply voltage.

With such a device, a margin mode test can be performed through a row decoder that selects and drives a word line in a memory cell array.

Reference will now be made in detail to the preferred embodiments of the present invention with reference to FIG. In Fig. 2, the same reference numerals are assigned to components having the same functions as the components shown in Fig.

2 is a circuit diagram showing a circuit of a row decoder of a nonvolatile semiconductor memory device according to a preferred embodiment of the present invention.

The row decoder shown in FIG. 2 is composed of word line selecting and driving units 18 capable of selecting a plurality of word lines, an input unit 12, a high voltage level transmitting unit 14, and an inverting unit 16. The input section 12 provided as the NAND gate G1 outputs a low level through the NAND gate G1 at this time when it is enabled by the external address Pi and Qi of the high level applied from the outside. The high voltage level transfer unit 14 includes PMOS transistors MP4 and MP5 and NMOS transistors MN4 and MN5. The high voltage level transfer unit 14 is connected to the first, second, and third power terminals 1, 2, External voltages VPXi, VEXi and shutoff voltage shut_off are applied at different levels. That is, in the read and program modes, the external voltage VPXi is applied with the boosting voltage VPR and the program voltage VPGM, respectively, and the external voltage VEXi is applied with 0 volt. In the erase mode, the external voltage VEXi is an erase voltage VERS of -10 volts, and the external voltage VPXi and the shutdown voltage shut_off are applied at 0 volts.

Thus, in the read and program mode, the NMOS transistor MN4 and the PMOS transistor MP5 are turned on and the external voltage VPXi is transferred to the output terminal. In the erase mode, the NMOS transistor MN5 and the PMOS transistors MP4 and MP5 are turned on And 0 volts is output to the output terminal. The inverting unit 16 is provided with a CMOS inverter including an NMOS transistor and a PMOS transistor. The inverting unit 16 receives the output of the high voltage level transfer unit 14, that is, the external voltage VPXi in each mode, in the read and program mode, and outputs the external voltage VEXi. The word line selecting and driving unit 18 includes a PMOS transistor MP7 and NMOS transistors MN7 and MN8. The gate of the NMOS transistor MN8 is connected to the input terminal of the inverting unit 16, And is connected to the output terminal of the inverting unit 16. [

External voltages VPXi, Si, VEXi and cut-off voltages of different levels are applied through each input terminal in each operation mode. That is, in the read and program modes, the external voltage VPXi is applied with the boosting voltage VPR and the program voltage VPGM, respectively, and the external voltage VEXi is applied with 0 volt. In the erase mode, the external voltage VEXi is an erase voltage VERS of -10 volts, and the external voltage VPXi is applied at 0 volts. The external voltage VPXi in each mode is applied to the input terminal of the word line selection and driving unit 18 during the read and program operations, and the external voltage VEXi is applied in the erase mode. An external voltage VEXi is applied to the gate of the NMOS transistor MN8 at the time of reading and program operation and to an input terminal of the driving unit 18 at the time of the erase mode. In the margin mode test, the word line selecting and driving unit 18 applies a necessary voltage to the external voltage Si, and the gate of the NMOS transistor MN8 is supplied with the power supply voltage Vcc and the gate of the PMOS transistor MP7 with 0 volts.

The operations of the semiconductor memory device in the read mode, the program mode, and the erase mode will be described with reference to the row decoder of the semiconductor memory device shown in FIG. 2 as follows.

First, in the case of the read mode, it is assumed that the NAND gate G1 is selected by the external addresses Pi and Qi. At this time, the word line readout boosting voltage VPR is applied through the first power source terminal 1, 0 volt is applied through the second power source terminal 2, and the gate of the reverse current prevention transistor MN1 is supplied with the cutoff voltage shut_off of the power source voltage level . Then, the word line selection signal Si is applied only to the selected word line selection and driving unit 18 and the boosting voltage VPR is applied to the selected word line selection and driving unit 18, and 0 volt is applied to the remaining word line selection and driving unit 18. Thereby, 0 volt is applied to the gate of the PMOS transistor MP5 through the backflow prevention transistor MN4. Therefore, an external voltage VPXi is applied to the input terminal of the inverting unit 16 through the PMOS transistor MP5, and the PMOS transistor MP6 is turned on. Thereby, the PMOS transistor MP7 of the word line selecting and driving unit 18 is turned on, through which the boosting voltage VPR is transferred to the output terminal, that is, the word line, and 0 volts is applied to the unselected word line.

Next, in the program mode, the word line program voltage VPGM is applied through the first power supply terminal 1, the 0 volt is applied through the second power supply terminal 2, and the gate of the reverse- The cutoff voltage shut_off of the power supply voltage level is applied. The word line selection signal Si is applied only to the selected word line selection and drive unit 18 and the program voltage VPGM is applied to the selected word line selection and drive unit 18, Thereby, 0 volt is applied to the gate of the PMOS transistor MP5 through the backflow prevention transistor MN4. Therefore, an external voltage VPXi is applied to the input terminal of the inverting unit 16 through the PMOS transistor MP5, and the PMOS transistor MP6 is turned on. Accordingly, the PMOS transistor MP7 of the word line selecting and driving unit 18 is turned on so that the VPGM voltage is transferred to the output terminal, that is, the word line, and 0 volts is applied to the unselected word line, do.

In the erase mode, the basic unit in the erase operation is executed in units of blocks or sectors each consisting of a plurality of cell arrays (several hundred K-bits). When the erase operation is performed, all the row decoders in the selected block are enabled and all the word line select signal Si is also applied with 0 volts, 0 volts through the first power supply terminal 1 and 0 volts through the second power supply terminal 2 An erase voltage VERS of 10 volts is applied. Therefore, the NMOS transistor MN5 of the selected block is turned on at zero volts because the erase voltage VERS, which is a negative voltage, is applied. The PMOS transistor MP4 is turned on by the NMOS transistor MN5 and an external voltage VPXi, that is, 0 volt is applied to the gate of the PMOS transistor MP5. Accordingly, the NMOS transistor MN6 of the inverting part 16 is turned on so that the erase voltage is applied to the word line selecting and driving part 18, whereby the NMOS transistor MN7 is turned on and the erase voltage VERS is applied and the erase operation is performed.

Finally, in the margin mode according to the present invention, it is necessary to control the voltage of the word line in order to analyze the threshold voltage distribution of the programmed memory cell or to analyze the threshold voltage distribution of the erased memory cell. In this case, the operation of the margin mode is basically the same as the operation of the read mode, and only the voltage of the word line selection signal Si is different. Therefore, by using the PMOS transistor MP7 and the NMOS transistor MN8 of FIG. 2, a voltage level to be first applied to the word line is applied to the selection signal Si, 0 volt is applied to the input terminal of the transistor MP7, A low voltage and a high voltage can be applied to a desired word line by enabling a row decoder so that a power supply voltage Vcc is applied. In addition, the number of transistors in the word line selecting and driving unit 18, which is composed of a plurality of word lines per row decoder, can be reduced, thereby reducing the layout area.

As described above, it is possible to perform a margin mode test operation to determine the distribution of threshold voltages of the memory cells through a row decoder for selecting and driving the word lines in the memory cell array. In addition, the layout area can be reduced by reducing the number of transistors in the word line selecting and driving unit.

Claims (7)

A row decoder of a nonvolatile semiconductor memory device for selecting a word line in a memory cell array and driving the word line with a voltage required for reading, programming, erasing and margin mode testing, An input unit 12 receiving external addresses Pi and Qi (here, i is a positive integer) applied from the outside and outputting a combination signal S_C in response thereto; A combination operation signal S_C output from the input unit 12 and a cutoff voltage shut_off applied from the outside and external voltages VPXi and VEXi are input to the input unit 12 to perform a read operation, Responsive to the external voltage VEXi of the cut-off voltage shut-off level and the ground voltage Vss level and the external voltage VPXi of the predetermined voltage level required for the word line in each operation mode, And outputs the ground voltage Vss in response to the external voltage VPXi and the shutoff voltage shut_off at the ground voltage Vss level and the external voltage VEXi at the erase voltage level during the erase operation A high voltage level transfer section 14; And receives the signals output from the high voltage level transmitter 14 and the external voltages VPXi and VEXi in response to the signals. When the output signal of the high voltage level transmitter 14 is at a high level in each operation mode, An inverting unit (16) for outputting the external voltage (VEXi) applied in the operation mode and outputting the external voltage (VPXi) applied in each operation mode when the level is low; And receives the external voltages VPXi and VEXi and the word line selection signal Si from the high voltage level transfer unit 14 and the inverting unit 16 and outputs the power voltage Vcc level The boosting voltage VPR is generated in response to the external voltage VPXi and the word line selection signal Si of the external voltage VEXi, the boosting voltage level VPR, and the ground voltage Vss, And outputs the external voltage VEXi at the level of the shutdown voltage shut_off and the ground voltage Vss at the level of the power supply voltage Vcc and the external voltage VPXi and the word voltage at the program voltage level VPGM, The program voltage VPGM in response to the line select signal Si and the external voltage VPXi, the word line select signal Si and the cutoff voltage shut_off at the ground contact voltage Vss level during the erase operation, And an erase voltage (VERS) in response to the external voltage (VEXi) at an erase voltage level, The external voltage VPXi of the external voltage VEXi and the external voltage VPXi of the boosting voltage level VPX at the level of the shutdown voltage shut_off and the ground voltage Vss of the power supply voltage Vcc level during the mode test operation, And a plurality of word line selecting and driving units (18) for outputting a predetermined voltage level during the test in response to a word line selecting signal (Si) of a predetermined voltage level. The nonvolatile semiconductor memory device . The method according to claim 1, Wherein the input unit (12) is provided with one of a NAND gate (G1), a NOR gate, and other logic gates. The method according to claim 1, Wherein the high voltage level transfer unit (14) comprises NMOS transistors (MP4, MN5) and PMOS transistors (MP4, MP5). The method of claim 3, Wherein the NMOS transistor MN4 is provided as a reverse current blocking transistor for blocking a high voltage from flowing back to an output terminal of the input unit 12. The nonvolatile semiconductor memory device of claim 1, The method according to claim 1, Wherein the inverting unit (16) comprises a CMOS inverter comprising an NMOS transistor (MN6) and a PMOS transistor (MP6). The method according to claim 1, Wherein the word line selecting and driving unit 18 includes NMOS transistors MN7 and MN8 and a PMOS transistor MN8. The method according to claim 1, Wherein the boosting voltage VPR is a voltage of about 4 to 5 volts boosted to a voltage higher than the power supply voltage when the power supply voltage is applied to the word line during a read operation.