KR100355715B1 - Row decoding circuit for use in a nor-type flash memory device - Google Patents

Abstract

The flash memory device disclosed herein includes a memory cell array having a plurality of local word lines, a plurality of bit lines, and a plurality of flash EEPROM cells arranged in intersections of the local word lines and the bit lines. do. A plurality of global word lines are arranged through the memory cell array to respectively correspond to the local word lines, and a local decoder circuit connects the local word lines and the global word lines in response to a control signal. The local decoder circuit includes a plurality of depletion type NMOS transistors each connected between corresponding local and global word lines.

Description

ROW DECODING CIRCUIT FOR USE IN A NOR-TYPE FLASH MEMORY DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a NOR flash memory device having a row decoder circuit capable of reducing an occupied layout area.

In general, semiconductor memory devices for storing data are classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. Volatile semiconductor memory devices lose data at power-off, while nonvolatile semiconductor memory devices retain data even at power-off. Therefore, nonvolatile semiconductor memory devices have been widely used in applications where power is suddenly cut off.

Nonvolatile semiconductor memory devices, such as NOR flash memory devices, include electrically erasable and programmable ROM cells, which are referred to as "flash EEPROM cells." In general, flash EEPROM cells include cell transistors. As shown in Fig. 1, the cell transistor is a semiconductor substrate 1 or bulk of a first conductivity type (e.g., P-type), and a second conductivity type (e.g., N-type) that is separated from each other. Source and drain regions (2, 3), a floating gate (4) for storing charges and disposed on a channel between the source and drain regions (2, 3), and on the floating gate (4) Control gate 5 disposed. The floating gate 4 and the control gate 5 are electrically separated from each other. The source region 2 is connected to the source line SL, the drain region 3 is connected to the bit line BL, and the control gate 5 is connected to the word line WL.

In Fig. 2, a nonvolatile semiconductor memory device, in particular a NOR flash memory device, is shown in block diagram form. The memory device comprises an array of memory cells, which array is divided into a plurality of, for example, two blocks or sectors 10. Each sector 10 is composed of a plurality of flash EEPROM cells, which are arranged in a matrix form of rows (or word lines) and columns (or bit lines). The memory device comprises a global word line decoder circuit 12, local decoder circuits 14 corresponding to the sectors 10, respectively, and the local decoder circuits ( Sector pre-decoder circuits 16 respectively corresponding to 14).

As shown in FIG. 2, a plurality of global word lines (GWLi, i = 0-n) are arranged in parallel through the sectors 10 and are connected to the global word line decoder circuit 12. . Each of the local decoder circuits 14 is composed of a plurality of local decoders connected to correspond to the global word lines GWLi, respectively. The word lines arranged in the sector 10 are divided into a plurality of segments, each segment consisting of a plurality of word lines. Segments of word lines in each sector correspond to local decoders in each sector 10, respectively. The word lines of each segment are commonly connected to the corresponding local decoder. Sector pre-decoder circuit 16 corresponding to each sector 10 supplies the selection signals Si corresponding to the word lines of each segment to each local decoder.

A detailed circuit diagram of a local decoder connected to any global word line GWLn is shown in FIG. The local decoder is connected to the global word line GWLn and the word lines WL0-WLm of the segment corresponding to the global word line GWLn, and the signal and the selection of the global word line GWLn. One of the word lines WL0-WLm is selected in response to signals S0-Sm. The local decoder includes an inverter INV1, a plurality of PMOS transistors MP0, MP1, ..., MP2, a plurality of first NMOS transistors MN0, MN2, ..., MN4 and a plurality of second NMOS transistors MN1. , MN3, ..., MN5) and are connected as shown in FIG.

4 is a diagram illustrating bias conditions of a conventional NOR flash memory device according to each operation mode. Hereinafter, the operation of the local decoder circuit according to the erase / read / program operation of the conventional nod type flash memory device will be described in detail with reference to FIGS. 2 to 4. Assume that one of the two sectors 10 has been selected.

In a program operation, the global word line decoder 12 selects one of the global word lines GWL0-GWLn and supplies a voltage of about 9V to the selected global word line (eg, GWL0). do. The grabble word line decoder 12 supplies a voltage of 0V to the unselected global word lines GWL1-GWLn. The sector pre-decoder circuit 16 corresponding to the selected sector selects one of the selection signals S0-Sm (eg, S0) and supplies a voltage of about 9V to the selected signal. In this case, each of the unselected selection signals S1 -Sm has a voltage of 0V. During the program operation, the voltage Vex applied to the local decoder is maintained at a voltage of 0V as shown in FIG.

In relation to the selected global word line, according to the bias condition described above, the PMOS transistors MP0, MP1, ..., MP2 and the first NMOS transistors MN0, MN2, ..., MN4 in the local decoder are Is turned on, and the second NMOS transistors MN1, MN3, ..., MN5 are turned off. Therefore, the word line WL0 receives a voltage of 9V from the selected global word line GWL0 through the PMOS and NMOS transistors MP0 and MN0, and the remaining word lines WL1-WLm correspond to each other. The PMOS and NMOS transistors are supplied with a voltage of 0V.

On the other hand, with respect to unselected global word lines, the PMOS transistors MP0, MP1,..., MP2, and the first NMOS transistors MN0, MN2,..., MN4 are turned off and the first 2 NMOS transistors MN1, MN3, ..., MN5 are turned on. Therefore, the word lines of each of the segments corresponding to the unselected global word lines are all supplied with a voltage Vex (see FIG. 4, for example 0V) through corresponding second NMOS transistors.

The read operation is the same as the program operation except that the selected signal lines GWL0 and S0 are supplied with 4.5V instead of 9V, and the description thereof is therefore omitted.

As is well known to those skilled in the art, all flash memory cells in the selected sector are erased simultaneously. Specifically, as shown in FIG. 4, the global word lines GWL0-GWLn are all supplied with a voltage of −9 V, and the selection signals S0-Sm are all supplied with a voltage of 0 V. As illustrated in FIG. At this time, a voltage Vex of −9 V is applied to each local decoder related to the selected sector. According to the bias condition described above, the PMOS transistors MP0, MP1,..., MP2 and the first NMOS transistors MN0, MN2,..., MN4 are turned off, whereas the second NMOS transistors are turned off. (MN1, MN3, ..., MN5) are turned on. Therefore, all word lines in the selected sector are supplied with a voltage Vex of -9V.

According to the conventional local decoder circuit, however, three MOS transistors (ie two NMOS transistors and one PMOS transistor) per word line are required. This causes an increase in chip size due to an increase in the layout area corresponding to the local decoder circuit.

It is an object of the present invention to provide a nonvolatile semiconductor memory device having a row decoder circuit capable of reducing the occupation area.

1 is a cross-sectional view of an electrically erased and programmable read only memory cell;

2 is a block diagram showing a conventional nonvolatile semiconductor memory device;

3 is a circuit diagram showing a local decoder circuit shown in FIG.

4 illustrates bias conditions of each operation mode according to a conventional memory device;

5 is a block diagram showing a nonvolatile semiconductor memory device according to the present invention;

6 is a preferred embodiment of the global word line decoder shown in FIG. 5;

FIG. 7 is a preferred embodiment of the sector selection circuit shown in FIG. 5;

8 shows bias conditions in each mode of operation in accordance with the memory device of the present invention; And

9 is another embodiment of a nonvolatile semiconductor memory device according to the present invention.

* Explanation of symbols on the main parts of the drawing

10, 100a, 100b: Sector 12, 120: Global word line decoder

14, 140a, 140b: local decoder circuit 16: sector pre-decoder circuit

160a, 160b, 160a ': sector selection circuit

(Configuration)

According to the present invention for achieving the above object, a flash memory device includes a plurality of first word lines, a plurality of bit lines and a plurality of word lines arranged in intersections of the word lines and the bit lines. A memory cell array having flash EEPROM cells; A plurality of second word lines arranged through the memory cell array to correspond to the first word lines, respectively; A first selection circuit coupled to the first word lines and driving the second word lines with word line voltages to be applied to the first word lines in each operation mode; A switch circuit connecting the first word lines and the second word lines in response to a control signal; And a second selection circuit for generating the control signal in accordance with address information for selecting the memory cell array. The switch circuit comprises a plurality of depletion type MOS transistors respectively connected between corresponding first and second word lines; The depletion MOS transistors are commonly controlled by the control signal.

In this embodiment, each of the depletion MOS transistors includes a depletion NMOS transistor having a negative threshold voltage.

In this embodiment, the first selection circuit includes a plurality of decoders each connected to the second word lines, each driving a corresponding second word line to a word line voltage; Each of the decoders comprises means for preventing the word line voltage from being supplied to the corresponding second word line during an erase operation when the corresponding second word line is defective.

In this embodiment, the flash memory device includes a plurality of third word lines, a plurality of second bit lines, and a plurality of second flash EEPROM cells arranged in intersection regions of the third word lines and the bit lines. A second memory cell array having a plurality of memory cells; A second switch circuit connecting the third word lines with the second word lines in response to a second control signal; And a third selection circuit for generating the second control signal according to the address information for selecting the second memory cell array.

In this embodiment, the second switch circuit includes a plurality of second depletion type MOS transistors respectively connected between corresponding second and third word lines; The second depletion type MOS transistors are commonly controlled by the second control signal.

In this embodiment, each of the second depletion type MOS transistors includes a depletion type NMOS transistor having a negative threshold voltage.

In this embodiment, when one of the first and second memory cell arrays is selected during the erase operation, the voltage level of the control signal applied to the switch circuit corresponding to the unselected memory cell array is not selected. It is set lower than the threshold voltage of the depletion type NMOS transistor so that the word lines in the non-memory cell array are floating.

(Example)

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention are described in detail below on the basis of reference drawings.

Referring to FIG. 5, a nonvolatile semiconductor memory device according to the present invention is shown in block diagram form. The nonvolatile semiconductor memory device includes a memory cell array, which is divided into a plurality of sectors or blocks. Each of the sectors includes a plurality of memory cells arranged in rows (or word lines) and columns (or bit lines). For convenience of description, only two sectors 100a and 100b constitute the memory cell array. The memory device includes a plurality of global word lines GWLi, i = 0-n, and the global word lines GWLi are arranged in parallel through the sectors 100a and 100b.

In this embodiment, the number of word lines WLi (hereinafter referred to as "local word line") in each sector 100a, 100b is equal to the number of global word lines GWLi. That is, the ratio of local word lines to global word lines is 1: 1.

The memory device of the present invention includes a global word line decoder circuit 120, first and second local decoder circuits 140a and 140b and first and second sector select circuits 160a and 160b. The global word lines GWL0-GWLn are connected to the global word line decoder circuit 120. The first and second local decoder circuits 140a and 140b correspond to the sectors 100a and 100b, respectively, and the first and second sector select circuits 160a and 160b correspond to the first and the second. Correspond to the two sector selection circuits 140a and 140b, respectively.

As shown in FIG. 5, each of the first and second local decoder circuits 140a and 140b includes a plurality of depletion NMOS transistors M0-Mn, each transistor having a local word line of a corresponding sector. To WL0-WLn. Depletion-type NMOS transistors M0-Mn of the first local decoder circuit 140a have gates commonly connected to a select signal or control signal SWSa supplied from the first sector select circuit 160a. Similarly, the depletion NMOS transistors M0-Mn of the second local decoder circuit 140b have gates commonly connected to the select signal or control signal SWSb supplied from the second sector select circuit 160b.

6, a preferred embodiment of a global word line decoder circuit corresponding to any global word line is shown. The global word line decoder 120 is connected to a corresponding global word line and word the global word line in response to the decode signals Di, Dj from a row pre-decoder circuit (not shown). Drive with line voltage (Vpx / Vex). The global word line decoder includes two PMOS transistors 121 and 122, four NMOS transistors 123, 124, 125 and 127, a fuse 126, a NAND gate 128 and a NOR gate 129. And connected as shown in FIG. 6.

Here, the PMOS and NMOS transistors 122 and 125 constitute a driver, and the NAND gate 128, the NOR gate 129, the PMOS transistor 121, and the NMOS transistors 123 and 124 drive the driver. And the fuse 126 and the NMOS transistor 127 supply the voltage Vex to the corresponding global word line during an erase operation when the corresponding global word line is defective. It constitutes a means for preventing it.

In the program / read operation, when the output of the NAND gate 128 goes low according to the decode signals Di and the NMOS transistor 124 is turned on by the decode signal Dj, the selected global word line GWL is driven to the voltage Vpx through the PMOS transistor 122, and the unselected global word lines are driven to the voltage Vex through any one of the fuse 126 and the NMOS transistor 127. Driven. The voltage levels of each signal used in the global word line decoder circuit are summarized in FIG.

As described above, since the global word lines GWL0-GWLn are arranged to correspond to the local word lines WL0-WLn of each sector 100a / 100b, adjacent global word lines are electrically connected. Can be connected. Such global word lines will be replaced by corresponding redundancy word lines by a redundancy circuit (not shown) so that they are not selected during program / read / erase operations.

Specifically, when any global word line is defective, the fuse 126 corresponding to the defective global word line is blown. In the program / read operation, the word line disable signal WLdis applied to the NOR gate 129 transitions from a low level to a high level, and the control signal ERA_Vneg becomes a high level (see FIG. 8). Therefore, the NMOS transistor 123 is turned off irrespective of the decode signals Di and Dj, and a combined global word line is connected to the voltage Vex through the NMOS transistor 127. In an erase operation, the signal ERA_Vneg has a negative voltage level (eg, -9V) such that the NMOS transistor 127 is turned off. Therefore, during the erase operation, the voltage Vex can be prevented from being supplied to the defective global word line.

If a voltage Vex of −9 V is applied to the defective global word line during the erase operation, the memory cell connected to the defective global word line, that is, the local word line corresponding to the defective global word line, is over-erased. This causes charges on the bit line connected to the overerased cell to leak through the undererased cell during a program operation, resulting in a program fail.

7 is a preferred embodiment of the sector selection circuit according to the present invention. The sector select circuit 160a / 160b includes two NAND gates 161 and 163, an OR gate 162, three PMOS transistors 164, 165 and 169, three NMOS transistors 166, 168 and 170, and an inverter 167, which is connected as shown in FIG. In the program / read operation, the sector selection circuits 160a / 160b apply a voltage Vpx to the selected signal line SWSa / SWSb in response to control signals SECTi and ERA, and the unselected signal line ( The voltage Vexm is applied to SWSb / SWSa). The control signal SECTi is a sector enable signal, and the control signal ERA indicates an erase operation.

For example, when the control signal SECTi is high level and the control signal ERA is high level, i.e., in the case of a selected sector, the NMOS transistors 166, 170 and the PMOS transistor 165 are turned on. As a result, the signal line SWSa / b is connected to the voltage Vexm. When the control signal SECTi is at a low level and the control signal ERA is at a high level, that is, in the case of an unselected sector, the NMOS transistor 168 and the PMOS transistor 170 are turned on. As a result, the signal line SWSa / b is connected to the voltage Vpx.

In this embodiment, the sector select circuit applies different voltages Vexm to the selected and unselected signal lines SWSa, SWSb or SWSb, SWSa during the erase operation. Specifically, the voltage Vexm is a negative voltage so that the selection signal SWSa / b associated with the selected sector has a voltage of −11V and the signal SWSb / a associated with the unselected sector has a voltage of 0V. It is applied to sector select circuits 160a / 160b via a level shifter (not shown). This will be explained in detail below.

8 is a diagram illustrating bias conditions of each operation mode of a memory device according to the present invention. Read, program and erase operations in accordance with the present invention are described in detail with reference to the accompanying drawings. Assuming that sector 100a of FIG. 5 is selected and sector 100b is not selected, the program / read / erase operations are described.

When the global word line decoder circuit 120 selects any global word line (e.g., GWL0) during a program / read operation, the global word line decoder circuit 120 selects the selected global word line. Supply a voltage of 9V / 4.5V to (GWL0) and a voltage of 0V to the unselected global word lines (GWL1-GWLn). The first sector selection circuit 160a outputs a selection signal or control signal SWSa having a voltage level of 9V / 4.5V. This causes the depletion NMOS transistors M0-Mn to be turned on so that the local word line WL0 is supplied with a voltage of 9V / 4.5V and the other local word lines WL1-WLn have a voltage of 0V. To be supplied.

On the other hand, in the program / read operation, the second sector select circuit 160b outputs a selection signal or control signal SWSb having a voltage level of 0V. Since the voltage of the selected global word line GWL0 is 9V / 4.5V and the gate voltage of the depletion NMOS transistor M0 is 0V, the local word line WL0 in the unselected sector 100b is depleted. Charged to the absolute value of the threshold voltage of the NMOS transistor M0. However, this does not affect the overall operation of the memory device because the column decoding circuitry (not shown) associated with the unselected sector 100b is disabled.

In the erase operation, as shown in FIG. 8, all global word lines, that is, all local word lines of the selected sector 100a are supplied with a voltage of −9 V, and all of the unselected sectors 100b Local word lines are plotted. Specifically, the global word line decoder circuit 120 supplies a voltage Vex of −9 V to the global word lines GWL0-GWLn. In this case, the first sector selection circuit 160a outputs a selection signal SWSa having a voltage level of 0V. This means that the voltages Vex (ie, -9V) of the global word lines GWL0-GWLn correspond to corresponding local words in the selected sector GWLn through corresponding depletion NMOS transistors M0-Mn. To be passed on lines.

While the selected sector is being erased, the voltages Vex (-9V) of the global word lines GWL0-GWLn should be prevented from being supplied to local word lines in the unselected sector 100b. . To this end, the second sector select circuit 160b according to the present invention outputs a select signal SWSb having a voltage Vexm level of −11 V (when the threshold voltage of a depletion NMOS transistor is −2 V), As a result, the depletion NMOS transistors M0-Mn of the second local decoder circuit 120b are shut off. This allows local word lines of the unselected sector 100b to float, thereby preventing the voltages of the global word lines from being supplied to local word lines of the unselected sector 100b.

As described above, the local decoder circuit is implemented using one depletion type NMOS transistor for connecting the global word line and the local word line. Therefore, the burden on the local decoder circuit for the chip size is reduced.

Since the ratio of the global word lines to the local word lines is 1: 1, as shown in Fig. 9, the local decoder circuits 140a / 140b are composed of local decoders and even local decoders. At this time, the sector select circuit 160a 'activates one of the select signals SWSae and SWSao according to the least significant bit of the address signals for selecting local word lines. This causes the depletion NMOS transistors (odd or even) placed on one side of the sector to be turned on, resulting in a reduced current consumption of the pumped voltage.

As described above, since the local decoder circuit is implemented using one depletion type NMOS transistor for connecting the global word line and the local word line, the burden on the local decoder circuit for the chip size is reduced.

Claims (16)

A memory cell array having a plurality of first word lines, a plurality of bit lines, and a plurality of flash EEPROM cells arranged in intersections of the word lines and the bit lines; A plurality of second word lines arranged through the memory cell array to correspond to the first word lines, respectively; A first selection circuit coupled to the first word lines and driving the second word lines with word line voltages to be applied to the first word lines in each operation mode; A switch circuit connecting the first word lines and the second word lines in response to a control signal; A second selection circuit for generating the control signal in accordance with address information for selecting the memory cell array; The switch circuit comprises a plurality of depletion type MOS transistors respectively connected between corresponding first and second word lines; And the depletion MOS transistors are commonly controlled by the control signal. The method of claim 1, And each of the depletion MOS transistors includes a depletion NMOS transistor having a negative threshold voltage. The method of claim 2, The first selection circuit includes a plurality of decoders each connected to the second word lines, each driving a corresponding second word line to a word line voltage; Each of the decoders comprises means for preventing the word line voltage from being supplied to the corresponding second word line during an erase operation when the corresponding second word line is defective. The method of claim 3, wherein A second memory cell array having a plurality of third word lines, a plurality of second bit lines and a plurality of second flash EEPROM cells arranged in intersections of the third word lines and the bit lines; A second switch circuit connecting the third word lines with the second word lines in response to a second control signal; And a third selection circuit for generating the second control signal in accordance with address information for selecting the second memory cell array. The method of claim 4, wherein The second switch circuit includes a plurality of second depletion type MOS transistors respectively connected between corresponding second and third word lines; And the second depletion type MOS transistors are commonly controlled by the second control signal. The method of claim 5, Each of the second depletion type MOS transistors includes a depletion type NMOS transistor having a negative threshold voltage. The method of claim 6, When one of the first and second memory cell arrays is selected during the erase operation, the voltage level of the control signal applied to the switch circuit corresponding to the unselected memory cell array is a word in the unselected memory cell array. A flash memory device that is set lower than a threshold voltage of the depletion type NMOS transistor so that lines are floating. A memory cell array divided into a first sector and a second sector; Each of the first and second sectors has a plurality of local word lines, a plurality of bit lines, and a plurality of flash EEPROM cells arranged in intersections of the local word lines and the bit lines. Wow; A plurality of global word lines arranged through the memory cell array to respectively correspond to local word lines in the respective sectors; A global word line decoder circuit coupled to the global word lines and driving the global word lines with word line voltages to be applied to the local word lines in each operation mode; First local decoder circuitry connecting the local word lines and the global word lines in the first sector in response to a first control signal; Second local decoder circuitry connecting the local word lines and the global word lines in the second sector in response to a second control signal; A first sector selecting circuit for generating the first control signal in accordance with address information for selecting the first sector; A second sector selection circuit for generating the second control signal according to the address information for selecting the second sector, Each of the first and first local decoder circuits comprises a plurality of depletion MOS transistors respectively connected between corresponding local and global word lines; And the depletion MOS transistors are commonly controlled by corresponding control signals. The method of claim 8, A depletion type MOS transistor in each of said first and second local decoder circuits each comprises a depletion type NMOS transistor having a negative threshold voltage. The method of claim 9, The global word line selection circuit is connected to the global word lines, each NOR flash memory device including a plurality of decoders for driving a corresponding global word line to a word line voltage. The method of claim 10, Each of the decoders, A drive control signal generator for generating a drive control signal in response to the decode signals; A driver connected between a first power supply terminal and a second power supply terminal and driving a corresponding global word line with a word line voltage provided from one of the first and second power supply terminals in response to the driving control signal; And; Means for preventing the voltage from the second power supply terminal from being supplied to the corresponding global word line during an erase operation when the corresponding global word line is defective. The method of claim 11, The prevention means includes a fuse connected between the driver and the second power supply terminal; An NMOS transistor connected in parallel with the fuse between the driver and the second power supply terminal; And the NMOS transistor is turned off when an erase operation is performed. The method of claim 12, And a fuse of each decoder is cut when the corresponding global word line is defective. The method of claim 10, When one of the first and second sectors is selected during the erase operation, the voltage level of the control signal applied to the local decoder circuit corresponding to the unselected sectors causes the local word lines in the unselected sectors to float. NOR flash memory device is set to be lower than the threshold voltage of the depletion type NMOS transistor. A memory cell array having a plurality of first word lines, a plurality of bit lines, and a plurality of flash EEPROM cells arranged in intersections of the word lines and the bit lines; A plurality of second word lines arranged through the memory cell array to correspond to the first word lines, respectively; A first selection circuit coupled to the first word lines and driving the second word lines with word line voltages to be applied to the first word lines in each operation mode; A first switch circuit disposed on one side of the memory cell array and configured to connect even-numbered lines of the first word lines and even-numbered lines of the second word lines in response to a first control signal; A second switch circuit disposed on the other side of the memory cell array and connecting odd-numbered lines of the first word lines and odd-numbered lines of the second word lines in response to a second control signal; A second selection circuit for generating the first and second control signals in accordance with address information for selecting the memory cell array, Each of the first and second switch circuits comprises a plurality of depletion MOS transistors respectively connected between corresponding first and second word lines; And the depletion MOS transistors are commonly controlled by the control signal. The method of claim 15, A depletion MOS transistor in each of the first and second switch circuits comprises a depletion NMOS transistor each having a negative threshold voltage.