KR19980022291A - Internal voltage converter of semiconductor memory device and driving method thereof - Google Patents

Abstract

The present invention relates to an internal voltage converter of a semiconductor memory device and a method of driving the same. The present invention provides a semiconductor memory device having a standby voltage generator for generating a standby voltage required in a standby state and a plurality of active voltage generators for generating an active voltage required for reading or writing. The power consumption of the semiconductor memory device is reduced by configuring the internal voltage converter of the semiconductor memory device.

Description

Internal voltage converter of semiconductor memory device and driving method thereof

The present invention relates to an internal voltage converter of a semiconductor memory device and a driving method thereof, and more particularly, to an internal voltage converter and a driving method thereof of a semiconductor memory device for reducing power consumption in a self refresh mode.

As the memory capacity increases, the breakdown voltages of the internal devices of the semiconductor memory device continue to decrease. As a result, the 5-volt power supply used in the low-capacity semiconductor memory device cannot be used. This is because the internal voltages of the internal devices are low to withstand 5 volts. In order to solve this problem, the only option was to lower the power. For DRAM producers, changing the external power supply for each generation according to the progress of transistor miniaturization can reduce power consumption and ensure reliability while still utilizing the performance of microtransistors. From the user's point of view, however, this is not a realistic alternative and it would be natural to want to have a constant external power supply for at least two or three generations. In large scale integrated circuits (LSIs), one can easily anticipate that demand will be very strong. The solution is to use an internal voltage converter. The internal voltage converter refers to a circuit for stepping down to match the breakdown voltage of a transistor by inputting a constant external power source. However, as memory capacities continue to increase and density increases, there is a need for an internal voltage converter capable of supplying a stable internal voltage.

1 is a circuit diagram of an internal voltage converter of a conventional semiconductor memory device. The structure of the circuit shown in FIG. 1 will be described. There are a first comparator 11, a second comparator 13, a third comparator 15, a fourth comparator 17, and a fifth comparator 19 having the reference voltage VCC_REF as an inverting input. The first PMOS transistor 21, the second PMOS transistor 23, the third PMOS transistor 25, the fourth PMOS transistor 27, and the first output terminal of each of the fields 11, 13, 15, 17, and 19. 5 PMOS transistors 29 are connected respectively. The drain of the first PMOS transistor 21 is connected to the STB_IVC signal, which is a voltage provided during the standby state of the semiconductor memory device, and the semiconductor memory device is activated to the drain of the second PMOS transistor 23. ACT_IVC1, the voltage provided at the time, ACT_IVC2 at the drain of the third PMOS transistor 25, ACT_IVC3 at the drain of the fourth PMOS transistor 27, and ACT_IVC4 at the drain of the fifth PMOS transistor 29, respectively. have.

In addition, a PIACT signal is connected to the control terminals of the second comparator 13, the third comparator 15, the fourth comparator 17, and the fifth comparator 19, so that the four comparators 13, 15, 17, 19) to control the operating state. That is, when PIACT is a logic high level, the second comparator 13, the third comparator 15, the fourth comparator 17, and the fifth comparator 19 are applied to each non-inverting input terminal. The second comparator 13, the third comparator 15, the fourth comparator 17, and the fifth comparator 19 are applied to each input terminal when the voltage is operated and the PIACT is a logic low level. It will not work regardless of the voltage.

The operation of the circuit shown in FIG. 1 will be described. First, in the standby state of the semiconductor memory device, STB_IVC connected to the first comparator 11 becomes the output of the internal voltage converter 10. If the STB_IVC is higher than VCC_REF, the output of the first comparator 11 becomes + Vcc, and the first PMOS transistor 21 is turned off. Since the first PMOS transistor 21 is unsuccessful, VCCext, which is an external power source, is not supplied, so that STB_IVC is stepped down. Then, when STB_IVC is lower than VCC_REF, the output of the first comparator 11 becomes -Vcc, so the first PMOS transistor 21 is conductive. VCCext is then supplied and STB_IVC is boosted again. STB_IVC is output as a constant voltage while repeating such step-down and step-up. Here, STB_IVC is set to output at a low voltage because power consumption must be reduced in the standby state.

Then, when the semiconductor memory device enters the activation mode, the activation mode signal PIACT is enabled to enable the second comparator 13, the third comparator 15, the fourth comparator 17, and the fifth comparator 19. Puts the unit into a standby state. Therefore, ACT_IVC1, ACT_IVC2, ACT_IVC3, and ACT_IVC4 become the outputs of the internal voltage converter 10. If ACT_IVC1 is higher than VCC_REF, the output of the second comparator 13 becomes + Vcc, so that the second PMOS transistor 23 is turned off. Since the second PMOS transistor 23 is unsuccessful, VCCext, which is an external power source, is not supplied, so the ACT_IVC1 is stepped down.

Then, when ACT_IVC1 is lower than VCC_REF, the output of the second comparator 13 becomes -Vcc, so the second PMOS transistor 23 is conductive. So VCCext is supplied and ACT_IVC1 is boosted again. As the step-down and step-up are repeated, ACT_IVC1 maintains a constant voltage. ACT_IVC2, ACT_IVC3, and ACT_IVC also operate in the same manner as ACT_IVC1. The ACT_IVC1, ACT_IVC2, ACT_IVC3, and ACT_IVC4 should be set to have sufficient voltage to drive the semiconductor devices connected to the internal voltage converter 10.

Here, in the activation mode, the second comparator 13, the third comparator 15, the fourth comparator 17 and the fifth comparator 19 are always in an operating state and are connected to the internal voltage converter 10. It consumes a certain amount of power regardless of the operating state. However, there is a self refresh mode to reduce power consumption among the activation modes. This mode is for reducing power consumption, but also in the self refresh mode, the second comparator 13, the third comparator 15, the fourth comparator 17, the fifth comparator 19 and the second PMOS transistor 23, Since the third PMOS transistor 25, the fourth PMOS transistor 27, and the fifth PMOS transistor 29 continue to operate, power is unnecessarily consumed.

As described above, according to the related art, the second comparator 13, the third comparator 15, the fourth comparator 17, and the fifth comparator 19 and the second comparator in the self-refresh mode to reduce power consumption. Since the PMOS transistor 23, the third PMOS transistor 25, the fourth PMOS transistor 27, and the fifth PMOS transistor 29 continue to operate, unnecessary power consumption is generated, and therefore, in designing a low power semiconductor memory device. It becomes an obstacle.

Accordingly, an aspect of the present invention is to provide an internal voltage converter of a semiconductor memory device capable of reducing power consumption in a specific mode.

Another object of the present invention is to provide a method of driving an internal voltage converter of a semiconductor memory device capable of reducing power consumption in a specific mode.

1 is a schematic diagram of an internal voltage converter of a conventional semiconductor memory device

2 is a schematic diagram of an internal voltage converter of a semiconductor memory device according to the present invention;

3 is a detailed circuit diagram of the comparator illustrated in FIG. 2.

4 is a timing diagram of signals used in FIG.

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a semiconductor memory device having a standby voltage generator for generating a standby voltage required in a standby state and a plurality of active voltage generators for generating an active voltage required for reading or writing. The four active voltage generators provide an internal voltage converter of the semiconductor memory device, which is selectively operated in a specific mode.

Preferably, the specific mode is a self refresh mode.

In order to achieve the above object, the present invention also provides a first comparator, a second comparator, a third comparator, a fourth comparator, and a fifth comparator with one reference voltage as the input, and the first comparator, the second comparator, and the third comparator. Gates are respectively connected to the output terminals of the comparator, the fourth comparator and the fifth comparator, the sources are connected to an external power supply, and the drains are respectively ratios of the first comparator, the second comparator, the third comparator, the fourth comparator and the fifth comparator. A standby voltage output signal connected to a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a drain of the first PMOS transistor respectively connected to an inverting input terminal and outputting a standby voltage; And a first active voltage control signal connected to a control terminal of the second comparator and the third comparator to control operations of the second comparator and the third comparator, the second PMOS transistor and the third PMOS. A first active voltage output signal connected to the drain of the transistor, a second active voltage control signal connected to a control terminal of the fourth comparator and the fifth comparator to control an operation of the fourth comparator and the fifth comparator; Input a second active voltage output signal connected to a drain of a 4 PMOS transistor and a fifth PMOS transistor, a third active voltage control signal enabled in a specific mode, and the first active voltage control signal and a third active voltage control signal And an output terminal having a logic gate connected to a control terminal of the fourth comparator and the fifth comparator to stop the operation of the fourth comparator and the fifth comparator when a third active voltage control signal is enabled. An internal voltage converter of a semiconductor memory device is provided.

Preferably, the specific mode is a self-refresh mode, the logic gate is an inverter for inputting the third active voltage control signal, and an AND gate for inputting the output of the inverter and the first active voltage control signal ( AND gate).

According to another aspect of the present invention, a first active voltage control signal is enabled to activate the second comparator and the third comparator so that a first active voltage output signal is output, and the first active voltage is output. As the control signal is enabled, the third active voltage control signal is enabled to activate the fourth comparator and the fifth comparator so that a second active voltage output signal is output, enabling the specific mode signal; The second active voltage control signal is enabled as the specific mode is enabled, and the third active voltage control signal is disabled as the second active voltage control signal is enabled to enable a fourth comparator and a fifth comparator. It provides a method of driving an internal voltage converter of a semiconductor memory device, characterized in that it comprises a step that is disabled.

Preferably, the specific mode is a self refresh mode.

According to the present invention, the power consumption of the semiconductor memory device is reduced.

Hereinafter, the present invention will be described in detail through examples.

2 is a schematic diagram of an internal voltage converter according to the present invention. The structure of the circuit shown in FIG. 2 will be described. First, a standby voltage generator 31 that generates a standby voltage required in a standby state of a semiconductor memory device, and a plurality of active voltage generators 33 that generate an active voltage required for reading or writing are configured. Specifically, there is a first comparator 41, a second comparator 43, a third comparator 45, a fourth comparator 47, and a fifth comparator 49 connected to each inverting input terminal to a reference voltage VCC_REF. A first PMOS transistor 51 and a second PMOS at each output terminal of the first comparator 41, the second comparator 43, the third comparator 45, the fourth comparator 47, and the fifth comparator 49. Gates of the transistor 53, the third PMOS transistor 55, the fourth PMOS transistor 57, and the fifth PMOS transistor 59 are connected to each other. Sources of the first PMOS transistor 51, the second PMOS transistor 53, the third PMOS transistor 55, the fourth PMOS transistor 57, and the fifth PMOS transistor 59 are all connected to VCCext, which is an external power source. The drains are connected to non-inverting input terminals of the first comparator 41, the second comparator 43, the third comparator 45, the fourth comparator 47 and the fifth comparator 49, respectively. The output terminal of the AND gate 63 is connected to the control terminal of the fourth comparator 47 and the fifth comparator 49, and the PIACT1 signal and the output terminal of the inverter 61 are connected to the input terminal of the AND gate 63. PIACT2 is connected to the input terminal of the inverter 61. PIACT1 is connected to the control terminals of the second comparator 43 and the third comparator 45 to control the operation of the second comparator 43 and the third comparator 45.

The output of the AND gate 63 is connected to the control stages of the fourth comparator 47 and the fifth comparator 49 as PIACT2P to control the operation of the fourth comparator 47 and the fifth comparator 49. . That is, when PIACT1 and PIACT2P are logic high levels, the second comparator 43, the third comparator 45, the fourth comparator 47, and the fifth comparator 49 operate by the voltage applied to the input terminal, When PIACT2P is at a logic low level, the second comparator 43, the third comparator 45, the fourth comparator 47 and the fifth comparator 49 do not operate regardless of the voltage applied to the input terminal.

3 is a circuit diagram of the comparator shown in FIG. 2. The comparator shown in FIG. 3 has a general differential amplifier 61 structure. An NMOS transistor 63 is connected to the lower end of the differential amplifier 61 to serve as a current source. One of the VCC_REF, PIACT1, and PIACT2P signals is connected to the gate of the NMOS transistor 63 to control the operation of the differential amplifier 61. That is, when the signal A connected to the gate of the NMOS transistor 63 is higher than the threshold voltage of the NMOS transistor 63, the NMOS transistor 63 conducts and changes the differential amplifier 61 to an operating state. When the signal A connected to the gate of the NMOS transistor 63 is lower than the threshold voltage of the NMOS transistor 63, the NMOS transistor 63 is turned off and the differential amplifier 61 is stopped.

4 is a timing diagram of signals used in FIG. 2. An operation of FIG. 2 will be described with reference to FIGS. 3 and 4. First, in the standby state of the semiconductor memory device, STB_IVC connected to the first comparator 41 becomes the output of the internal voltage converter 30. If the STB_IVC is higher than VCC_REF, the output of the first comparator 41 becomes + Vcc, and the first PMOS transistor 51 is turned off. Since the first PMOS transistor 51 is turned off, the external power supply VCCext is not supplied and STB_IVC is stepped down. Then, when STB_IVC is lower than VCC_REF, the output of the first comparator 41 becomes -Vcc, so the first PMOS transistor 51 is conducting. VCCext is then supplied and STB_IVC is boosted again. STB_IVC is output as a constant voltage while repeating such step-down and step-up. Here, STB_IVC is set to output at a low voltage because power consumption must be reduced in the standby state.

Then, the CASB signal is first enabled as the CBR (CASB Before RASB) mode so that the semiconductor memory device enters the activation mode, and the RASB signal is enabled after a while. When the RASB signal is enabled, the PIRAS signal is enabled and PIACT1 is enabled accordingly. When PIACT1 is enabled, PIACT2P is enabled and at the same time ACT_IVC1 is turned on and output as the output of the internal voltage converter 30. Up to this point, the read or write operation of the semiconductor memory device is performed.

In this state, if ACT_IVC1 becomes higher than VCC_REF, the outputs of the second comparator 43 and the third comparator 45 become + Vcc so that the second PMOS transistor 53 and the third PMOS transistor 55 are not connected. Since the second PMOS transistor 53 and the third PMOS transistor 55 are not communicated with each other, VCCext, which is an external power source, is not supplied, so that ACT_IVC1 is stepped down. Then, when ACT_IVC1 is lower than VCC_REF, the outputs of the second comparator 43 and the third comparator 45 become -Vcc, so that the second PMOS transistor 53 and the third PMOS transistor 55 become conductive. So VCCext is supplied and ACT_IVC1 is boosted again.

When the read or write operation of the semiconductor memory device is completed, PIACT2 is enabled due to the PISELF enabled by the RASB. As PIACT2 is enabled, the output of inverter 61 is at a logic low level, causing the output of AND gate 63 to be at a logic low level. That is, PIACT2P is at a logic low level. When PIACT2P is at a logic low level, the current sources of the fourth comparator 47 and the fifth comparator 49 are interrupted, and the fourth comparator 47 and the fifth comparator 49 stop operation, so the ACT_IVC2 is turned off. The output of the internal voltage converter 30 becomes zero. This is the self refresh mode. In the self-refresh mode, power consumption is reduced by not operating the fourth comparator 47 and the fifth comparator 49.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, according to the present invention, power consumption is reduced because only the ACT_IVC1 of the internal voltage converter operates in the self refresh mode. Therefore, it is suitable for low power semiconductor memory devices.

Claims (7)

A semiconductor memory device having a standby voltage generator for generating a standby voltage required in a standby state and a plurality of active voltage generators for generating an active voltage required for reading or writing, wherein the plurality of active voltage generators are selectively used in a specific mode. An internal voltage converter of a semiconductor memory device, characterized in that it operates. The internal voltage converter of claim 1, wherein the specific mode is a self refresh mode. A first comparator, a second comparator, a third comparator, a fourth comparator, and a fifth comparator having a reference voltage as one input; Gates are respectively connected to the output terminals of the first comparator, the second comparator, the third comparator, the fourth comparator, and the fifth comparator, the sources are connected to an external power supply, and the drains are the first comparator, the second comparator, and the third comparator. A first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor respectively connected to the non-inverting input terminals of the fourth comparator and the fifth comparator; A standby voltage output signal connected to the drain of the first PMOS transistor and outputting a standby voltage; A first active voltage control signal connected to a control terminal of the second comparator and a third comparator to control an operation of the second comparator and the third comparator; A first active voltage output signal connected to the drains of the second PMOS transistor and the third PMOS transistor; A second active voltage control signal connected to a control terminal of the fourth comparator and the fifth comparator to control an operation of the fourth comparator and the fifth comparator; A second active voltage output signal connected to the drains of the fourth PMOS transistor and the fifth PMOS transistor; A third active voltage control signal enabled in a specific mode; When the first active voltage control signal and the third active voltage control signal are input, and an output terminal is connected to the control terminals of the fourth comparator and the fifth comparator, when the third active voltage control signal is enabled, the fourth comparator And a logic gate to halt the operation of the comparator. The internal voltage converter of claim 3, wherein the specific mode is a self refresh mode. The semiconductor device of claim 3, wherein the logic gate comprises an inverter configured to receive the third active voltage control signal, and an AND gate configured to receive the output of the inverter and the first active voltage control signal. Internal voltage converter of the memory device. Enabling a first comparator voltage control signal to activate the second comparator and a third comparator, and outputting a first active voltage output signal accordingly; As the first active voltage control signal is enabled, a third active voltage control signal is enabled to activate a fourth comparator and a fifth comparator and thus output a second active voltage output signal; Enabling a particular mode signal; Enabling a second active voltage control signal as the specific mode is enabled; And And disabling a third active voltage control signal as the second active voltage control signal is enabled so that a fourth comparator and a fifth comparator are not communicated with each other. The internal voltage converter of claim 6, wherein the specific mode is a self refresh mode.