KR19980020622A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

Disclosed are a semiconductor memory device having an alignment key pattern for laser repair and a method of manufacturing the same. The semiconductor memory device includes an alignment key pattern formed in a scribe line or a test element group (TEG) to align a repair fuse formed in a redundancy circuit unit. The key pattern is formed of the same conductive layer as the fuse formed in the redundancy circuit. Therefore, a case in which the fuse and the alignment key pattern do not deviate from each other does not occur, and when the laser is driven in accordance with the alignment key pattern, the laser beam may be completely cut in the fuse roll.

Description

Semiconductor memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device having an alignment key pattern for repairing a repair fuse and a method of manufacturing the same.

In semiconductor devices, fuses are commonly used to repair memory cells through repair, and replacing a defective cell with a redundancy cell is a redundancy decoder corresponding to an address of a main cell to be replaced. ) Is cut by using a technique such as a laser beam.

On the other hand, as semiconductor memory devices become more integrated, a greater number of redundancy cells and a larger number of fuses are required to repair them. Accordingly, the gaps and widths of the fuses are narrower, and thus a more precise manufacturing process is required, which means that fuses having fine intervals are accurately aligned to cut fuses corresponding to defective cells. . To this end, alignment between semiconductor memory devices and manufacturing equipment has become an important requirement.

Alignment in the manufacturing process of a general semiconductor device is irradiated and reflected by the alignment key pattern formed in the semiconductor substrate by the laser in the alignment part of a stepper, and at this time, from an alignment key pattern The detection unit recognizes the difference in reflectance of the reflected light to determine the direction or position of the semiconductor substrate, and then adjusts the semiconductor substrate and the equipment.

1A through 4B are cross-sectional views illustrating a method of forming a fuse and an alignment key pattern according to the related art, wherein each a is a decoding portion of a redundancy cell in which a fuse is formed, and each b is an alignment key pattern. Indicates a site.

1A and 1B, a field oxide film 3 defining an active region and a device isolation region is formed on a semiconductor substrate 1, and a substructure (not shown) such as a transistor is formed, and then A first interlayer insulating layer 5 is formed, a conductive material is deposited on the resultant on which the first interlayer insulating layer 5 is formed, and then patterned to form bit lines (not shown) in the main cell array portion and the redundancy cell array portion. In the redundant cell decoding unit, a fuse 7 is formed. In this case, the bit line and the fuse 7 are typically formed of a polyside structure in which a polysilicon layer and a tungsten silicide layer are stacked.

2A and 2B, a second interlayer insulating layer 9 is formed on the entire surface of the resultant product in which the fuse 7 is formed, and metal, for example, aluminum is deposited thereon, and then patterned to form a main cell array and a redundancy cell array. The metal lines 11 are formed in the unit and the redundancy cell decoding unit, and the alignment key patterns 11 'are formed in the scribe line or the test element group (hereinafter referred to as TEG).

Referring to FIGS. 3A and 3B, a protective film 13 is formed by depositing an insulator such as BPSG on the entire surface of the resultant metal line 11 and the alignment key pattern 11 ′.

Referring to FIGS. 4A and 4B, the passivation layer 13 is patterned to partially expose the metal wiring 11, and the alignment key pattern 11 ′ and the second interlayer insulating layer 9 surrounding the alignment key pattern 11 ′ are exposed. The second interlayer insulating layer 9 on the fuse 7 is exposed.

According to the conventional method as described above, the fuse 7 and the alignment key pattern 11 ′ are different from each other, for example, when the fuse 7 forms a bit line, the alignment key pattern 11 ′ forms a metal wiring. It is formed in the city. Therefore, the fuse cutting process should be performed while the two different layers, that is, the mask for forming the fuse 7 and the mask for forming the alignment key pattern, are aligned, which reduces the margin of the process. Becomes In other words, even if the laser is driven in accordance with the alignment key pattern 11 ', when the alignment of the mask for forming the fuse 7 is misaligned, the laser beam may not cut the fuse correctly. If the fuse is incompletely cut in this way, the repair cannot be made normally.

The above problem is caused when the photo process equipment used for forming the alignment key pattern and the fuse is different (normally, since the bit lines are formed in a fine pattern compared to the metal wiring, patterning is performed using different photo process equipment). It is more serious, and it is more serious because the higher the integration, the narrower the gap between the fuses.

Accordingly, an object of the present invention is to solve the above problems and to provide a semiconductor memory device having an alignment key pattern formed on the same layer as a fuse.

Another object of the present invention is to provide a manufacturing method suitable for manufacturing the semiconductor memory device.

1A through 4B are cross-sectional views illustrating a method of forming a fuse and an alignment key pattern according to the related art.

5A and 5B are cross-sectional views illustrating an alignment key pattern according to an embodiment of the present invention.

6A to 9B are cross-sectional views illustrating a method for manufacturing an alignment key pattern according to an embodiment of the present invention.

In order to achieve the above object, the present invention provides a semiconductor having an align line pattern formed in a scribe line or a test element group (TEG) for aligning a repair fuse formed in a redundant circuit unit. The memory device of claim 1, wherein the alignment key pattern is formed of the same conductive layer as the fuse formed in the redundancy circuit.

Here, the conductive layer is a conductive layer for forming a bit line in the memory cell array unit, and the conductive layer is preferably formed of a structure in which polysilicon and tungsten silicide are laminated.

In order to achieve the above object, the present invention, the first step of forming a first interlayer insulating layer on a semiconductor substrate formed with a lower structure, such as a transistor; Depositing a conductive material on the entire surface of the resultant material on which the first interlayer insulating layer is formed, and then patterning the conductive material to form an alignment key pattern for a bit line, a fuse, and a laser repair; A third step of forming a second interlayer insulating layer on the entire surface of the resultant product; Selectively removing the second interlayer insulating layer to expose the alignment key pattern for the laser repair; A fifth step of depositing a conductive material on the entire surface of the resultant to which the alignment key pattern is exposed and then patterning the metal wires; And a sixth step of forming a protective film on the entire surface of the resultant metal wiring and then patterning the semiconductor layer to expose a portion of the metal wiring, a fuse, and a second interlayer insulating layer over the peripheral portion thereof. to provide.

In this case, after the sixth step, the method further comprises etching the second interlayer insulating layer formed on the fuse and its surroundings to a predetermined depth so that a part of the second interlayer insulating layer formed on the fuse remains to facilitate cutting of the fuse. can do.

Therefore, when the laser is driven in accordance with the alignment key pattern, the laser beam can be completely cut in the fuse roll.

Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.

5A and 5B are cross-sectional views illustrating an alignment key pattern according to an exemplary embodiment of the present invention. FIG. 5A illustrates a portion where a fuse is formed, and FIG. 5B illustrates a portion where an alignment key pattern is formed. .

5A and 5B, a field oxide film 53 is formed on a semiconductor substrate 51 divided into a memory cell array unit, a peripheral circuit unit, a redundancy cell array unit, and a redundancy circuit unit. A first interlayer insulating layer 55 is formed thereon to insulate a substructure (not shown) such as a transistor or the like. Bit lines (not shown), fuses 57, and alignment key patterns 57 ′ are formed on the first interlayer insulating layer 55 using the same conductive layer, wherein the bit lines are a memory cell array. And a fuse 57 are formed in a redundancy circuit in which a redundancy cell decoder or the like is formed, and the align key pattern 57 'is formed at the edge of a chip such as a scribe line or a TEG. Is formed.

Meanwhile, a second interlayer insulating layer 59 is formed to cover an area except for the alignment key pattern 57 ', and the metal wiring 61 formed of, for example, aluminum on the second interlayer insulating layer 59. Is formed, and a passivation layer 63 is formed which covers an area except for the second interlayer insulating layer 59 and the upper portion of the metal wiring 61 on the fuse 57.

The repair process of the defective cell first recognizes the difference in reflectance of the light reflected from the alignment key pattern 57 'by the stepper detection unit, adjusts the direction of the semiconductor substrate and the position of the laser for fuse cutting, and then By irradiating the fuse to cut the fuse to form a current path of the redundancy cell corresponding to the defective cell.

Meanwhile, according to the exemplary embodiment of the present invention as described above, since the fuse 57 and the alignment key pattern 57 'are formed of the same conductive layer, the fuse and the alignment key pattern are different from each other. It is not generated, and thus driving the laser in accordance with the alignment key pattern allows the laser beam to be completely cut in the fuse roll.

6A to 9B are cross-sectional views illustrating a method of manufacturing an alignment key pattern according to an exemplary embodiment of the present invention, wherein a is a portion where a fuse is formed, and b is a portion where the alignment key is formed. Indicates.

First, referring to FIGS. 6A and 6B, a field oxide film 53 defining an active region and a device isolation region is formed on a semiconductor substrate 51 using a conventional device isolation process, and a substructure (such as a transistor) may be formed. (Not shown), and then depositing an insulating material such as high temperature oxide or BPSG on the entire surface of the resultant to form the first interlayer insulating layer 55. Subsequently, a conductive layer is formed by depositing a conductive material on the resultant on which the first interlayer insulating layer 55 is formed, and then patterning to form a bit line (not shown) in the memory cell array unit and the redundancy cell array unit. A fuse 57 is formed in the circuit portion, and an align key pattern 57 'is formed outside the chip such as a scribe line or a tag.

In this case, the alignment key pattern 57 ', the bit line, and the fuse 57 may be formed of a polyside structure in which a polysilicon layer and a tungsten silicide layer are stacked, and the alignment key pattern 57' may be formed as X. It is preferable to form three or more places in a direction and a Y direction.

Referring to FIGS. 7A and 7B, a second interlayer insulating layer 59 may be formed on the entire surface of the resultant in which the fuse 57 is formed to deposit an insulator such as high temperature oxide or BPSG to insulate the bit line, and then the freeze. The in key pattern 57 'is patterned to be exposed.

In this case, the patterning process may be performed simultaneously with the bit line contact hole etching in the main cell array unit and the redundancy cell array unit, and the second interlayer insulating layer 59 around the second interlayer insulating layer 59 is completely exposed so that the alignment key pattern is completely exposed. It is preferable to etch a predetermined depth.

8A and 8B, for example, aluminum is deposited on the entire surface of the resultant layer on which the second interlayer insulating layer 59 is formed, and then patterned to form a metal wiring 61, and an insulating material such as BPSG is formed on the front surface of the resultant. By depositing, a protective film 63 is formed.

9A and 9B, the passivation layer 63 is patterned to expose the metal wiring 61, and the fuse 57 and the second interlayer insulating layer 59 are disposed on the upper portion of the protective layer 63. In this case, when the protection layer 63 is etched, the fuse 57 and the second interlayer insulating layer 59 formed over the peripheral portion are etched to a predetermined depth so that a part of the second interlayer insulating layer remains on the fuse 57. It is preferable to make cutting 57 easier.

As described above, according to the exemplary embodiment of the present invention, since the fuse and the alignment key pattern are formed of the same conductive layer as in the related art, a case in which the fuse and the alignment key pattern are not shifted from each other does not occur, and thus, the alignment key By driving the laser to the pattern, the laser beam can be completely cut out of the fuse roll.

Claims (5)

A semiconductor memory device having an align key pattern formed in a scribe line or a test device group (TEG) for aligning a repair fuse formed in a redundancy circuit unit. And the alignment key pattern is formed of the same conductive layer as the fuse formed in the redundancy circuit. The semiconductor memory device of claim 1, wherein the conductive layer is a conductive layer for forming a bit line in the memory cell array unit. The semiconductor memory device of claim 1, wherein the conductive layer has a structure in which polysilicon and tungsten silicide are stacked. A first step of forming a first interlayer insulating layer on a semiconductor substrate on which a lower structure such as a transistor is formed; Depositing a conductive material on the entire surface of the resultant material on which the first interlayer insulating layer is formed, and then patterning the conductive material to form an alignment key pattern for a bit line, a fuse, and a laser repair; A third step of forming a second interlayer insulating layer on the entire surface of the resultant product; Selectively removing the second interlayer insulating layer to expose the alignment key pattern for the laser repair; A fifth step of depositing a conductive material on the entire surface of the resultant to which the alignment key pattern is exposed and then patterning the metal wires; And And a sixth step of forming a protective film on the entire surface of the resultant metal wiring and then patterning the metal layer to expose a portion of the metal wiring, a fuse, and a second interlayer insulating layer over the peripheral portion thereof. The method of claim 4, after the sixth step, etching the fuse and the second interlayer insulating layer formed on the upper portion of the fuse to a predetermined depth to leave a part of the second interlayer insulating layer formed on the fuse to facilitate cutting of the fuse. Method for manufacturing a semiconductor memory device characterized in that it further comprises.