KR19980020521A - Bipolar Transistors and Manufacturing Method Thereof - Google Patents
Bipolar Transistors and Manufacturing Method Thereof Download PDFInfo
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- KR19980020521A KR19980020521A KR1019960039016A KR19960039016A KR19980020521A KR 19980020521 A KR19980020521 A KR 19980020521A KR 1019960039016 A KR1019960039016 A KR 1019960039016A KR 19960039016 A KR19960039016 A KR 19960039016A KR 19980020521 A KR19980020521 A KR 19980020521A
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- channel stop
- breakdown voltage
- stop layer
- semiconductor substrate
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- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 230000015556 catabolic process Effects 0.000 abstract description 19
- 238000000034 method Methods 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 2
- 238000007689 inspection Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 238000005530 etching Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Abstract
소자의 내압 측정시 스파크가 발생하는 것을 방지할 수 있는 구조를 갖는 바이폴라 트랜지스터 제조방법이 개시되어 있다.Disclosed is a method of manufacturing a bipolar transistor having a structure capable of preventing sparks from occurring when measuring the breakdown voltage of an element.
본 발명은 제 1 도전형의 반도체 기판의 표면 영역에 선택적으로 제 2 도전형 불순물을 첨가하여 베이스층을 형성하는 단계; 상기 베이스층의 표면 영역과 상기 반도체 기판의 표면 영역에 선택적으로 제 1 도전형 불순물을 첨가하여 에미터층과 채널스톱층을 각각 형성하는 단계; 상기 채널스톱층의 상부에 절연막을 형성하는 단계를 포함하는 것을 특징으로 한다.The invention provides a method for forming a base layer by selectively adding a second conductivity type impurity to a surface region of a semiconductor substrate of a first conductivity type; Selectively adding a first conductivity type impurity to the surface region of the base layer and the surface region of the semiconductor substrate to form an emitter layer and a channel stop layer, respectively; And forming an insulating film on the channel stop layer.
따라서, 본 발명은 고내압 소자의 내압 측정시 스파크가 발생하는 것을 방지함으로써 소자의 전기적 특성 검사 효율 및 신뢰성을 향상시킬 수 있는 효과가 있다.Therefore, the present invention has the effect of improving the electrical characteristics inspection efficiency and reliability of the device by preventing the occurrence of sparks when measuring the breakdown voltage of the high breakdown voltage device.
Description
본 발명은 바이폴라 트랜지스터 및 그 제조방법에 관한 것으로서, 특히 소자의 내압 측정시 스파크가 발생하는 것을 방지할 수 있는 구조를 갖는 바이폴라 트랜지스터 및 그 제조방법에 관한 것이다.The present invention relates to a bipolar transistor and a method of manufacturing the same, and more particularly, to a bipolar transistor having a structure capable of preventing the occurrence of sparks when measuring the breakdown voltage of the device and a method of manufacturing the same.
일반적으로, 일련의 반도체 제조공정으로 웨이퍼를 가공하여 소자를 완성한 후 웨이퍼를 칩 단위로 절단하여 조립 공정에 들어가기 전에 반도체 소자의 전기적 특성을 시험하여 개별 반도체 칩의 양, 불량을 판정하는 작업이 실시된다.In general, after processing a wafer through a series of semiconductor manufacturing processes to complete the device, the wafer is cut into chips and the electrical properties of the semiconductor device are tested before entering the assembly process to determine the quantity and defect of individual semiconductor chips. do.
소자의 내압 특성 검사시 저내압 소자의 경우에는 저전압이 인가되기 때문에 문제가 발생하지 않지만 약 2000 볼트 이상이 인가되는 고내압 소자의 경우에는 소자의 구성요소 간에 방전이 일어나 스파크가 발생하여 내압 측정이 어렵게 된다.When checking the breakdown voltage characteristics of the device, a low voltage device does not cause a problem because a low voltage is applied.However, in the case of a high breakdown voltage device having a voltage of about 2000 volts or more, a discharge occurs between components of the device, causing sparks, Becomes difficult.
도 1 을 참조하면, 종래의 바이폴라 트랜지스터에서는 스크라이브 라인 영역에 형성된 채널 스톱층(20) 표면에 절연막이 형성되지 않으며 이로 인하여 바이폴라 트랜지스터의 베이스-콜렉터 간 내압 측정시 콜렉터층와 등전위를 갖게 되는 채널 스톱층(20) 영역에서 스파크가 발생하게 된다.Referring to FIG. 1, in the conventional bipolar transistor, an insulating film is not formed on the surface of the channel stop layer 20 formed in the scribe line region, and thus, a channel stop layer having an equipotential with the collector layer when measuring the breakdown voltage between the base and the collector of the bipolar transistor. Sparks occur in the region (20).
소자의 내압 측정시 스파크가 발생하게 되면 누설 전류로 인하여 기울어진 내압 파형이 발생하거나 항복전압 근처에서 파형이 불안정하게 되어 소자의 정확한 내압 특성을 확인할 수 없게 된다.When spark is generated during breakdown voltage measurement, the breakdown voltage waveform is generated due to leakage current or the waveform becomes unstable near the breakdown voltage, and thus the accurate breakdown voltage characteristic of the device cannot be confirmed.
따라서, 종래의 기술에 있어서는 소자의 내압 측정은 조립이 완성된 후에나 가능하게 되어 불량 칩을 조립공정 전에 선별하지 못하므로 제조원가가 증가하는 문제점이 있었다.Therefore, in the related art, the breakdown voltage of the device can be measured after the assembly is completed, so that the defective chip cannot be sorted before the assembly process, thereby increasing the manufacturing cost.
본 발명의 목적은 소자의 내압 측정시 스파크가 발생하는 것을 방지할 수 있는 구조를 가진 바이폴라 트랜지스터 및 그 제조방법을 제공하는 데 있다.An object of the present invention is to provide a bipolar transistor having a structure capable of preventing the occurrence of sparks when measuring the breakdown voltage of the device and a method of manufacturing the same.
상기 목적을 달성하기 위한 본 발명의 바이폴라 트랜지스터는, 채널스톱층을 갖는 바이폴라 트랜지스터에 있어서, 상기 채널 스톱층 영역의 상부에 절연막이 형성된 것을 특징으로 한다.In the bipolar transistor of the present invention for achieving the above object, in the bipolar transistor having a channel stop layer, an insulating film is formed on the channel stop layer region.
또한, 본 발명의 바이폴라 트랜지스터 제조방법은 제 1 도전형의 반도체 기판의 표면 영역에 선택적으로 제 2 도전형 불순물을 첨가하여 베이스층을 형성하는 단계; 상기 베이스층의 표면 영역과 상기 반도체 기판의 표면 영역에 선택적으로 제 1 도전형 불순물을 첨가하여 에미터층과 채널스톱층을 각각 형성하는 단계; 상기 채널스톱층의 상부에 절연막을 형성하는 단계를 포함하는 것을 특징으로 한다.In addition, the bipolar transistor manufacturing method of the present invention comprises the steps of forming a base layer by selectively adding a second conductivity type impurities to the surface region of the first conductivity type semiconductor substrate; Selectively adding a first conductivity type impurity to the surface region of the base layer and the surface region of the semiconductor substrate to form an emitter layer and a channel stop layer, respectively; And forming an insulating film on the channel stop layer.
도 1 은 종래의 고내압 바이폴라 트랜지스터의 구조를 나타내는 도면.1 is a view showing the structure of a conventional high breakdown voltage bipolar transistor;
도 2 는 본 발명의 고내압 바이폴라 트랜지스터의 구조를 나타내는 도면.2 is a diagram showing the structure of a high breakdown voltage bipolar transistor of the present invention;
도 3 의 (a) 내지 (c) 는 본 발명의 바이폴라 트랜지스터 제조방법을 설명하기 위한 도면.3 (a) to 3 (c) are views for explaining the bipolar transistor manufacturing method of the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of the drawings
10,40 : 반도체 기판12,44 : P- 베이스층10,40: semiconductor substrate 12,44: P-base layer
14,46 : 필드리미트링16,50 : P+ 불순물층14,46: field limit ring 16,50: P + impurity layer
18,54 : N+ 에미터층20,56 : N+ 채널스톱층18,54: N + emitter layer 20,56: N + channel stop layer
22 : 절연막24 : 베이스전극22: insulating film 24: base electrode
26 : 에미터전극 28 : 채널스톱전극26 emitter electrode 28 channel stop electrode
30 : 보호막42,48,52 : 실리콘산화막30: protective film 42, 48, 52: silicon oxide film
이하, 본 발명의 구체적인 실시예를 나타내는 첨부된 도면을 참조하여 더욱 상세히 설명한다.Hereinafter, with reference to the accompanying drawings showing a specific embodiment of the present invention will be described in more detail.
도 2 를 참조하면, 본 발명의 일 실시예에 따른 바이폴라 트랜지스터는 바이폴라 트랜지스터의 콜렉터층을 이루는 N형의 반도체 기판(10)에 형성된 P- 베이스층(12), 베이스층(12)의 표면 영역에 형성된 N+ 에미터층(18)과 P+ 불순물층(16), P+ 불순물층(16)에 접속된 베이스전극(24), N+ 에미터층(18)에 접속된 에미터전극(26), 내압을 향상시키기 위한 필드리미트링 영역(14), 누설전류를 감소시키기 위한 채널스톱층(20) 및 상기 채널스톱층(20)에 접속된 채널스톱전극(28)으로 구성되며, 또한 상기 전극(24,26,28)들은 절연막(22)으로 분리되어 있으며 상기 채널스톱전극(28)과 상기 채널스톱층(20)은 절연막(22)으로 덮여 있다.Referring to FIG. 2, a bipolar transistor according to an embodiment of the present invention includes a surface region of a P-base layer 12 and a base layer 12 formed on an N-type semiconductor substrate 10 forming a collector layer of a bipolar transistor. The N + emitter layer 18 and the P + impurity layer 16 formed on the base electrode 24 connected to the P + impurity layer 16, the emitter electrode 26 connected to the N + emitter layer 18, and the breakdown voltage are improved. And a channel stop electrode 28 connected to the channel stop layer 20 and a channel stop layer 20 for reducing leakage current, and also the electrodes 24 and 26. 28 are separated by an insulating film 22, and the channel stop electrode 28 and the channel stop layer 20 are covered with the insulating film 22.
상기와 같이 구성된 본 발명의 바이폴라 트랜지스터에서는 상기 절연막(22)이 베이스-콜렉터 간의 내압 측정시 인가되는 고전압으로부터 상기 채널 스톱층(20)을 전기적으로 절연시키게 되므로 내압 측정시 채널 스톱층 영역(20)에서 스파크가 발생하지 않게 된다.In the bipolar transistor of the present invention configured as described above, the insulating layer 22 electrically insulates the channel stop layer 20 from the high voltage applied during the breakdown voltage measurement between the base and the collector. Sparks will not occur in the
상기와 같은 구조를 갖는 바이폴라 트랜지스터의 제조방법을 도 3 을 참조하여 설명하면 다음과 같다.A method of manufacturing a bipolar transistor having the above structure will be described with reference to FIG. 3.
먼저 도 3 (a) 를 참조하면, N형의 반도체 기판 표면(40)에 실리콘산화막(42)을 형성하고 통상의 사진 및 식각공정으로 상기 실리콘산화막(42)을 선택적으로 제거하여 베이스 형성창과 필드리미트링 형성창을 개방한 다음, 상기 반도체 기판(40)에 P형의 불순물을 주입하여 P- 베이스층(44)과 P- 필드리미트링(46)을 형성한다.First, referring to FIG. 3A, a silicon oxide film 42 is formed on an N-type semiconductor substrate surface 40, and the silicon oxide film 42 is selectively removed by a conventional photographic and etching process. After opening the limit ring forming window, P-type impurities are implanted into the semiconductor substrate 40 to form the P-base layer 44 and the P-field limit ring 46.
이어서, 반도체 기판 전면에 실리콘산화막(48)을 형성하고 통상의 사진 및 식각공정으로 상기 실리콘산화막(48)을 선택적으로 제거하여 상기의 베이스 형성창을 개방한 후 상기 반도체 기판(40)에 N형의 불순물을 주입하여, 도 3 (b) 에 도시된 바와 같이, 베이스전극이 접속될 P+ 불순물층(50)을 형성한다.Subsequently, a silicon oxide film 48 is formed on the entire surface of the semiconductor substrate, and the silicon oxide film 48 is selectively removed by a general photograph and an etching process to open the base forming window, and then an N type on the semiconductor substrate 40. Is implanted to form a P + impurity layer 50 to which the base electrode is connected, as shown in FIG.
그 다음, 반도체 기판 전면에 실리콘산화막(52)을 형성하고 통상의 사진 및 식각공정으로 상기 실리콘산화막(52)을 선택적으로 제거하여 에미터 형성창과 채널스톱층 형성창을 개방한 후 N형의 불순물을 주입하여, 도 3 (c) 에 도시된 바와 같이, N+ 에미터층(54)과 N+ 채널스톱층(56)을 각각 형성한다.Next, a silicon oxide film 52 is formed on the entire surface of the semiconductor substrate, and the silicon oxide film 52 is selectively removed by a conventional photolithography and etching process to open the emitter forming window and the channel stop layer forming window, and then n-type impurities. Is injected to form an N + emitter layer 54 and an N + channel stop layer 56, respectively, as shown in FIG.
이후 상기 반도체 기판 전면에 실리콘산화막을 형성하고 사진 및 식각공정으로 상기 실리콘산화막을 선택적으로 제거하여 콘택홀을 형성한 다음 금속배선공정으로 금속전극을 형성하고 보호막을 침적한 후 상기 보호막을 선택적으로 제거하여 패드를 형성하여 도 2 와 같은 바이폴라 트랜지스터를 완성하게 되는데, 이때 웨이퍼의 스크라이브 라인 영역상의 상기 보호막이 제거되어도 상기 채널스톱층의 표면에는 앞 공정에서 형성된 실리콘산화막이 남게 된다.Thereafter, a silicon oxide film is formed on the entire surface of the semiconductor substrate, and the silicon oxide film is selectively removed by a photo and etching process to form a contact hole, a metal electrode is formed by a metal wiring process, a protective film is deposited, and then the protective film is selectively removed. By forming a pad to complete a bipolar transistor as shown in FIG. 2, the silicon oxide film formed in the previous process remains on the surface of the channel stop layer even if the protective film on the scribe line region of the wafer is removed.
따라서, 본 발명은 고내압 소자의 내압 측정시 스파크가 발생하는 것을 방지함으로써 소자의 전기적 특성 검사 효율 및 신뢰성을 향상시킬 수 있는 효과가 있다.Therefore, the present invention has the effect of improving the electrical characteristics inspection efficiency and reliability of the device by preventing the occurrence of sparks when measuring the breakdown voltage of the high breakdown voltage device.
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| KR1019960039016A KR100490333B1 (en) | 1996-09-09 | 1996-09-09 | Bipolar Transistors and Manufacturing Method |
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| KR1019960039016A KR100490333B1 (en) | 1996-09-09 | 1996-09-09 | Bipolar Transistors and Manufacturing Method |
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| KR100490333B1 KR100490333B1 (en) | 2006-04-28 |
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| KR (1) | KR100490333B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230064284A (en) | 2021-11-03 | 2023-05-10 | 임대영 | Smart Timer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6080273A (en) * | 1983-10-07 | 1985-05-08 | Nec Corp | Semiconductor device of high withstand voltage |
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1996
- 1996-09-09 KR KR1019960039016A patent/KR100490333B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230064284A (en) | 2021-11-03 | 2023-05-10 | 임대영 | Smart Timer |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100490333B1 (en) | 2006-04-28 |
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