KR19980018532A - Phase locked loop circuit - Google Patents

Abstract

In PLL circuits with first and second PLL loops in which the crystal oscillator acts as a reference frequency source, the object of the present invention is to use a reference signal having a frequency higher than the oscillation frequency in the crystal oscillator, which is stable even when the supply voltage is reduced. It is to provide a PLL circuit that can obtain frequency characteristics. In the first PLL circuit, the input reference signal is multiplied and output as an output signal. The output signal from the first PLL loop is used as the reference signal for the second PLL loop. The output signal is output externally from the second PLL loop. When the crystal oscillator acts as a reference signal source for the first PLL loop, a frequency higher than the oscillation frequency is used as the reference signal in the crystal oscillator.

Description

Phase locked loop circuit

The present invention relates to a PLL circuit, and more particularly, to a PLL (phase locked loop) circuit using two feedback circuits.

Since the PLL circuit has used a crystal oscillator with good frequency accuracy as a reference signal source so far, a PLL circuit with good frequency accuracy is realized.

A conventional PLL circuit is described below with reference to the drawings.

1 is a block diagram showing a configuration example of a conventional PLL circuit. It should be noted that the desired frequency output FOUT in this conventional PLL circuit is obtained from the voltage controlled oscillator 303 (hereinafter referred to as VCO in the following figures and the following description).

As shown in Fig. 1, the conventional PLL circuit includes a crystal oscillator 301 for generating a reference frequency signal and outputting the frequency signal, and a frequency divider circuit 302 for dividing the reference frequency signal supplied from the crystal oscillator. And a VCO 303 which generates an output frequency signal in accordance with the supplied voltage and outputs it, a frequency divider circuit 304 which divides the output frequency signal supplied from the VCO 303, and a frequency divider circuit 302. Phase comparator 305 for comparing the phase of the output from the phase with the output of the frequency divider circuit 304 and outputting a comparison result, and a row for converting the comparison result supplied from the phase comparator 305 into voltage. Pass filter 306 (hereinafter referred to as LPF in the figures and in the following description). The LPF 306 is connected to the VCO 303 so that the voltage output from the LPF is applied to the VCO 303.

The operation of the PLL circuit configured as described above is as follows.

First, the reference frequency signal fR is generated in the crystal oscillator 301 and output from it to the frequency divider circuit 302. After the signal fR is output to the frequency divider circuit 302, the signal fR is divided so that a signal having a frequency equal to fR / n is generated by the frequency divider circuit 302.

On the other hand, the output frequency signal fOUT is generated by the VCO 303 and output from the frequency divider circuit 304 therefrom. After the signal fOUT is output to the frequency divider circuit 304, the signal fOUT is divided by the frequency divider circuit 304 so that a signal having a frequency equal to fOUT / k is generated by the circuit 304.

Then, in the phase comparator 305, the phase of the output from the frequency divider circuit 302 is compared with the phase of the output from the frequency divider circuit 304. Since the output frequencies of the frequency divider circuits 302 and 304 are different from each other, signals that depend on the difference are output from the phase comparator 305.

Thereafter, in the LPF 306, the signal output from the phase comparator 305 is converted into a voltage and the voltage VOUT is supplied to the VCO 303.

At VCO 303, an output frequency signal is generated that depends on the voltage VOUT supplied from the LPF. The output frequency signal is output therefrom. Therefore, the output frequency signal fOUT is obtained.

The operation of the phase comparator 305 in the above-described PLL circuit is described in detail below.

FIG. 2 is a circuit diagram showing a configuration example of a phase comparator 305 provided in the PLL circuit shown in FIG.

FIG. 3A is a timing chart for explaining the operation of the phase comparator shown in FIG. 2 when the frequency of the reference signal fIN is higher than the frequency of the input signal fR. FIG. 3B is a timing chart for explaining the operation of the phase comparator shown in FIG. 2 when the frequency of the reference signal fIN is lower than the frequency of the input signal fR.

In the circuit shown in Fig. 2, when the disable signal 401 is at the H level, the circuit stops its operation so that the UP output signal 404 and the DW output signal 405 are at the H level.

On the other hand, when the disable signal 401 is at the L level, the frequencies of the reference signal fR 402 and the input signal fIN 403 are compared, both of which are supplied from the outside of the circuit. As a result of the comparison, when the frequency of the reference signal fIN 402 is higher than the frequency of the input signal fR 403, the UP output signal 404 and the DW output signal 405 show the waveform shown in FIG. 3A. When the frequency of the reference signal fIN 402 is lower than the frequency of the input signal fR 403, they show a waveform as shown in FIG. 3B.

Further, when the frequency and phase of the input signal fIN 403 and the reference signal fR 402 are the same, respectively, the UP and DW output signals 404 and 405 become H level. Therefore, the circuit shown in FIG. 2 stops its operation.

When the circuit described above is used for the phase comparator 305, the LPF 306 causes the LPF 306 to reduce the level of the output voltage VOUT output therefrom after the reception of the UP output signal and output voltage after the reception of the DW output signal. It is configured to increase the level of VOUT.

In addition, the VCO 303 configures the VCO 303 to reduce the output frequency fOUT output therefrom when the supplied voltage VOUT decreases and to increase the output frequency fOUT when the voltage VOUT decreases, so that the frequency is a predetermined value. A PLL circuit that converges is configured.

In the PLL circuit shown in Fig. 1, the output frequency signal fOUT is determined according to the reference frequency signal fR and the frequency division numbers n and k of the frequency divider circuits 302 and 304, and the output frequency signal fOUT is expressed by the following formula. .

fOUT = kfR / n

Where n and k are frequency divider numbers of frequency divider circuits 302 and 304.

Here, a PLL circuit as a means for improving the characteristics is disclosed in Japanese Patent Laid-Open No. 1987-120721.

4 is a block diagram showing the configuration of the PLL circuit disclosed in Japanese Patent Laid-Open No. 1987-120721.

As shown in FIG. 4, a conventional PLL circuit includes a phase comparator 601 and a phase comparator 601 for comparing a phase of two signals supplied thereto and outputting a signal according to a phase difference between the two signals. An extraction unit 602 for extracting a reference frequency component signal from a signal supplied from the N-axis, a booster unit 603 for outputting an AC signal obtained by boosting the reference frequency component signal extracted by the extraction unit 602, A signal switching unit 604 for converting the AC signal supplied from the boosting unit 603 into a DC signal, and an output signal having a repeated frequency in accordance with the DC signal supplied from the signal switching unit 604 and outputting the same; It consists of a voltage controlled oscillation part 603 for following.

Note that the conventional PLL circuit is configured such that an output signal output from the voltage controlled oscillator 605 is supplied to the phase comparator 601.

In the conventional PLL circuit described above, the signal output from the phase comparison unit 601 is extracted by the extraction unit 602. Thereafter, the signal extracted by the extraction unit 602 is boosted by the extraction circuit 603 and supplied to a signal switching unit 604 such as the LPF of the present invention. Therefore, the signal switching section 605 operates at high voltage. As a result, the amount of charge supplied to the voltage controlled oscillator 605 increases, so that the output characteristics of the voltage controlled oscillator 605 are improved.

Further, in the PLL circuit disclosed in Japanese Patent Laid-Open No. 1988-245127, two feedback circuits for outputting different frequency signals are provided, and a lower frequency output signal from one feedback circuit is a reference signal for another feedback circuit. It is used as a high frequency signal is output.

5 is a block diagram showing the configuration of a PLL circuit disclosed in Japanese Laid-Open Patent Publication No. 1988-245127.

As shown in Fig. 5, the conventional PLL circuit disclosed in Japanese Patent Laid-Open No. 1988-245127 is composed of first and second feedback circuits. In the first feedback circuit, a voltage controlled oscillator 701, a synchronous separation circuit 702, a phase comparator 703 and a lowpass filter 704 are provided. Further, in the second feedback circuit using the signal supplied from the first feedback circuit as a reference signal, the voltage controlled oscillator 705, the frequency divider circuit 706, the phase comparator 707 and the low pass filter 708 ) Is provided. The signal output from the second feedback circuit is used as an output frequency signal.

In the first feedback circuit of the conventional PLL circuit configured as described above, the horizontal synchronizing signal of the television composite video signal is regarded as a reference signal and a signal of the same frequency as that of the horizontal synchronizing signal is output. In the second feedback circuit, when the frequency division number determined by the frequency divider circuit 706 is assumed to be n, an output signal of frequency n times higher than the frequency of the horizontal synchronization signal is obtained.

6A is a diagram showing a measurement result of the frequency characteristic of an output signal when the frequency of the reference signal is 25 kH in the PLL circuit of FIG. 6B is a diagram showing a measurement result of the frequency characteristic of the output signal when the frequency of the reference signal is 50 kH in the PLL circuit of FIG. 6C is a diagram illustrating a measurement result of frequency characteristics of an output signal when the frequency of the reference signal is 100 kHz in the PLL circuit of FIG. 1.

When the conventional PLL circuit described above is used in radios, television receivers, etc., the reference frequency is determined according to the reception band and the channel space. As shown in Figs. 6A, 6B and 6C, the frequency accuracy of the output signal of the VCO is better as the frequency of the reference signal is higher. The reason is as follows. When the frequency of the reference signal supplied to the phase comparator is approximately equal to the frequency of the input signal, the signal provided from the phase comparator has the same frequency as the frequency of the reference signal. Therefore, when the frequency of the reference signal is higher, it is possible to respond with higher accuracy to changes in the VCO.

However, if the crystal oscillator acts as a reference frequency source, there are bands that are not reflected by the frequency accuracy in the crystal oscillator. To avoid this situation, the frequency generated by the crystal oscillator must be changed. When the oscillation frequency generated in the crystal oscillator is changed to a high frequency, the output of the frequency divider circuit can be kept constant by increasing the number of frequency dividers in the frequency divider circuit. However, there is a problem that the power consumption current increases in the crystal oscillator.

Further, in the case where the oscillation frequency is changed to low frequency in the crystal oscillator, the output of the frequency divider circuit can be kept constant by decreasing the frequency in the frequency divider circuit. However, since the frequency division number in the frequency divider circuit is more than 1, the frequency of the reference signal cannot be increased to a frequency higher than the oscillation frequency in the crystal oscillator. Also, as described above, when the reference frequency is low, the frequency accuracy of the signal provided from the VCO is degraded. In addition, when the oscillation frequency in the crystal oscillator is low, the crystal oscillator is characterized by not starting oscillation at a low voltage. Therefore, the oscillation frequency itself cannot sometimes be reduced depending on the operating voltage.

Next, the problems involved in the aforementioned PLL circuit disclosed in the two previous techniques are described.

In the PLL circuit shown in Fig. 4 disclosed in Japanese Patent Laid-Open No. 1987-120721, the boosting unit 603 is positioned at a stage before the signal switching unit 604, so that sufficient charge is supplied to the voltage controlled oscillator to operate. do. Therefore, low voltage operation is possible despite the low reference frequency. However, when the synchronization is released due to the variation of the input frequency, a delay such as the maximum reference frequency is generated until the input frequency is transmitted to the phase comparator 601, resulting in a deterioration of the following characteristic due to the low reference frequency. In addition, since the signal switching means is a low pass filter, it is easy to remove a high frequency signal. However, since the signal is not sufficiently removed near the pass band, the unremoved signal is output as noise.

In addition, the PLL circuit shown in FIG. 5 disclosed in Japanese Patent Laid-Open No. 1988-245127 is composed of two feedback circuits. In the feedback circuit of Fig. 5, since the output from the first feedback circuit using the horizontal synchronization signal as the reference signal is used as the reference signal for the second feedback circuit and the output signal is generated in the second feedback circuit, the second feedback circuit is used. The output frequency of the phase comparator is changed when the output of the phase comparator changes due to some factor or when the division value of the frequency divider circuit 706 aligned in the second feedback circuit is changed to change the output of the second feedback circuit. It is limited to the output frequency of the loop, ie the frequency of the horizontal sync signal. Therefore, there is a problem as described above.

SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL circuit which uses a crystal oscillator as a reference frequency source, uses a reference signal with a frequency higher than the oscillation frequency in a crystal oscillator, and obtains stable frequency characteristics even at a reduction time in power supply voltage. .

1 is a block diagram showing a configuration example of a conventional PLL circuit.

FIG. 2 is a circuit diagram showing a configuration example of a phase comparator 305 given to the PLL circuit of FIG.

3A is a timing chart illustrating the operation of the phase comparator of FIG. 2 when the frequency of the reference signal fIN is higher than the frequency of the input signal fR.

FIG. 3B is a timing chart for explaining the operation of the phase comparator of FIG. 2 when the frequency of the reference signal fIN is lower than the frequency of the input signal fR.

4 is a block diagram showing the configuration of a PLL circuit disclosed in Japanese Patent Laid-Open No. 1987-120721.

5 is a block diagram showing the configuration of a PLL circuit disclosed in Japanese Laid-Open Patent Publication No. 1988-245127.

FIG. 6A shows measurement results of frequency characteristics of an output signal when the frequency of the reference signal is set to 25 kHz in the PLL circuit of FIG. 1; FIG.

FIG. 6B shows measurement results of frequency characteristics of the output signal when the frequency of the reference signal is set to 50 kHz in the PLL circuit of FIG.

FIG. 6C shows measurement results of frequency characteristics of the output signal when the frequency of the reference signal is set to 100 kHz in the PLL circuit of FIG. 1; FIG.

Fig. 7 is a block diagram showing Embodiment 1 of the PLL circuit of the present invention.

Fig. 8 is a block diagram showing Embodiment 2 of the PLL circuit of the present invention.

* Description of the symbols for the main parts of the drawings *

301: crystal oscillator 302, 304, 706: frequency divider circuit

303, 701, 705: VCO 305, 601, 703, 707: phase comparators

306, 708: low pass filter 602: extraction unit

603: boosting unit 604: signal switching unit

702: synchronous isolation circuit 704: low pass filter

To achieve the above object, a PLL circuit including a first feedback circuit and a second feedback circuit that outputs a signal to the outside uses a signal obtained by multiplying a reference signal in the first feedback circuit as a reference signal.

In addition, the first feedback circuit includes a crystal oscillator serving as a reference signal source of the first feedback circuit, and a CR oscillator serving as an input signal source of the first feedback circuit and serving as a reference signal source of the second feedback circuit. Wow,

A first frequency divider circuit for dividing an input signal supplied from the CR oscillator and outputting a divided input signal;

Comparing the phase of the reference signal output from the crystal oscillator with the phase of the divided input signal in the first frequency divider circuit and outputting a signal according to the phase difference between the reference signal and the phases of the divided input signal. 1 phase comparator,

And a first lowpass filter converting the signal output from the first phase comparator into a voltage and returning the voltage to the CR oscillator.

The second feedback circuit includes a voltage controlled oscillator serving as an input signal source for the second feedback circuit;

A second frequency divider circuit for dividing a reference signal supplied from the CR oscillator and outputting a divided reference signal;

A third frequency divider circuit for dividing an input signal supplied from the voltage controlled oscillator and outputting the divided input signal to a second phase comparator;

Compare the phase of the reference signal divided in the second frequency divider circuit with the phase of the divided input signal output from the voltage controlled oscillator and divided in the third frequency divider circuit, and the divided reference signal and the divided A second phase comparator for outputting a signal in accordance with the phase difference between the phases of the input signal,

And a second lowpass filter for switching the signal supplied from the second phase comparator and returning this voltage to the voltage controlled oscillator.

In addition, the first feedback circuit may include a crystal oscillator serving as a reference signal source for the first feedback circuit;

A CR oscillator serving as an input signal source for the first feedback circuit and serving as a reference signal source for the second feedback circuit;

A first frequency divider circuit for dividing an input signal supplied from the CR oscillator and outputting a divided input signal;

A second frequency divider circuit for dividing an input signal divided by the first frequency divider circuit and outputting the divided signal;

Comparing the phase of the input signal output from the CR oscillator and divided in the first and second frequency divider circuits with the phase of the reference signal output from the crystal oscillator, and between the phase of the reference signal and the phase of the input signal. A first phase comparator for outputting a signal in accordance with a phase difference of;

A first lowpass filter converting the signal output from the phase comparator into a voltage and returning the voltage to the CR oscillator,

The second feedback circuit includes a voltage controlled oscillator serving as an input signal source of the second feedback circuit;

A third frequency divider circuit for dividing an input signal output from the voltage controlled oscillator to output a divided input signal;

Comparing the phase of the reference signal output from the CR oscillator and divided in the first frequency divider circuit with the phase of an input signal divided in the third frequency divider circuit, and comparing the phase of the reference signal and the divided input signal. A second phase comparator for outputting a signal in accordance with the phase difference between the phases of

And a second low pass filter converting the signal output from the second phase comparator into a voltage and returning the voltage to the voltage controlled oscillator.

In addition, the frequency of the input signal from the CR oscillator is controlled according to the signal converted into a voltage in the first low pass filter.

In addition, the frequency of the input signal from the voltage controlled oscillator is controlled in accordance with the signal converted into a voltage in the second low pass filter.

Further, the frequency division number of the second frequency divider circuit is set to be changeable.

According to the PLL circuit of the present invention, in the first feedback circuit, the reference signal input is multiplied and output as an output signal, and the output signal from the first feedback circuit is used as the reference signal in the second feedback circuit, so that the second feedback circuit is used. The output signal from is output to the outside.

As described above, since the reference signal in the second feedback circuit that outputs the output signal to the PLL circuit is a signal having a frequency higher than the frequency of the reference signal in the first feedback circuit, the crystal oscillator is referred to in the first feedback circuit. When acting as a signal source, a frequency higher than the oscillation frequency in the crystal oscillator is used as the reference signal so that a stable frequency characteristic can be obtained even when the power supply voltage is reduced.

In addition, the frequency of the reference signal is easily removed in the low pass filter, and the resave rate is increased at the frequency change, so that the signal / noise characteristic can be improved.

In addition, the oscillation speed of the crystal oscillator is reduced, so that the current consumed can be reduced.

The above and other objects, features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of preferred embodiments of the present invention.

(Example 1)

Fig. 7 is a block diagram showing Embodiment 1 of the PLL circuit of the present invention.

As shown in Fig. 7, the PLL circuit of this embodiment is composed of first and second feedback circuits. In the first feedback circuit, the crystal oscillator 101 acts as a reference signal source for the first feedback circuit, and serves as an input signal for the first feedback circuit as well as acts as a reference signal source for the second feedback circuit. A phase and a first frequency divider circuit of the reference signal supplied from the CR oscillator 102, the first frequency divider circuit 103 for dividing the input signal provided from the CR oscillator 102, From the first phase comparator 104 and the first phase comparator 104 which compare the phase of the input signal output from the CR oscillator 102 divided by the 103 and output the signal according to the phase difference between the two phases. A first LPF 105 which converts the supplied signal into a voltage and supplies this voltage to the CR oscillator 102.

In a second PLL loop, a VCO 106 serving as an input signal source for the second feedback circuit, and a second frequency divider circuit for dividing the reference signal supplied from the CR oscillator 102 to output the divided reference signal. 107, a third frequency divider circuit 108 for dividing the input signal supplied from the VCO 106 and outputting the divided input signal, and a CR oscillator 102 to be divided in the frequency divider circuit 107. A second phase which compares the phase of the reference signal output from the phase of the input signal output from the VCO 106 to be divided in the frequency divider circuit 108 and outputs the signal according to the phase difference between the reference signal and the input signal. A comparator and a second LPF 110 are provided which convert the signal supplied from the phase comparator 109 into a voltage and supply this voltage to the VCO 106.

The operation of the PLL circuit configured as described above is described below.

First, the reference signal fOSC is output from the crystal oscillator 101 as a reference signal for the first feedback circuit, and the frequency signal fR is output from the CR oscillator 102 as an input signal for the first feedback circuit.

The input signal fR output from the CR oscillator 102 is divided by 1 / n in the frequency divider circuit 103 and the divided signal is input to the phase comparator 104. At the same time, the reference signal fOSC output from the crystal oscillator 101 is input to the phase comparator 104.

Here, the reference signal fOSC output from the crystal oscillator 101 is directly input to the phase comparator 104 without passing through the frequency divider circuit, in order to increase the frequency accuracy of the CR oscillator 102.

Thereafter, the phase comparator 104 compares the phase of the input signal fR / n and the phase of the reference signal fOSC supplied thereto to output a phase difference between the input signal fR / n and the reference signal fOSC.

The phase difference output from the phase comparator 104 is converted into a voltage in accordance with the value of the phase difference in the LPF 105 and supplied to the CR oscillator 102.

The frequency of the frequency signal fR is controlled by the CR oscillator 102 in accordance with the voltage supplied from the LPF 105.

At this time, the frequency fR output from the CR oscillator 102 is expressed by the following formula when the first feedback circuit is in a stable state.

fR = n fOSC

Where n is the frequency divider number of the frequency divider 103.

On the other hand, when the frequency signal fOUT is output from the VCO 106 as an input signal to the second feedback circuit, the input signal fOUT output from the VCO 106 is divided by 1 / m by the frequency divider circuit 108. The divided signal is input to the phase comparator 109.

In addition, the frequency signal fR output from the CR oscillator 102 is input to the frequency divider circuit 107 as a reference signal for the second feedback circuit, and the frequency signal fR is 1 / k by the frequency divider circuit 107. Is dispensed with Thereafter, the divided signal is input to the phase comparator 109.

Here, the frequency division number k of the frequency divider circuit 107 is set to be variable so that the required channel space can be ensured in a system using the PLL circuit.

The phase of the input signal fOUT and the phase of the reference signal fR / k are compared by the phase comparator 109, and the phase difference between the input signal fOUT and the reference signal fR / k is output.

The phase difference output from the phase comparator 109 is converted into a voltage by the LPF 110 in accordance with the value of the phase difference, and the voltage is supplied to the VCO 106. The frequency of the frequency signal fOUT is controlled by the VCO 106 in accordance with the voltage supplied from the LPF 110.

Thereafter, the output frequency is changed by the VCO 106 to allow the system to stabilize. The output frequency of the VCO 106 for stabilizing the second PLL loop is represented by the following formula.

fOUT = m fR / k = m n fOSC / k

Here, n, k and m are frequency division numbers of the frequency divider circuits 103, 107 and 109, respectively.

(Example 2)

Fig. 8 is a block diagram showing Embodiment 2 of the PLL circuit of the present invention.

As shown in Fig. 8, the PLL circuit of the second embodiment is composed of first and second feedback circuits. In the first feedback circuit, the crystal oscillator 201 acts as a reference signal source for the first feedback circuit, and acts as an input signal source for the first feedback circuit as well as a reference signal source for the second feedback circuit. And a first frequency divider circuit 203 for dividing the frequency signal output from the CR oscillator 202 to output the divided frequency signal, and the frequency divider circuit 203. The second frequency divider circuit 204 for further dividing the frequency signal and the phase of the reference signal output from the crystal oscillator 201 are compared with the frequency of the input signal divided by the frequency divider circuits 203 and 204. Converting the signal output from the first phase comparator 205 and the phase comparator 205 into a voltage according to the phase difference between the reference signal and the input signal, It includes a first LPF 1 (206) for supplying a voltage to the CR oscillator (202). In the second feedback circuit, a VCO 207 serving as an input signal source for the second feedback circuit, a third frequency divider circuit 208 for dividing an input signal output from the VCO 207, and a frequency divider The phase of the reference signal divided by the circuit 203 is compared with the phase of the input signal output from the VCO 207 divided by the frequency divider circuit 207 to obtain a signal according to the phase difference between the reference signal and the input signal. And a second LPF 210 for converting the signal output from the phase comparator 209 into a voltage and supplying the voltage to the VCO 207.

The operation of the PLL circuit configured as described above is described below.

First, the frequency signal fOSC is output from the crystal oscillator 201 as a reference signal for the first feedback circuit, and at the same time, the frequency signal fR is output from the CR oscillator 202 as an input signal for the first feedback circuit.

The input signal fR output from the CR oscillator 202 is divided by 1 / n by the frequency divider circuit 203 and further divided by 1 / k by the frequency divider circuit 204. Thereafter, the divided input signal fR is input to the phase comparator 205. At the same time, the reference signal fOSC output from the crystal oscillator 201 is input to the phase comparator 205.

Thereafter, the phase of the input signal fR / (n · K) and the phase of the reference signal fOSC are compared by the phase comparator 205, and the phase difference between the two signals is output.

The phase difference output from the phase comparator 205 is converted into a voltage in accordance with the value of the phase difference by the LPF 206. The voltage is supplied to the CR oscillator 202. The frequency of the frequency signal fR is controlled by the CR oscillator 202 in accordance with the voltage supplied from the LPF 206.

At this time, the frequency signal fR output from the CR oscillator 202 when the first feedback circuit is stabilized is represented by the following formula.

fR = nk fOSC

Here, n and k are frequency division numbers of the frequency divider circuits 203 and 204, respectively.

On the other hand, when the frequency signal fOUT is output from the VCO 207 as an input signal to the second feedback circuit, the input signal fOUT output from the VCO 207 is divided by 1 / m by the frequency divider circuit 208. The divided input signal fOUT is input to the phase comparator 209.

Also, the frequency signal fR / n output by the CR oscillator 202 and divided by 1 / n by the frequency divider circuit 203 is input to the phase comparator 209 as a reference signal for the second feedback circuit.

Here, the frequency division number n of the frequency divider circuit 203 is set to be variable so that the required channel space can be guaranteed in the system using the PLL circuit.

Thereafter, the phase of the input signal fOUT / m and the phase of the reference signal fR / n are compared by the phase comparator 209, and the phase difference between the input signal fOUT and the reference signal fR / n is output from the phase comparator 209.

The phase difference output from the phase comparator 209 is converted into a voltage in accordance with the value of the phase difference by the LPF 210, and this voltage is supplied to the VCO 207. The frequency of the frequency signal fOUT is controlled by the VCO 207 in accordance with the voltage supplied from the LPF 210.

Therefore, the output frequency is changed by the VCO 207 so that the system is stable. The output frequency of the VCO 207 for stabilizing the second feedback circuit is represented by the following formula.

fOUT = m fR / n = m k fOSC

Here, n, k, and m are frequency divider numbers of the frequency divider circuits 203, 204, and 208, respectively.

In this embodiment, the output fOUT output from the second PLL loop is determined by the product of each of the frequency of the frequency divider circuits 203 and 208 and the oscillation frequency of the crystal oscillator 201. In addition, since the cycle of the signal output from the phase comparator 209 is determined by the output obtained by dividing the output of the CR oscillator 202 using the frequency divider circuit 203, the output frequency of the phase comparator 209 Can be changed without changing the output frequency of the PLL circuit.

While the preferred embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and substitutions are possible without departing from the spirit and scope of the invention as defined by the appended claims.

As described above, according to the PLL circuit of the present invention, in the first PLL loop, the input reference signal is multiplied and output as an output signal. In the first feedback circuit, the output signal is used as a reference signal for the second feedback circuit, and in the second feedback circuit, the output signal is output externally. Therefore, when the crystal oscillator acts as a reference signal source for the first feedback circuit, a frequency higher than the oscillation frequency in the crystal oscillator is used as the reference signal. Thereafter, stable frequency characteristics can be obtained even when the power supply voltage is reduced.

In addition, the oscillation frequency of the crystal oscillator can be reduced so that the current consumption is reduced.

Claims (17)

In a PLL circuit, A first feedback circuit, And a second feedback circuit for outputting the signal to the outside using a signal obtained by multiplying the reference signal in the first feedback circuit as a reference signal. The method of claim 1, wherein the first feedback circuit, A crystal oscillator serving as a reference signal source of the first feedback circuit, A CR oscillator serving as an input signal source of the first feedback circuit and serving as a reference signal source of the second feedback circuit; A first frequency divider circuit for dividing an input signal supplied from the CR oscillator and outputting a divided input signal; Comparing the phase of the reference signal output from the crystal oscillator with the phase of the divided input signal in the first frequency divider circuit and outputting a signal according to the phase difference between the phase of the reference signal and the phase of the divided input signal. A first phase comparator, and A first lowpass filter converting the signal output from the first phase comparator into a voltage and returning the voltage to the CR oscillator, The second feedback circuit includes a voltage controlled oscillator serving as an input signal source for the second feedback circuit; A second frequency divider circuit for dividing a reference signal supplied from the CR oscillator and outputting a divided reference signal; A third frequency divider circuit for dividing an input signal supplied from the voltage controlled oscillator and outputting a divided input signal; Compare the phase of the reference signal divided by the second frequency divider circuit with the phase of the input signal divided by the third frequency divider circuit, and according to the phase difference between the phase of the reference signal and the phase of the input signal. A second phase comparator for outputting a; And a second lowpass filter converting the signal supplied from said second phase comparator into a voltage and returning this voltage to said voltage controlled oscillator. 3. The PLL circuit of claim 2, wherein the frequency of the input signal from the CR oscillator is controlled in accordance with the signal converted to voltage in the first lowpass filter. 3. The PLL circuit of claim 2, wherein the frequency of the input signal from the CR oscillator is controlled in accordance with the signal converted to voltage in the second lowpass filter. 4. The PLL circuit of claim 3, wherein the frequency of the input signal from the CR oscillator is controlled in accordance with the signal converted into voltage in the second lowpass filter. 3. The PLL circuit according to claim 2, wherein the frequency division number of the second frequency divider circuit is set to be changeable. 4. The PLL circuit according to claim 3, wherein the frequency division number of the second frequency divider circuit is set to be changeable. The PLL circuit according to claim 4, wherein the frequency division number of the second frequency divider circuit is set to be changeable. 6. The PLL circuit according to claim 5, wherein the frequency division number of the second frequency divider circuit is set to be changeable. The method of claim 1, wherein the first feedback circuit, A crystal oscillator serving as a reference signal source for the first feedback circuit, A CR oscillator serving as an input signal source for the first feedback circuit and serving as a reference signal source for the second feedback circuit; A first frequency divider circuit for dividing an input signal supplied from the CR oscillator and outputting a divided input signal; A second frequency divider circuit for dividing an input signal from the first frequency divider circuit and outputting a divided input signal; Compare the phase of the reference signal supplied from the crystal oscillator with the phase of the divided input signal in the first and second frequency divider circuits and according to the phase difference between the phase of the reference signal and the phase of the divided input signal. A first phase comparator for outputting a; A first lowpass filter converting the signal output from the phase comparator into a voltage and returning the voltage to the CR oscillator, The second feedback circuit includes a voltage controlled oscillator serving as an input signal source of the second feedback circuit; A third frequency divider circuit for dividing an input signal output from the voltage controlled oscillator and outputting a divided input signal; Compare the phase of the divided reference signal in the first frequency divider circuit with the phase of the divided input signal in the third frequency divider circuit, and determine a signal according to the phase difference between the reference signal and the phases of the input signal. A second phase comparator for outputting, And a second lowpass filter converting the signal output from the second phase comparator into a voltage and returning the voltage to the voltage controlled oscillator. 11. The PLL circuit of claim 10, wherein the frequency of the input signal from the oscillator is controlled in accordance with the signal converted to voltage in the first lowpass filter. 11. The PLL circuit of claim 10, wherein the frequency of the input signal from the voltage controlled oscillator is controlled in accordance with the signal converted to voltage in the second low pass filter. 12. The PLL circuit of claim 11, wherein the frequency of the input signal from the voltage controlled oscillator is controlled in accordance with the signal converted to voltage in the second lowpass filter. 11. The PLL circuit according to claim 10, wherein the frequency division number of the second frequency divider circuit is set to be changeable. 12. The PLL circuit according to claim 11, wherein the frequency divider number of the second frequency divider circuit is set to be changeable. 13. The PLL circuit according to claim 12, wherein the frequency divider number of the second frequency divider circuit is set to be changeable. 14. The PLL circuit according to claim 13, wherein the frequency division number of the second frequency divider circuit is set to be changeable.