KR19980015706A - TFT substrate having a source / drain electrode made of an alloy - Google Patents
TFT substrate having a source / drain electrode made of an alloy Download PDFInfo
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- KR19980015706A KR19980015706A KR1019960035140A KR19960035140A KR19980015706A KR 19980015706 A KR19980015706 A KR 19980015706A KR 1019960035140 A KR1019960035140 A KR 1019960035140A KR 19960035140 A KR19960035140 A KR 19960035140A KR 19980015706 A KR19980015706 A KR 19980015706A
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- tft substrate
- drain electrode
- alloy
- electrode made
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- 239000000758 substrate Substances 0.000 title claims abstract description 38
- 239000000956 alloy Substances 0.000 title claims abstract description 25
- 229910045601 alloy Inorganic materials 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 10
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 9
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 8
- 229910052735 hafnium Inorganic materials 0.000 claims abstract description 7
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 7
- 229910052726 zirconium Inorganic materials 0.000 claims abstract description 7
- 229910052804 chromium Inorganic materials 0.000 claims abstract description 6
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 6
- 239000004973 liquid crystal related substance Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 abstract description 7
- 229910052763 palladium Inorganic materials 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 150000002739 metals Chemical class 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000010407 anodic oxide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000002351 wastewater Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
본 발명은 TFT기판에 관한 것으로, 더욱 상세하게는 소오스/드레인 전극으로서 2원소 또는 3원소 금속이 일정한 비율로 합금된 합금층을 이용하는 합금으로 이루어진 소오스/드레인 전극을 갖는 TFT 기판에 관한 것으로, 합금으로 이루어진 소오스/드레인 전극을 갖는 TFT 기판은 액정 표시 소자용 소오스/드레인 전극을 갖는 TFT 기판에 있어서, 상기 소오스/드레인 전극은 Cr, Mo, Ta, Ti, W, Ni, Zr, Hf, Co, Pt, Pd으로 이루어진 군으로부터 선택된 적어도 2원소 금속의 합금인 것을 특징으로 한다.The present invention relates to a TFT substrate, and more particularly to a TFT substrate having a source / drain electrode made of an alloy using an alloy layer in which a two-element or three-element metal is alloyed at a certain ratio as a source / drain electrode, Wherein the source / drain electrodes are formed of a material selected from the group consisting of Cr, Mo, Ta, Ti, W, Ni, Zr, Hf, Co, Pt, Pd, and the like.
Description
본 발명은 TFT기판에 관한 것으로, 더욱 상세하게는 소오스/드레인 전극으로 2원소 또는 3원소 금속이 일정한 비율로 합금된 합금층을 이용하는 합금으로 이루어진 소오스/드레인 전극을 갖는 TFT 기판에 관한 것이다.The present invention relates to a TFT substrate, and more particularly, to a TFT substrate having a source / drain electrode made of an alloy using an alloy layer in which a source / drain electrode is alloyed with a two-element or three-element metal at a certain ratio.
일반적으로, TFT 기판은 도 1에 도시된 바와 같이, DC스퍼터링 방법에 의해 유리 기판(1)상에 Al 박막을 증착하여 소정의 사진식각 공정을 실시하여 게이트(2)를 형성하고, 게이트(2)가 형성된 유리 기판(1) 위에 PECVD법으로 SiNx를 전면에 도포하여 게이트 절연막(3)을 형성하며, 그 위에 비정질 실리콘을 연속적으로 도포하여 반도체층(4)을 형성한다.1, an Al thin film is deposited on a glass substrate 1 by a DC sputtering method, a predetermined photolithography process is performed to form a gate 2, and a gate 2 Is formed on the glass substrate 1 by the PECVD method to form the gate insulating film 3, and the amorphous silicon is continuously applied thereon to form the semiconductor layer 4. Then, as shown in FIG.
다음에, 오믹층 형성시 반도체층이 손상되지 않도록 SiNx를 반도체층(4)상에 증착시키고 소정의 사진식각 공정을 실시하여 에칭 스토퍼막(6)을 형성하고, 반도체층(4)에 포토레지스트를 도포하고 패터닝한 후 건식 식각하여 채널층을 형성한다.Next, SiNx is deposited on the semiconductor layer 4 so as not to damage the semiconductor layer during the formation of the ohmic layer, a predetermined photolithography process is performed to form the etching stopper film 6, And patterned, followed by dry etching to form a channel layer.
계속하여 소오스와 드레인의 오믹접촉을 원할하게 하기 위해 PECVD법으로 오믹층(5)을 형성하고 스퍼터링 방법에 의해 도전 물질을 증착하여 소정의 식각으로 소오스 전극(7)과 드레인 전극(8)을 형성하고, 상기 샘플 전면에 SiNx를 증착하여 형성한 후 드레인 전극(8)이 노출되도록 일부 보호막(9)을 제거한다.Subsequently, an ohmic layer 5 is formed by a PECVD method to facilitate ohmic contact between the source and the drain, a conductive material is deposited by a sputtering method, and the source electrode 7 and the drain electrode 8 are formed by a predetermined etching SiNx is deposited on the entire surface of the sample, and then the protective film 9 is removed to expose the drain electrode 8.
이후, 상기 노출된 드레인 상부에 ITO(10)를 도포한 후 필요한 부분만을 남기고 ITO(Indum Tin Oxide)를 제거하여 최종적으로 TFT 기판이 제작된다.Thereafter, ITO (10) is coated on the exposed drain, and indium tin oxide (ITO) is removed leaving only a necessary portion, finally, a TFT substrate is manufactured.
여기서, 상기와 같이 제작된 TFT 기판은 ES(Etch-Stopper)타입이라고 하며, 도 1(B)에 도시된 바와 같은 TFT 기판은 BCE(Back-Channel-Etched)타입이라고 하는 바, 이 기판의 제조 방법은 도 1(A)의 ES(Etch-Stopper)타입의 제조 방법과 별차이점이 없어 상세한 설명은 생략하기로 한다.Here, the TFT substrate manufactured as described above is referred to as an ES (Etch-Stopper) type, and the TFT substrate as shown in FIG. 1B is referred to as a Back-Channel-Etched (BCE) type. The method is not different from the ES (Etch-Stopper) type manufacturing method of FIG. 1 (A), and a detailed description thereof will be omitted.
미설명 부호 2'는 게이트 절연막을 성장시키는데 사용되는 양극 산화막이다.Reference numeral 2 'is an anodic oxide film used for growing a gate insulating film.
또한, 상기의 스퍼터링을 진행할 때, 증착되는 물질로 타겟(Target)이 사용되는 바, 이 타겟은 대기 용해(Atmospheric Melting), 진공 용해(Vacuum Melting), HIP(Hot Isostatic Pressure), Sintering 등의 방법으로 제작된다.When the sputtering is performed, a target is used as a material to be deposited. The target may be formed by a method such as atmospheric melting, vacuum melting, HIP (hot isostatic pressure), sintering .
상기와 같이 제작된 TFT 기판과, 공통 전극 및 화소 등이 형성된 상부 기판을 절연성 에폭시 수지 등의 봉합제로 봉합한 후 TFT 기판과 상부 기판 사이의 공간을 액정으로 채운다. 그 다음 상기 봉합된 TFT 및 상부 기판을 소정 온도에서 열처리하여 상기 박막트랜지스터의 반도체층과 칼라 필터 등을 안정화시키고, 상기 봉합제를 경화하여 액정 표시 장치를 제작한다.The TFT substrate manufactured as described above and the upper substrate on which the common electrodes and pixels are formed are sealed with a sealant such as an insulating epoxy resin, and then the space between the TFT substrate and the upper substrate is filled with liquid crystal. Then, the sealed TFT and the upper substrate are heat-treated at a predetermined temperature to stabilize the semiconductor layer, the color filter, and the like of the thin film transistor, and the sealant is cured to manufacture a liquid crystal display device.
여기서, 상기 액정은 그 배열 방식에 따라 TN(Twisted Nematic) 액정 구동 방식 또는 IPS 액정 구동 방식이 사용될 수 있다.Here, the liquid crystal may be a twisted nematic (TN) liquid crystal driving method or an IPS liquid crystal driving method depending on the arrangement method thereof.
상기와 같이 제작된 TFT 기판의 소오스/드레인 전극으로 사용되는 금속은 비정질의 실리콘으로 형성된 반도체층(4)과 오믹층(5)과의 양호한 저항 콘택을 형성하고, 저저항이고, 내화학성이 우수하여야 하는 바, 이 중에서 가장 중요하게 대두되고 있는 점은 비정질의 실리콘으로 형성된 반도체층(4)과 오믹층(5)과의 양호한 저항 콘택(contact)을 형성해야 하는 것이다.The metal used as the source / drain electrode of the TFT substrate fabricated as described above forms a good resistance contact between the semiconductor layer 4 formed of amorphous silicon and the ohmic layer 5, and has a low resistance and excellent chemical resistance The most important point is that a good ohmic contact between the semiconductor layer 4 formed of amorphous silicon and the ohmic layer 5 should be formed.
상기의 도 1(a),(b)에 도시된 TFT 기판의 소오스/드레인 전극은 Cr/Al, Mo/Al, Ta/Al/Mo, Ti/ITO, Cr/ITO, Mo/ITO 등과 같이 층을 갖는 구조가 사용되기도 한다.The source / drain electrodes of the TFT substrate shown in FIGS. 1 (a) and 1 (b) may be formed of a material such as Cr / Al, Mo / Al, Ta / Al / Mo, Ti / ITO, Cr / ITO, Mo / May be used.
그러나, 상기에 기술된 소오스/드레인 전극으로 사용되는 금속 중에 Cr은 비정질의 실리콘으로 형성된 반도체층(4)과 오믹층(5)과의 양호한 저항 콘택이 형성되고, 저저항이며, 내화학성이 우수하지만, Cr 에칭후 발생되는 폐수로 인해 환경 공해 물질이란 측면에서 대단히 취약하다.However, in the metal used as the source / drain electrode described above, Cr has a good resistance contact between the semiconductor layer 4 formed of amorphous silicon and the ohmic layer 5, has a low resistance, has excellent chemical resistance However, the wastewater generated after Cr etching is very weak in terms of environmental pollutants.
또한, Mo는 저항이 13.5μΩㆍ㎝로서 저항이 작지만 내화학성이 약하며, Ta과 Ti는 저항이 높아서 20 inch 이상의 대화면에 사용하려면 소오스/드레인 전극을 Ta/Al, Ti/Al 등의 구조를 이용해야 하므로 제조 공정 단순화가 어려운 난점이 있으며, W는 재질 자체가 응력에 약하기 때문에 드레인 전극을 형성하는 경우에 단락이 되는 문제점이 있다. 또한, Ni은 강자성체로서 RF(Radio Frequency) 스퍼터링을 해야하기 때문에 장비 제약이 있다.In addition, Mo has a resistance of 13.5 μΩ · cm, resistance is low, but its chemical resistance is weak. Ta and Ti have high resistance. To use for a large screen of 20 inches or more, the source / drain electrode is made of Ta / Al or Ti / Al There is a problem in that the manufacturing process is difficult to be simplified, and W has a problem that the material itself is short in stress when forming the drain electrode. In addition, Ni is a ferromagnetic material and RF (Radio Frequency) sputtering is required.
따라서, 본 발명은 이와 같은 종래의 소오스/드레인 전극으로 사용되는 물질들의 단점을 배제하고 장점을 이용하여 두 가지 물질 또는 세 가지 물질을 상호 일정 비율로 혼합하여 합금으로 이루어진 소오스/드레인 전극을 갖는 TFT 기판을 제공하는데 그 목적이 있다.Therefore, the present invention excludes the disadvantages of the conventional materials used as the source / drain electrodes and, by using the advantages, the two materials or three materials are mixed at a certain ratio to form TFTs having source / And to provide a substrate.
도 1(a),(b)는 일반적인 TFT 기판의 수직 구조를 도시한 단면도.1 (a) and 1 (b) are sectional views showing a vertical structure of a general TFT substrate.
*도면의 주요부분에 대한 부호의 설명*Description of the Related Art [0002]
1 : 유리 기판2 : 게이트3 : 게이트 절연막1: glass substrate 2: gate 3: gate insulating film
4 : 반도체층5 : 오믹 층6 : 스토퍼막4: semiconductor layer 5: ohmic layer 6: stopper film
7 : 소오스 전극8 : 드레인 전극9 : 보호막7: source electrode 8: drain electrode 9:
10 : ITO10: ITO
이와 같은 본 발명의 목적을 달성하기 위한 합금으로 이루어진 소오스/드레인 전극을 갖는 TFT 기판은 액정 표시 소자용 소오스/드레인 전극을 갖는 TFT 기판에 있어서 상기 소오스/드레인 전극은 Cr, Mo, Ta, Ti, W, Ni, Zr, Hf, Co, Pt, Pd으로 이루어진 군으로부터 선택된 적어도 2원소 금속의 합금인 것을 특징으로 한다.In order to achieve the object of the present invention, there is provided a TFT substrate having a source / drain electrode made of an alloy and having a source / drain electrode for a liquid crystal display device, wherein the source / W, Ni, Zr, Hf, Co, Pt, and Pd.
이하, 본 발명에 따른 소오스/드레인 전극에 대해 상세히 설명하면 다음과 같다.Hereinafter, the source / drain electrode according to the present invention will be described in detail.
본 발명에 의한 소오스/드레인 전극을 Cr/Al, Mo/Al, Ta/Al/Mo, Ti/ITO, Cr/ITO, Mo/ITO 등의 층으로 이루어진 단일 원소 금속을 사용하지 않고, Cr, Mo, Ta, Ti, W, Ni, Zr, Hf, Co, Pt, Pd 등의 단일 원소금속 중에 두 가지 또는 세 가지의 금속을 일정 비율로 혼합하여 만들어진 합금으로 제조된 것을 제외하고는 종래의 도 1(A),(B)에 도시된 TFT 기판과 동일하여 상세한 설명은 생략하기로 하고 소오스/드레인 전극으로 사용되는 합금의 구체적인 조성을 설명하기로 한다.The source / drain electrodes according to the present invention can be formed of Cr, Mo, Al, Mo, Ti / ITO, Cr / ITO and Mo / ITO without using a single element metal such as Cr / 1, except that a single element metal such as Ta, Ti, W, Ni, Zr, Hf, Co, Pt, Pd or the like is made of an alloy made by mixing two or three metals in a certain ratio. (A) and (B), and a detailed description thereof will be omitted. A specific composition of an alloy used as a source / drain electrode will be described.
첫째, Cr, Mo, Ta, Ti, W, Ni, Zr, Hf, Co, Pt, Pd의 금속들의 2원소 금속으로서 각 원소의 at%를 각각 a,b라고 하면, 각 원소가 차지하는 비율이 각각 a ≥ 1% 및 b ≥1%가 되도록 조성하여 a+b=100%가 되도록 한다.First, if the at% of each element is a and b as the two element metals of the metals of Cr, Mo, Ta, Ti, W, Ni, Zr, Hf, Co, Pt and Pd, a > 1% and b > 1% so that a + b = 100%.
둘째, Cr, Mo, Ta, Ti, W, Ni, Zr, Hf, Co, Pt, Pd의 금속들의 3원소 금속으로서 각원소의 at%를 각각 a,b,c라고 하면, 각 원소가 차지하는 비율이 각각 a ≥ 1%, b ≥1% 및 c ≥1%가 되도록 조성하여 a+b+c=100%가 되도록 한다.Second, if at% of each element is a, b and c as the three elemental metals of the metals of Cr, Mo, Ta, Ti, W, Ni, Zr, Hf, Co, Pt and Pd, Are formed such that a ≥ 1%, b ≥ 1% and c ≥ 1%, respectively, so that a + b + c = 100%.
이와 같이 상기의 합금 비율로 제조된 소오스/드레인 전극은 비정질의 실리콘으로 형성된 반도체 층과 오믹층과의 양호한 저항 콘택을 형성하고, 저저항이며, 내화학성이 우수해진다. 특히, 비정질의 실리콘으로 형성된 반도체 층과 오믹층과의 저항 콘택이 좋아진다.As described above, the source / drain electrode made of the above alloy ratio forms a good ohmic contact between the amorphous silicon semiconductor layer and the ohmic layer, and has low resistance and excellent chemical resistance. In particular, resistance contact between the amorphous silicon semiconductor layer and the ohmic layer is improved.
본 발명에 따른 소오스/드레인 전극은 상기에 기술된 방법으로 제조된 합금을 단일층으로 하여 제작할 수도 있고, 저저항을 위해 합금/Al으로 이루어진 층으로 제작할 수도 있으며, 공정 단순화를 위해 합금/ITO으로 이루어진 층으로도 제작할 수 있다.The source / drain electrodes according to the present invention may be fabricated using a single layer of the alloy prepared by the above-described method, or may be made of a layer made of alloy / Al for low resistance. In order to simplify the process, And the like.
이상 살펴본 바와 같이, 본 발명에 의한 합금으로 이루어진 소오스/드레인 전극을 갖는 TFT 기판에 의하면, 비정질의 실리콘으로 형성된 반도체층과 오믹층과의 양호한 저항 콘택을 형성하고, 저저항이며, 내화학성이 우수해지며, 특히, 비정질의 실리콘으로 형성된 반도체층과 오믹층과의 저항 콘택이 좋아진다. 또한, 소오스/드레인 전극을 합금/Al의 층으로 형성함으로써, 저항이 작게할 수 있으며, 합금/ITO의 층으로 형성함으로써, 공정 단순화를 이룰 수 있는 효과가 있다.As described above, according to the TFT substrate having a source / drain electrode made of an alloy according to the present invention, a good resistance contact between a semiconductor layer formed of amorphous silicon and an ohmic layer is formed, and a low resistance and excellent chemical resistance In particular, resistance contact between the ohmic layer and the semiconductor layer formed of amorphous silicon is improved. In addition, by forming the source / drain electrode as a layer of alloy / Al, the resistance can be made small and it is possible to simplify the process by forming the layer of alloy / ITO.
Claims (9)
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| KR1019960035140A KR100246856B1 (en) | 1996-08-23 | 1996-08-23 | Thin film transistor for a liquid crystal display device having a source/drain electrode consist of alloy |
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| KR1019960035140A KR100246856B1 (en) | 1996-08-23 | 1996-08-23 | Thin film transistor for a liquid crystal display device having a source/drain electrode consist of alloy |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100878275B1 (en) * | 2002-09-03 | 2009-01-13 | 삼성전자주식회사 | A thin film transistor substrate using wring having low resistance and liquid crystal displays comprising the same |
| US7723981B2 (en) * | 2006-08-22 | 2010-05-25 | Techwing Co., Ltd. | Method for transferring test trays in a side-docking type test handler |
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| JPS58212178A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Thin film field effect transistor and manufacture thereof |
| JP2661112B2 (en) * | 1988-03-08 | 1997-10-08 | 富士通株式会社 | Thin film transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100878275B1 (en) * | 2002-09-03 | 2009-01-13 | 삼성전자주식회사 | A thin film transistor substrate using wring having low resistance and liquid crystal displays comprising the same |
| US7723981B2 (en) * | 2006-08-22 | 2010-05-25 | Techwing Co., Ltd. | Method for transferring test trays in a side-docking type test handler |
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