KR102931352B1 - 반도체 장치 - Google Patents
반도체 장치Info
- Publication number
- KR102931352B1 KR102931352B1 KR1020217038306A KR20217038306A KR102931352B1 KR 102931352 B1 KR102931352 B1 KR 102931352B1 KR 1020217038306 A KR1020217038306 A KR 1020217038306A KR 20217038306 A KR20217038306 A KR 20217038306A KR 102931352 B1 KR102931352 B1 KR 102931352B1
- Authority
- KR
- South Korea
- Prior art keywords
- transistor
- bit line
- oxide
- control circuit
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/312—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
- H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2019096945 | 2019-05-23 | ||
| JP2019096937 | 2019-05-23 | ||
| JPJP-P-2019-096937 | 2019-05-23 | ||
| JPJP-P-2019-096945 | 2019-05-23 | ||
| JP2019096943 | 2019-05-23 | ||
| JPJP-P-2019-096943 | 2019-05-23 | ||
| PCT/IB2020/054454 WO2020234689A1 (ja) | 2019-05-23 | 2020-05-12 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20220008837A KR20220008837A (ko) | 2022-01-21 |
| KR102931352B1 true KR102931352B1 (ko) | 2026-02-27 |
Family
ID=73458402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020217038306A Active KR102931352B1 (ko) | 2019-05-23 | 2020-05-12 | 반도체 장치 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11869627B2 (https=) |
| JP (2) | JP7459079B2 (https=) |
| KR (1) | KR102931352B1 (https=) |
| CN (1) | CN113748463A (https=) |
| WO (1) | WO2020234689A1 (https=) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI910401B (zh) * | 2022-01-27 | 2026-01-01 | 新加坡商發明與合作實驗室有限公司 | 伺服處理器和機架伺服器單元的機體電路微縮和拉伸平台 |
| JPWO2023148574A1 (https=) * | 2022-02-04 | 2023-08-10 | ||
| WO2023152595A1 (ja) * | 2022-02-10 | 2023-08-17 | 株式会社半導体エネルギー研究所 | 記憶装置 |
| KR20240149947A (ko) * | 2022-02-18 | 2024-10-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
| WO2023223127A1 (ja) * | 2022-05-16 | 2023-11-23 | 株式会社半導体エネルギー研究所 | 半導体装置、記憶装置及び電子機器 |
| US11984165B2 (en) * | 2022-05-24 | 2024-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device with reduced area |
| US12513888B2 (en) * | 2022-07-22 | 2025-12-30 | Fujian Jinhua Integrated Circuit Co., Ltd. | Memory device and manufacturing method thereof |
| KR20260019447A (ko) * | 2023-06-09 | 2026-02-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120033489A1 (en) | 2010-08-03 | 2012-02-09 | Samsung Electronics Co., Ltd. | Memory device, precharge controlling method thereof, and devices having the same |
| US20120147686A1 (en) | 2010-12-09 | 2012-06-14 | Elpida Memory, Inc. | Semiconductor device having hierarchical bit line structure and control method thereof |
| US20130070506A1 (en) | 2011-09-15 | 2013-03-21 | Elpida Memory Inc. | Semiconductor device having stacked layers |
| WO2019025912A1 (en) | 2017-08-04 | 2019-02-07 | Semiconductor Energy Laboratory Co., Ltd. | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
| WO2019048967A1 (ja) | 2017-09-06 | 2019-03-14 | 株式会社半導体エネルギー研究所 | 半導体装置、記憶装置、及び電子機器 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000090682A (ja) | 1998-09-10 | 2000-03-31 | Toshiba Corp | 半導体記憶装置 |
| DE10009346B4 (de) * | 2000-02-28 | 2011-06-16 | Qimonda Ag | Integrierte Schreib-/Leseschaltung zur Auswertung von zumindest einer Bitline in einem DRAM Speicher |
| JP2002008386A (ja) * | 2000-06-22 | 2002-01-11 | Toshiba Corp | 半導体集積回路装置 |
| JP2012256821A (ja) | 2010-09-13 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 記憶装置 |
| TWI691960B (zh) | 2010-10-05 | 2020-04-21 | 日商半導體能源研究所股份有限公司 | 半導體記憶體裝置及其驅動方法 |
| US11205461B2 (en) * | 2017-06-27 | 2021-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Memory device comprising first through fourth transistors |
-
2020
- 2020-05-12 WO PCT/IB2020/054454 patent/WO2020234689A1/ja not_active Ceased
- 2020-05-12 JP JP2021520484A patent/JP7459079B2/ja active Active
- 2020-05-12 KR KR1020217038306A patent/KR102931352B1/ko active Active
- 2020-05-12 CN CN202080032247.5A patent/CN113748463A/zh active Pending
- 2020-05-12 US US17/606,116 patent/US11869627B2/en active Active
-
2024
- 2024-03-19 JP JP2024043913A patent/JP7639207B2/ja active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120033489A1 (en) | 2010-08-03 | 2012-02-09 | Samsung Electronics Co., Ltd. | Memory device, precharge controlling method thereof, and devices having the same |
| US20120147686A1 (en) | 2010-12-09 | 2012-06-14 | Elpida Memory, Inc. | Semiconductor device having hierarchical bit line structure and control method thereof |
| US20130070506A1 (en) | 2011-09-15 | 2013-03-21 | Elpida Memory Inc. | Semiconductor device having stacked layers |
| WO2019025912A1 (en) | 2017-08-04 | 2019-02-07 | Semiconductor Energy Laboratory Co., Ltd. | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
| WO2019048967A1 (ja) | 2017-09-06 | 2019-03-14 | 株式会社半導体エネルギー研究所 | 半導体装置、記憶装置、及び電子機器 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2024079742A (ja) | 2024-06-11 |
| US11869627B2 (en) | 2024-01-09 |
| KR20220008837A (ko) | 2022-01-21 |
| JP7459079B2 (ja) | 2024-04-01 |
| CN113748463A (zh) | 2021-12-03 |
| JP7639207B2 (ja) | 2025-03-04 |
| US20220246185A1 (en) | 2022-08-04 |
| WO2020234689A1 (ja) | 2020-11-26 |
| JPWO2020234689A1 (https=) | 2020-11-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102919551B1 (ko) | 반도체 장치 및 상기 반도체 장치를 가지는 전자 기기 | |
| KR102929911B1 (ko) | 반도체 장치 | |
| KR102931352B1 (ko) | 반도체 장치 | |
| JP7702530B2 (ja) | 半導体装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
|
| D18-X000 | Deferred examination requested |
St.27 status event code: A-1-2-D10-D18-exm-X000 |
|
| D19-X000 | Deferred examination accepted |
St.27 status event code: A-1-2-D10-D19-exm-X000 |
|
| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
|
| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |
|
| D20-X000 | Deferred examination resumed |
St.27 status event code: A-1-2-D10-D20-exm-X000 |
|
| D22 | Grant of ip right intended |
Free format text: ST27 STATUS EVENT CODE: A-1-2-D10-D22-EXM-PE0701 (AS PROVIDED BY THE NATIONAL OFFICE) |
|
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| F11 | Ip right granted following substantive examination |
Free format text: ST27 STATUS EVENT CODE: A-2-4-F10-F11-EXM-PR0701 (AS PROVIDED BY THE NATIONAL OFFICE) |
|
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U12-oth-PR1002 Fee payment year number: 1 |
|
| U12 | Designation fee paid |
Free format text: ST27 STATUS EVENT CODE: A-2-2-U10-U12-OTH-PR1002 (AS PROVIDED BY THE NATIONAL OFFICE) Year of fee payment: 1 |
|
| PG1601 | Publication of registration |
St.27 status event code: A-4-4-Q10-Q13-nap-PG1601 |
|
| Q13 | Ip right document published |
Free format text: ST27 STATUS EVENT CODE: A-4-4-Q10-Q13-NAP-PG1601 (AS PROVIDED BY THE NATIONAL OFFICE) |