KR102876341B1 - 셀의 활성 영역 위의 게이트 접점 - Google Patents

셀의 활성 영역 위의 게이트 접점

Info

Publication number
KR102876341B1
KR102876341B1 KR1020247006821A KR20247006821A KR102876341B1 KR 102876341 B1 KR102876341 B1 KR 102876341B1 KR 1020247006821 A KR1020247006821 A KR 1020247006821A KR 20247006821 A KR20247006821 A KR 20247006821A KR 102876341 B1 KR102876341 B1 KR 102876341B1
Authority
KR
South Korea
Prior art keywords
gate
metal
gem
contact
paragraph
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020247006821A
Other languages
English (en)
Korean (ko)
Other versions
KR20240033144A (ko
Inventor
리차드 티. 슐츠
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20240033144A publication Critical patent/KR20240033144A/ko
Application granted granted Critical
Publication of KR102876341B1 publication Critical patent/KR102876341B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H01L21/76895—
    • H01L23/535—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020247006821A 2018-05-25 2019-03-27 셀의 활성 영역 위의 게이트 접점 Active KR102876341B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15/989,604 US10818762B2 (en) 2018-05-25 2018-05-25 Gate contact over active region in cell
US15/989,604 2018-05-25
KR1020207033968A KR20210002649A (ko) 2018-05-25 2019-03-27 셀의 활성 영역 위의 게이트 접점
PCT/US2019/024364 WO2019226229A1 (en) 2018-05-25 2019-03-27 Gate contact over active region in cell

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1020207033968A Division KR20210002649A (ko) 2018-05-25 2019-03-27 셀의 활성 영역 위의 게이트 접점

Publications (2)

Publication Number Publication Date
KR20240033144A KR20240033144A (ko) 2024-03-12
KR102876341B1 true KR102876341B1 (ko) 2025-10-27

Family

ID=66102798

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020247006821A Active KR102876341B1 (ko) 2018-05-25 2019-03-27 셀의 활성 영역 위의 게이트 접점
KR1020207033968A Ceased KR20210002649A (ko) 2018-05-25 2019-03-27 셀의 활성 영역 위의 게이트 접점

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020207033968A Ceased KR20210002649A (ko) 2018-05-25 2019-03-27 셀의 활성 영역 위의 게이트 접점

Country Status (6)

Country Link
US (2) US10818762B2 (enExample)
EP (1) EP3803962A1 (enExample)
JP (1) JP7572948B2 (enExample)
KR (2) KR102876341B1 (enExample)
CN (1) CN112166498B (enExample)
WO (1) WO2019226229A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11152347B2 (en) * 2018-04-13 2021-10-19 Qualcomm Incorporated Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections
US10818762B2 (en) * 2018-05-25 2020-10-27 Advanced Micro Devices, Inc. Gate contact over active region in cell
US10846327B2 (en) * 2018-11-02 2020-11-24 A9.Com, Inc. Visual attribute determination for content selection
EP3723127B1 (en) * 2019-04-10 2026-06-17 IMEC vzw A standard cell device and a method for forming an interconnect structure for a standard cell device
US10796061B1 (en) * 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
DE102020125647B4 (de) * 2020-01-31 2026-06-03 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit Komplementärfeldeffekttransistor des Typs mit vergrabenen Logikleitern, Layout-Diagramm-Herstellungsverfahren und System dafür
US11362090B2 (en) 2020-01-31 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same
US12205897B2 (en) 2021-09-23 2025-01-21 Advanced Micro Devices, Inc. Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells
US20250087285A1 (en) * 2023-09-12 2025-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160329241A1 (en) 2015-05-07 2016-11-10 United Microelectronics Corp. Integrated circuit structure and method for forming the same
WO2018042986A1 (ja) 2016-08-29 2018-03-08 株式会社ソシオネクスト 半導体集積回路装置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889329A (en) 1994-11-02 1999-03-30 Lsi Logic Corporation Tri-directional interconnect architecture for SRAM
DE102004063926B4 (de) 2004-03-24 2017-10-19 Infineon Technologies Ag Konfigurierbare Treiberzelle eines logischen Zellenfeldes
US7761831B2 (en) 2005-12-29 2010-07-20 Mosaid Technologies Incorporated ASIC design using clock and power grid standard cell
JP4322888B2 (ja) 2006-06-01 2009-09-02 エルピーダメモリ株式会社 半導体装置
US7984395B2 (en) 2008-01-17 2011-07-19 Synopsys, Inc. Hierarchical compression for metal one logic layer
JP5410082B2 (ja) 2008-12-12 2014-02-05 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US8533641B2 (en) 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions
US8716124B2 (en) * 2011-11-14 2014-05-06 Advanced Micro Devices Trench silicide and gate open with local interconnect with replacement gate process
KR20130070252A (ko) 2011-12-19 2013-06-27 에스케이하이닉스 주식회사 반도체 메모리 소자의 스페어 로직 구현방법 및 그 구조
WO2013106799A1 (en) 2012-01-13 2013-07-18 Tela Innovations, Inc. Circuits with linear finfet structures
US8743580B2 (en) * 2012-03-30 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for high speed ROM cells
US9461143B2 (en) * 2012-09-19 2016-10-04 Intel Corporation Gate contact structure over active gate and method to fabricate same
US10283437B2 (en) 2012-11-27 2019-05-07 Advanced Micro Devices, Inc. Metal density distribution for double pattern lithography
US9331013B2 (en) 2013-03-14 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated capacitor
WO2015083281A1 (ja) 2013-12-06 2015-06-11 ルネサスエレクトロニクス株式会社 半導体装置
KR102369511B1 (ko) 2015-07-08 2022-03-03 삼성전자주식회사 반도체 집적 회로 및 이를 포함하는 전자 시스템
US10672708B2 (en) 2015-11-30 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Standard-cell layout structure with horn power and smart metal cut
US9881872B2 (en) 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating a local interconnect in a semiconductor device
US11189569B2 (en) 2016-09-23 2021-11-30 Advanced Micro Devices, Inc. Power grid layout designs for integrated circuits
US9837398B1 (en) 2016-11-23 2017-12-05 Advanced Micro Devices, Inc. Metal track cutting in standard cell layouts
US10270430B2 (en) 2016-12-28 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same
US10503859B2 (en) 2017-08-30 2019-12-10 Arm Limited Integrated circuit design and/or fabrication
US11120190B2 (en) 2017-11-21 2021-09-14 Advanced Micro Devices, Inc. Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
US10818762B2 (en) * 2018-05-25 2020-10-27 Advanced Micro Devices, Inc. Gate contact over active region in cell

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160329241A1 (en) 2015-05-07 2016-11-10 United Microelectronics Corp. Integrated circuit structure and method for forming the same
WO2018042986A1 (ja) 2016-08-29 2018-03-08 株式会社ソシオネクスト 半導体集積回路装置

Also Published As

Publication number Publication date
JP7572948B2 (ja) 2024-10-24
CN112166498B (zh) 2025-08-08
KR20210002649A (ko) 2021-01-08
WO2019226229A1 (en) 2019-11-28
KR20240033144A (ko) 2024-03-12
US11424336B2 (en) 2022-08-23
US10818762B2 (en) 2020-10-27
JP2021525974A (ja) 2021-09-27
US20210028288A1 (en) 2021-01-28
US20190363167A1 (en) 2019-11-28
EP3803962A1 (en) 2021-04-14
CN112166498A (zh) 2021-01-01

Similar Documents

Publication Publication Date Title
JP7572948B2 (ja) セル内のアクティブ領域でのゲート接点
KR102912573B1 (ko) 5nm 이상을 위한 표준 셀 레이아웃 아키텍처 및 드로잉 스타일
US10651164B2 (en) Metal zero contact via redundancy on output nodes and inset power rail architecture
JP7343395B2 (ja) 垂直ゲートオールアラウンドライブラリアーキテクチャ
US11387255B2 (en) Semiconductor device
JP2019531602A (ja) 集積回路用の電力グリッドレイアウト設計
KR20200087190A (ko) 셀 영역을 감소시키고 셀 배치를 칩 레벨로 개선하는 금속0 전원 및 접지 포스트 라우팅
US12308370B2 (en) Cross field effect transistors (XFETs) in integrated circuits
CN121176170A (zh) 使用三维交叉场效应自对准晶体管的标准单元之间的零扩散中断
US20240304241A1 (en) Memory bit cells with three-dimensional cross field effect transistors
CN120167140A (zh) 具有正面功率连接和背面功率连接的三维交叉场效应自对准晶体管

Legal Events

Date Code Title Description
A107 Divisional application of patent
PA0104 Divisional application for international application

St.27 status event code: A-0-1-A10-A18-div-PA0104

St.27 status event code: A-0-1-A10-A16-div-PA0104

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

D22 Grant of ip right intended

Free format text: ST27 STATUS EVENT CODE: A-1-2-D10-D22-EXM-PE0701 (AS PROVIDED BY THE NATIONAL OFFICE)

PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

F11 Ip right granted following substantive examination

Free format text: ST27 STATUS EVENT CODE: A-2-4-F10-F11-EXM-PR0701 (AS PROVIDED BY THE NATIONAL OFFICE)

PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

U12 Designation fee paid

Free format text: ST27 STATUS EVENT CODE: A-2-2-U10-U12-OTH-PR1002 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

Q13 Ip right document published

Free format text: ST27 STATUS EVENT CODE: A-4-4-Q10-Q13-NAP-PG1601 (AS PROVIDED BY THE NATIONAL OFFICE)

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000