KR102694691B1 - 이중 금속 전력 레일을 갖는 집적 회로 제조 방법 - Google Patents

이중 금속 전력 레일을 갖는 집적 회로 제조 방법 Download PDF

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KR102694691B1
KR102694691B1 KR1020180065496A KR20180065496A KR102694691B1 KR 102694691 B1 KR102694691 B1 KR 102694691B1 KR 1020180065496 A KR1020180065496 A KR 1020180065496A KR 20180065496 A KR20180065496 A KR 20180065496A KR 102694691 B1 KR102694691 B1 KR 102694691B1
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metal
recessed features
isolated
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recessed
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KR20180133341A (ko
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수 두 채
카오루 마에카와
제프리 스미스
니콜라스 조이
게리트 제이 뢰싱크
카이훙 유
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도쿄엘렉트론가부시키가이샤
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    • H01L21/76877—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H01L21/02282—
    • H01L21/32056—
    • H01L21/76813—
    • H01L21/7685—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/036—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being within a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/438—Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H01L2924/01029—
    • H01L2924/01044—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020180065496A 2017-06-06 2018-06-07 이중 금속 전력 레일을 갖는 집적 회로 제조 방법 Active KR102694691B1 (ko)

Applications Claiming Priority (2)

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US201762515968P 2017-06-06 2017-06-06
US62/515,968 2017-06-06

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KR20180133341A KR20180133341A (ko) 2018-12-14
KR102694691B1 true KR102694691B1 (ko) 2024-08-12

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US (1) US10580691B2 (https=)
JP (2) JP2018207110A (https=)
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879115B2 (en) * 2017-11-21 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and forming method thereof
US11121075B2 (en) * 2018-03-23 2021-09-14 Qualcomm Incorporated Hybrid metallization interconnects for power distribution and signaling
US11101175B2 (en) * 2018-11-21 2021-08-24 International Business Machines Corporation Tall trenches for via chamferless and self forming barrier
US11024537B2 (en) * 2019-08-09 2021-06-01 Applied Materials, Inc. Methods and apparatus for hybrid feature metallization
KR102833584B1 (ko) * 2019-09-03 2025-07-15 삼성전자주식회사 반도체 소자
US11450562B2 (en) * 2019-09-16 2022-09-20 Tokyo Electron Limited Method of bottom-up metallization in a recessed feature
US11908738B2 (en) 2021-10-18 2024-02-20 International Business Machines Corporation Interconnect including integrally formed capacitor

Citations (7)

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KR100245970B1 (ko) 1995-09-07 2000-03-02 포만 제프리 엘 반도체구조와 이를 제조하기위한 개선된방법
JP2002353161A (ja) * 2001-05-25 2002-12-06 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
US20080122109A1 (en) 2006-07-19 2008-05-29 International Business Machines Corporation Porous and dense hybrid interconnect structure and method of manufacture
US20130043556A1 (en) * 2011-08-17 2013-02-21 International Business Machines Corporation Size-filtered multimetal structures
JP2014187208A (ja) * 2013-03-22 2014-10-02 Toshiba Corp 半導体装置及びその製造方法
US20170133317A1 (en) * 2015-11-05 2017-05-11 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US20170200642A1 (en) 2016-01-08 2017-07-13 Applied Materials, Inc. Co or ni and cu integration for small and large features in integrated circuits

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KR20010017237A (ko) * 1999-08-09 2001-03-05 박종섭 Ｍｍｌ반도체소자의 아날로그 커패시터형성방법
KR100447977B1 (ko) * 2002-03-13 2004-09-10 주식회사 하이닉스반도체 듀얼 다마신 공정을 이용한 반도체 소자의 금속 배선 형성방법
JP2004063995A (ja) * 2002-07-31 2004-02-26 Matsushita Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
US8093716B2 (en) * 2005-07-29 2012-01-10 Texas Instruments Incorporated Contact fuse which does not touch a metal layer
JP2007081113A (ja) * 2005-09-14 2007-03-29 Sony Corp 半導体装置の製造方法
KR20080029251A (ko) * 2006-09-28 2008-04-03 주식회사 하이닉스반도체 플래시 메모리 소자 제조방법
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Patent Citations (7)

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Publication number Priority date Publication date Assignee Title
KR100245970B1 (ko) 1995-09-07 2000-03-02 포만 제프리 엘 반도체구조와 이를 제조하기위한 개선된방법
JP2002353161A (ja) * 2001-05-25 2002-12-06 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
US20080122109A1 (en) 2006-07-19 2008-05-29 International Business Machines Corporation Porous and dense hybrid interconnect structure and method of manufacture
US20130043556A1 (en) * 2011-08-17 2013-02-21 International Business Machines Corporation Size-filtered multimetal structures
JP2014187208A (ja) * 2013-03-22 2014-10-02 Toshiba Corp 半導体装置及びその製造方法
US20170133317A1 (en) * 2015-11-05 2017-05-11 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US20170200642A1 (en) 2016-01-08 2017-07-13 Applied Materials, Inc. Co or ni and cu integration for small and large features in integrated circuits

Also Published As

Publication number Publication date
JP2018207110A (ja) 2018-12-27
KR20180133341A (ko) 2018-12-14
US10580691B2 (en) 2020-03-03
JP7492618B2 (ja) 2024-05-29
US20180350665A1 (en) 2018-12-06
JP2023062148A (ja) 2023-05-02

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