KR102670339B1 - Source driver integrated circuit, display device and data processing method thereof - Google Patents

Abstract

The present invention relates to a source driver integrated circuit and a display device including the same. The source driver integrated circuit divides first and second image data into a preset number of bits from one image data according to a signal from the outside. a first latch that sequentially inputs and outputs data and has a storage space of a size matching the number of bits of either first image data or second image data; a second latch that inputs and outputs the first image data provided from the first latch; It includes a digital-to-analog converter that combines the second image data provided from the first latch and the first image data provided from the second latch and converts them into analog form. Accordingly, by reducing the number of latches or flip-flops of the first latch and the second latch, not only can the size of the source driver integrated circuit be reduced, but also the cost can be reduced.

Description

Source driver integrated circuit, display device, and data processing method {SOURCE DRIVER INTEGRATED CIRCUIT, DISPLAY DEVICE AND DATA PROCESSING METHOD THEREOF}

These embodiments relate to a source driver integrated circuit, a display device, and a data processing method thereof.

As the information society develops, the demand for display devices for displaying images increases in various forms. As the information society develops, the demand for display devices for displaying images increases in various forms, and in recent years, liquid crystal display devices Various display devices such as LCD (Liquid Crystal Display Device), PDP (Plasma Display Panel), and OLED (Organic Light Emitting Display Device) are being used.

This display device includes a display panel in which multiple data lines and multiple gate lines are arranged, a source driver that supplies data voltages to multiple data lines, a gate driver that supplies scan signals to multiple gate lines, and a source driver. and a timing controller that controls the gate driver.

The gate driver can receive control signals from a timing controller and drive a plurality of gate lines arranged on the display panel.

The source driver may include a plurality of integrated circuits, and each integrated circuit receives image data and a signal that controls the operation timing of each integrated circuit from a timing controller to perform data driving.

The timing controller is connected to each integrated circuit of the source driver through a pair of data wires, and divides the image data and provides it to each integrated circuit of the source driver through a pair of data wires. That is, in the case of 10 bits of video data, 5 bits of video data are provided through each data wire. In this existing structure, a pair of image data divided by 5 bits is input through each data wire, and then the pair of image data is recombined and processed in the source driver integrated circuit.

This point-to-point data transmission is based on the EPI (Embedded clock Point-to-point Interface) transmission protocol, and video data is transmitted at an EPI rate of 2.1 GHz through a data wire pair.

Meanwhile, the integrated circuits of the source driver include a shift register, a first latch, a second latch, a digital-to-analog converter, and an output buffer corresponding to the number of pixels. Here, the first latch and the second latch have latches or flip-flops of a size that matches the size of the image data, and when image data is provided from the timing controller through a pair of data wires of 5 bits at a time, the first latch Since 10 bits of image data are stored in the latch at once, and the image data from the first latch is transferred to the second latch as is, the first latch and the second latch are latches or flips of a size that matches the total size of the image data. -A flop is provided. Since the first and second latches are formed in numbers corresponding to the number of each pixel, the number or size of the first and second latches greatly affects the size and cost of the entire circuit.

The present embodiments are intended to solve the above problems, and provide a source driver integrated circuit, a display device, and We would like to provide a method of processing that data.

One embodiment sequentially inputs and outputs first and second image data divided by a preset number of bits from one image data according to a signal from the outside, and either the first image data or the second image data is sequentially input and output. A first latch having a storage space of a size matching the number of bits is presented. And a second latch that inputs and outputs the first image data provided from the first latch is presented. A source driver integrated circuit including a digital-to-analog converter that combines the second image data provided from the first latch and the first image data provided from the second latch and converts them into analog form.

In another embodiment, a display panel including a plurality of pixels disposed in an intersection area of a plurality of data lines and a plurality of gate lines; A gate driver that supplies a scan signal through the gate line; a source driver that supplies a data voltage through the data line; A timing controller is presented that sequentially provides a signal that controls the driving timing of the source driver and first and second image data formed by dividing image data into a preset number of bits to the source driver. The source driver sequentially inputs and outputs first and second video data divided into a preset size from one piece of video data according to the external signal, and selects one of the first video data and the second video data. A first latch is provided having a storage space of a size matching the number of bits. And the source driver provides a second latch that inputs and outputs the first image data provided from the first latch. The source driver includes a plurality of source driver integrated circuits including a digital-to-analog converter that combines the second image data provided from the first latch and the first image data provided from the second latch and converts them into analog form. Present a display device.

In another embodiment, a plurality of source driver integrated circuits including a first latch and a second latch for inputting and outputting image data according to an external signal, and a digital-to-analog converter for converting the image data into analog form. presents. We propose a division step of dividing one image data into a preset size to generate first and second image data. A step of storing the first image data in the first latch is proposed. A step of transferring and storing the first image data from the first latch to the second latch is proposed. A step of storing the second image data in the first latch is proposed. A step of transferring the second image data from the first latch and the first image data from the second latch to the digital-to-analog converter is proposed. We propose a data processing method for a display device that includes combining the first image data and the second image data in the digital-to-analog converter and converting them into analog form.

According to the present embodiments as described above, by reducing the number of latches or flip-flops of the first latch and the second latch, not only can the size of the source driver integrated circuit be reduced, but the cost can also be reduced. there is.

According to this embodiment, circuit wiring can be simplified by configuring a single data wire for transmitting image data from the timing controller to the source driver integrated circuit (SDIC).

1 is a schematic system configuration diagram of an organic light emitting display device according to the present embodiments.
Figure 2 is a block diagram of a source driver integrated circuit (SDIC) according to an embodiment of the present invention.
3A to 3C are configuration diagrams of a first latch and a second latch according to the present invention.
Figures 4a to 4d are waveform diagrams of the SOE signal according to an embodiment of the present invention.
Figures 5a to 5d are waveform diagrams of SOE signals according to another embodiment of the present invention.
Figures 6A to 6D are block diagrams of a source driver integrated circuit (SDIC) showing the process of processing divided first image data according to an embodiment of the present invention.
FIG. 7 is a flowchart showing the process of processing image data in the source driver integrated circuit (SDIC) of FIG. 6.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments introduced below are provided as examples so that the idea of the present invention can be sufficiently conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And in the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numerals refer to like elements throughout the specification.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification. The sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of explanation.

When an element or layer is referred to as another element or “on” or “on” it includes not only those directly on top of another element or layer, but also all cases where there is another layer or element in between. do. On the other hand, referring to an element as “directly on” or “directly on” indicates that there is no intervening element or layer.

Spatially relative terms such as “below, beneath,” “lower,” “above,” and “upper” refer to one element or component as shown in the drawing. It can be used to easily describe the correlation with other elements or components. Spatially relative terms should be understood as terms that include different directions of the element during use or operation in addition to the direction shown in the drawings. For example, if an element shown in the drawings is turned over, an element described as “below” or “beneath” another element may be placed “above” the other element. Accordingly, the illustrative term “down” can include both downward and upward directions.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

1 is a schematic system configuration diagram of a display device according to the present embodiments.

Referring to FIG. 1, the display device 100 according to the present embodiments has a plurality of data lines (DL) and a plurality of gate lines (GL), and a plurality of subpixels (SP: Sub Pixel). a display panel 110, a source driver 120 connected to the top or bottom of the display panel 110 and driving a plurality of data lines DL, and a gate driver driving a plurality of gate lines GL1 ( 130) and a timing controller 140 that controls the source driver 120 and the gate driver 130.

A plurality of subpixels (SP) are arranged in a matrix type on the display panel 110.

The source driver 120 drives multiple data lines DL by supplying a data voltage to the multiple data lines DL.

The gate driver 130 sequentially supplies scan signals to the plurality of gate lines GL under the control of the timing controller 140 to sequentially drive the plurality of gate lines GL. Here, the gate driver 130 is also called a scan driver.

The gate driver 130 may be located on only one side of the display panel 110, as shown in FIG. 1, or may be located on both sides depending on the case, depending on the driving method or panel design method. Additionally, the gate driver 130 may include one or more gate driver integrated circuits (GDIC: Gate Driver Integrated Circuit).

When the gate line is opened by a specific scan signal, the source driver 120 converts the image data (Data) received from the timing controller 140 into an analog data voltage (Vdata) and converts it to a plurality of data lines (DL). By supplying, multiple data lines (DL) are driven.

The source driver 120 may include at least one source driver integrated circuit (SDIC) and drive multiple data lines.

Each of the above-described gate driver integrated circuits (GDIC) or source driver integrated circuits (SDIC) is bonded to the bonding pad of the display panel 110 using a tape automated bonding (TAB) method or a chip on glass (COG) method. Bonding Pad), may be placed directly on the display panel 110, or, depending on the case, may be integrated and placed on the display panel 110.

The timing controller 140 converts the input video data input from the outside to suit the data signal format used by the source driver 120, and then outputs the converted video data (Data). In addition to the source driver 120 and In order to control the gate driver 130, timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal are input, various control signals are generated, and the source driver 120 and It is output to the gate driver 130.

For example, the timing controller 140 uses a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE) to control the gate driver 130. : Outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable.

Here, the gate start pulse (GSP) controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver 130. The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of a scan signal (gate pulse). The gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits.

Additionally, the timing controller 140 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE) to control the source driver 120. Outputs various data control signals (DCS: Data Control Signal) including Output Enable.

Here, the source start pulse (SSP) controls the data sampling start timing of one or more source driver integrated circuits (SDICs) constituting the source driver 120. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data in each source driver integrated circuit (SDIC). The source output enable signal (SOE) controls the output timing of the source driver 120.

The timing controller 140 and the source driver integrated circuit (SDIC) are connected to each IC of the source driver integrated circuit (SDIC) in a point-to-point manner.

The timing controller 140 according to this embodiment is connected to each cell of the source driver integrated circuit (SDIC) through one data wire 145, and the timing controller 140 is connected to each cell of the source driver integrated circuit (SDIC) through one data wire 145. First image data and second image data, which will be described later, are sequentially transmitted to the source driver integrated circuit (SDIC).

If one video data is divided into first video data and second video data and transmitted sequentially, it may take twice as much time at the same speed as before, but recently, as the EPI speed has increased to 5GHz, it can be transmitted twice. Even if transmitted sequentially, video data can be transmitted faster than when transmitting video data all at once.

As one data wire 145 is used to transmit image data between the timing controller 140 and the source driver, the circuit can be constructed more simply.

As this timing controller 140 uses only one data wire 145, it divides one image data into first image data and second image data, and when dividing the first image data and second image data, the first image data The number of bits of the image data and the second image data may be divided equally, or the number of bits of one of the first image data and the second image data may be greater.

For example, in the case of 10-bit image data, the timing controller 140 may divide the first image data and the second image data into 5 bits each. In the case of 8-bit image data, the timing controller 140 may divide the first image data and the second image data into 4 bits each.

Additionally, the timing controller 140 may divide the first image data so that the number of bits is greater than the number of bits of the second image data. For example, in the case of 10-bit image data, the timing controller 140 divides the first image data into 6-bit, 7-bit, 8-bit, and 9-bit, and the second image data into 4-bit, 3-bit, 2-bit, and 4-bit corresponding to the first image data, respectively. It can be divided into 1 bit.

Conversely, the timing controller 140 may divide the first image data so that the number of bits is less than the number of bits of the second image data. For example, in the case of 10 bit image data, the timing controller 140 divides the first image data into 4 bits, 3 bits, 2 bits, and 1 bit, and the second image data into 6 bits, 7 bits, 8 bits, and 6 bits corresponding to the first image data, respectively. It can be divided into 9 bits.

The timing controller 140 may sequentially provide divided first and second image data to the source driver 120 along with a source output enable signal (SOE).

Figure 2 is a block diagram of a source driver integrated circuit (SDIC) according to an embodiment of the present invention.

The source driver integrated circuit (SDIC) according to this embodiment includes a shift register 121, a first latch 123, a second latch 125, a digital analog converter (DAC: 127), and an output buffer ( 129), etc. may be included.

The shift register 121 sequentially drives each cell of the first latch 123 to perform line-by-line driving, and is horizontally synchronized with the horizontal clock signal (Hclock) provided from the timing controller 140. The operation time of the first latch 123 is controlled according to the signal Hsync. That is, the shift register 121 sequentially synchronizes all data corresponding to one gate line (GL) with the horizontal synchronization signal (Hsync) as the start signal to the horizontal clock signal (Hclock) to the first latch ( 123) to be sampled and stored in each cell.

The first latch 123 is configured to have as many cells as the number of data lines DL, and stores image data of each column provided from the timing controller 140 in each cell under control from the shift register 121. For example, in the case of an 8-bit 480-channel source driver integrated circuit (SDIC), the first latch 123 is generally composed of 480 cells, and in the case of a 10-bit 960-channel source driver integrated circuit (SDIC), the first latch 123 is composed of 480 cells. The latch 123 may be composed of 960 cells.

Each cell of the first latch 123 includes a latch or flip-flop as a storage space, and the number of latches or flip-flops in each cell is less than the number of bits of image data. The latch or flip-flop of each cell of the first latch 123 may be configured to match the larger number of bits of the first image data or the second image data provided from the timing controller 140.

The second latch 125 stores the first image data provided from the first latch 123 and can transmit the first image data to the digital-to-analog converter 127 according to the SOE signal provided from the timing controller 140.

The second latch 125, like the first latch 123, is configured to have cells equal to the number of data lines, and each cell may be formed of a number of latches or flip-flops less than the number of bits of image data. Since each cell of the second latch 125 stores only the first image data provided from the first latch 123, it is preferably formed with the same number of latches or flip-flops as the number of bits of the first image data.

For example, if the number of bits of the image data is 10 bits and the number of bits of the first image data are 9 bits, 8 bits, 7 bits, and 6 bits, respectively, the number of bits of the second image data are 1 bit, 2 bits, 3 bits, and 4 bits, respectively. In this case, the latch or flip-flop of each cell of the first latch 123 matches the number of bits of the first image data and is formed as 9 bits, 8 bits, 7 bits, and 6 bits, respectively. And since the latch or flip-flop of each cell of the second latch 125 matches the number of bits of the first image data, like the first latch 123, it is formed with 9 bits, 8 bits, 7 bits, and 6 bits, respectively.

In more detail, as shown in FIG. 3A, if the number of bits of the first image data is 6 bits and the number of bits of the second image data is 4 bits, the latch or flip-flop of each cell of the first latch 123 is the first latch 123. Among the image data and the second image data, it is formed by matching the first image data with a larger number of bits, and the second latch 125 is also formed by matching the first image data. Accordingly, the latches or flip-props of the cells of the first latch 123 and the second latch 125 are all formed to match 6 bits, which is the number of bits of the first image data.

That is, if the number of bits of the first image data is greater than the number of bits of the second image data, the size of the latch or flip-flop of each cell of the first latch 123 and the first latch 125 is the bit of the first image data. It is formed in correspondence with numbers.

On the other hand, if the number of bits of the image data is 10 bits and the number of bits of the first image data is 1 bit, 2 bit, 3 bit, and 4 bit, respectively, the number of bits of the second image data is 9 bit, 8 bit, 7 bit, and 6 bit, respectively, and in this case, the first The latch or flip-flop of each cell of the latch 123 matches the number of bits of the second image data and is formed as 9 bits, 8 bits, 7 bits, and 6 bits, respectively.

In more detail, as shown in Figure 3b, when the first image data is formed of 2 bits and the second image data is formed of 8 bits, the latch or flip-flop of each cell of the first latch 123 is, It is formed by matching 8 bits, which is the number of bits of the second image data, which has the larger number of bits among the first and second image data. However, since only the first image data is provided to the second latch 125, the latch or flip-flop of each cell of the second latch 125 is formed by matching 2 bits, which is the number of bits of the first image data.

That is, if the number of bits of the second image data is greater than the number of bits of the first image data, the size of the latch or flip-flop of each cell of the first latch 123 is formed to correspond to the number of bits of the second image data. However, since the size of the latch or flip-flop of each cell of the second latch 125 is always formed to correspond to the number of bits of the first image data, the size of the latch or flip-flop of each cell of the first latch 123 differs from the size of the latch or flip-flop of each cell of the second latch 125.

In this way, the size of the latch or flip-flop of each cell of the first latch 123 is formed to match the larger of the number of bits of the first image data and the number of bits of the second image data, so that the first image data and the second image data All data can be stored in each cell of the first latch 123. Additionally, since the second latch 125 is determined according to the number of bits of the first image data, when the number of bits of the first image data is small, the size of the second latch 125 can also be formed to be small.

Meanwhile, when the number of bits of the first image data and the second image data are the same, that is, when the image data is 8 bits, the number of bits of the first image data and the second image data are 4 bits each, and the first latch 123 and the second Each cell of the 2 latch 125 is formed with 4 bits each. And when the image data is 10 bits, as shown in FIG. 3C, if the number of bits of the first image data and the second image data is 5 bits, each cell of the first latch 123 and the second latch 125 is It is formed of 5 bits.

If the size of the first image data and the second image data are formed to be the same, the size of each cell of the first latch 123 and the second latch 125 can be formed to be the same, so that the source driver is configured to an optimal size. An integrated circuit (SDIC) can be configured.

The first latch 123 stores the input first image data and may provide the first image data to the second latch 125 according to the SOE signal provided from the timing controller 140.

The first latch 123 provides first image data to the second latch 125 and then receives second image data according to the SOE signal provided from the timing controller 140. Then, the first latch 123 may provide the second image data to the digital-to-analog converter 127 according to the SOE signal. At the same time, the second latch 125 may provide the first image data provided from the first latch 123 to the digital-to-analog converter 127.

That is, the first image data can be transmitted to the digital-analog converter 127 through the second latch 125, and the second image data can be directly transmitted to the digital-analog converter 127 without passing through the second latch 125. there is.

In this embodiment, the number of latches or flip-flops in each cell of the first latch 123 and the second latch 125 is formed to be less than the number of bits of image data, so the first latch 123 and the second latch ( The size of each cell of 125) can be reduced, and accordingly, the sizes of the first latch 123 and the second latch 125 can be reduced. Accordingly, the size of the source driver integrated circuit (SDIC) on which the first latch 123 and the second latch 125 are mounted can be reduced, and the cost can also be reduced.

Meanwhile, the first latch 123 and the second latch 125 shown in FIGS. 3 to 6 of this embodiment are respectively one cell of the first latch 123 and one cell of the second latch 125. represents.

Figures 4a to 4d are waveform diagrams of the SOE signal according to an embodiment of the present invention.

The first latch 123 and the second latch 125 according to this embodiment input and output image data according to the SOE signal from the timing controller 140. In this embodiment, as the image data is divided and input/output, the SOE signal output from the timing controller 140 to control the input/output of the first and second image data is configured as shown in FIGS. 4A to 4D.

4A to 4D show waveforms consisting of a first signal (SIGNAL1) for controlling the input and output of the first image data and a second signal (SIGNAL2) for controlling the input and output of the second image data as one signal. there is.

The SOE signal includes a first signal (SIGNAL1) and a second signal (SIGNAL2), and the first signal (SIGNAL1) and the second signal (SIGNAL2) may be formed to have the same size and width. Here, the first signal (SIGNAL1) is used to control the input and output of the first image data, and the second signal (SIGNAL2) is used to control the input and output of the second image data.

When the SOE signal is input to the first latch 123 and the second latch 125, at the point when the first signal (SIGNAL1) rises as shown in (a), the first latch 123 receives the first image data. is stored in each cell of the first latch 123, and at the point when the first signal (SIGNAL1) falls as shown in (b), the first latch 123 outputs the first image data to the second latch. By transmitting the data to 125, the first image data is stored in the second latch 125.

Then, as shown in (c), at the point when the second signal (SIGNAL2) goes up, the first latch 123 receives the second image data and stores it in each cell. Finally, as in (d), at the point when the second signal (SIGNAL2) goes down, the first latch 123 transfers the second image data to the digital-to-analog converter 127, and at the same time, the second latch 125 also 1Transmit video data to the digital-to-analog converter (127). Then, the digital-to-analog converter 127 combines the first image data and the second image data.

Figures 5a to 5d are waveform diagrams of SOE signals according to another embodiment of the present invention.

The SOE signal of this embodiment may include a first signal (SIGNAL1) and a second signal (SIGNAL2). The first signal (SIGNAL1) and the second signal (SIGNAL2) are provided simultaneously from the timing controller 140.

The first signal (SIGNAL1) has a wider width than the second signal (SIGNAL2), turns on earlier than the second signal (SIGNAL2), and turns off later than the second signal (SIGNAL2).

When the first signal (SIGNAL1) is input to the first latch 123, as shown in (a), the first latch 123 receives the first image data at the point when the first signal (SIGNAL1) goes up and stores the first image data in each cell. Save it to And as shown in (b), when the E2 signal goes up, the first latch 123 transfers the first image data to the second latch 125. Then, as shown in (c), when the second signal SIGNAL2 goes down, the first latch 123 receives and stores the second image data. Finally, as in (d), at the point when the first signal (SIGNAL1) goes down, the first latch 123 transfers the second image data to the digital-analog converter 127, and at the same time, the second latch 125 transmits the second image data to the digital-analog converter 127. 1Transmit video data to the digital-to-analog converter (127).

The digital-to-analog converter 127 receives second image data and first image data from the first latch 123 and the second latch 125, respectively, and converts them into analog data voltages.

When the digital-analog converter 127 receives first image data from the second latch 125 and second image data from the first latch 123, the digital-analog converter 127 sequentially combines the first image data and the second image data. Restores it as a single video data.

Then, the digital-to-analog converter 127 converts the recovered image data from a digital form to an analog data voltage based on the externally supplied gamma reference voltage.

The output buffer 129 is composed of an operational amplifier and receives an analog data voltage from the digital-to-analog converter 127 and amplifies the current, allowing the data voltage to charge the capacitance in the subpixel in a short time.

FIGS. 6A to 6D are block diagrams of a source driver integrated circuit (SDIC) showing the process of processing divided first image data according to an embodiment of the present invention, and FIG. 7 is a block diagram of the source driver integrated circuit (SDIC) of FIG. 6. ) This is a flowchart showing the process of processing video data.

6A to 6D show an example where the first image data and the second image data are each formed of 5 bits. However, as described above, the sizes of the first image data and the second image data can be formed in various ways. Of course it exists.

In the embodiment of FIGS. 6A to 6D, the first image data is 5 bit image data where each bit is composed of D9, D8, D7, D6, and D5, and the second image data is each bit composed of D4, D3, and D2. , D1, and D0 are 5 bits of image data.

When the first image data and the SOE signal are provided to the source driver integrated circuit (SDIC) from the timing controller 140, as shown in FIG. 6A, at the point when the first signal (SIGNAL1) goes up, the first latch 123 The first image data is stored (S700).

Then, as shown in FIG. 6B, the first latch 123 transfers the first image data to the second latch 125 at the point when the first signal SIGNAL1 goes down (S710). Then, the second latch 125 stores the first image data in the second latch 125. At the point when the second signal SIGNAL2 goes up, the first latch 123 stores the second image data provided from the timing controller 140 in the first latch 123 (S720). Accordingly, as shown in FIG. 6C, the second image data is stored in the first latch 123, and the first image data is stored in the second latch 125.

In this state, when the second signal (SIGNAL2) goes down, the first latch 123 transfers the stored second image data to the digital-analog converter 127, and the second latch 125 transmits the first image data. It is transmitted to the digital-to-analog converter (127) (S730). Then, as shown in FIG. 6D, the first image data and the second image data are transferred to the digital-analog converter 127, and the digital-analog converter 127 combines the first image data and the second image data and then (S740), the recovered image data is converted to analog data (S750).

Image data that has completed analog conversion is provided to the output buffer 129, and the output buffer 129 amplifies the current of the analog image data.

As such, in this embodiment, by dividing and providing image data, the number of latches or flip-flops in each cell of the first latch 123 and the second latch 125 can be reduced. Accordingly, the size of the source driver integrated circuit (SDIC) on which the first latch 123 and the second latch 125 are mounted can be reduced, as well as the cost.

Additionally, by dividing the image data, the data wires 145, which were previously configured as a pair to transmit image data from the timing controller 140 to the source driver integrated circuit (SDIC), can be configured as one. Accordingly, circuit wiring between the timing controller 140 and the source driver integrated circuit (SDIC) can be simplified.

The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present invention.

In addition, although the description has been made focusing on the embodiments above, this is only an example and does not limit the present invention, and those skilled in the art will understand the above examples without departing from the essential characteristics of the present embodiments. You will be able to see that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. And these variations and differences in application should be construed as being included in the scope of the present invention as defined in the attached claims.

100: display device 110: display panel
120: Source driver 121: Shift register
123: first latch 125: second latch
127: digital analog converter 129: output buffer
130: gate driver 140: timing controller

Claims (8)

According to a signal from the outside, N/2 bit first and second video data divided into 1/2 from one N bit video data are sequentially input and output, and the N/2 bit first and second video data of a size matching the N/2 number of bits are sequentially input and output. a first latch having a storage space;
a second latch for inputting and outputting the N/2 bit first image data provided from the first latch; and
A digital-to-analog converter that combines the N/2-bit second image data provided from the first latch and the N/2-bit first image data provided from the second latch, restores the N-bit image data, and converts it into analog form. Source driver integrated circuit containing ; delete A display panel including a plurality of pixels disposed in intersection areas of a plurality of data lines and a plurality of gate lines;
A gate driver that supplies a scan signal through the gate line;
a source driver that supplies a data voltage through the data line;
It includes a signal that controls the driving timing of the source driver, and a timing controller that sequentially provides N/2-bit first and second image data formed by dividing N-bit image data into 1/2 to the source driver;
The source driver is,
a first latch that sequentially inputs and outputs the N/2 bit first and second image data according to a signal from the timing controller, and has a storage space of a size matching the number of N/2 bits;
a second latch that inputs and outputs the N/2 bit first image data provided from the first latch and has a storage space of a size matching the number of N/2 bits; and
A digital-to-analog converter that combines the N/2-bit second image data provided from the first latch and the N/2-bit first image data provided from the second latch, restores the N-bit image data, and converts it into analog form. A display device including a plurality of source driver integrated circuits including; delete delete Data of a display device having a plurality of source driver integrated circuits including a first latch and a second latch for inputting and outputting image data according to an external signal, and a digital-to-analog converter for converting the image data into analog form. In the processing method,
A division step of dividing one N-bit image data into 1/2 to generate N/2-bit first and second image data;
storing the N/2 bit first image data in the first latch;
transferring and storing the N/2 bit first image data from the first latch to the second latch;
storing the N/2 bit second image data in the first latch;
transferring the N/2 bit second image data from the first latch and the N/2 bit first image data from the second latch to the digital-to-analog converter; and
Data processing of a display device comprising: combining the N/2-bit first image data and the N/2-bit second image data in the digital-to-analog converter to restore the N-bit image data and converting it to analog form; method. delete delete

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