KR102656041B1 - Display device and method for controlling display device - Google Patents

Abstract

A display device according to an embodiment of the present specification includes a display panel including a plurality of pixels. In one embodiment herein, each pixel includes a pixel circuit and a sensing circuit. When the display device is driven in sensing mode, the operation section of the display device is divided into an initialization section, a sensing section, and a sampling section. In one embodiment of the present specification, when the display device is driven in a sensing mode, the sensing capacitors of all pixels are simultaneously charged with a sensing voltage in the sensing period. Accordingly, the length of the sensing section and the time during which the sensing mode is performed are reduced, thereby shortening the total time required for external compensation.

Description

Display device and control method of the display device {DISPLAY DEVICE AND METHOD FOR CONTROLLING DISPLAY DEVICE}

This specification relates to a display device and a method of controlling the display device, and more specifically, to a display device and a method of controlling the display device that can reduce the time required to compensate for deterioration of a display panel.

Representative examples of display devices include Liquid Crystal Display device (LCD), Plasma Display Panel device (PDP), Field Emission Display device (FED), and Electro Luminescence. Display device (ELD), Electro-Wetting Display device (EWD), and Organic Light Emitting Display device (OLED).

Among these, organic light emitting display devices display images through pixels containing organic light emitting elements that are self-luminous elements. Therefore, compared to other display devices, organic light emitting display devices have the advantage of having a thinner thickness, a wider viewing angle, and faster response speed. However, pixels of organic light emitting display devices deteriorate due to various reasons. When the display panel deteriorates due to the deterioration of each pixel, afterimages or stains occur and image quality deteriorates. Accordingly, various technologies are being applied to compensate for the deterioration of the display panel.

One of the methods to compensate for the deterioration of the display panel is an external compensation method. In the external compensation method, sensing of the characteristic value of each pixel is performed to compensate for the deviation of the characteristic value of each pixel. However, since sensing the characteristic value of each pixel is performed for each pixel or each line, a considerably long time is required for sensing the characteristic value. In particular, the higher the resolution of the display panel, the longer the time required to sense characteristic values, which increases the time required for external compensation.

The purpose of the present specification is to provide a display device and a control method for the display device that can shorten the total time required for external compensation by reducing the time required for sensing characteristic values.

The purposes of the present specification are not limited to the purposes mentioned above, and other purposes and advantages of the present specification that are not mentioned can be understood through the following description and will be more clearly understood by the examples of the present specification. Additionally, it will be readily apparent that the objects and advantages of the present specification can be realized by the means and combinations thereof indicated in the patent claims.

A display device according to an embodiment of the present specification includes a display panel including a plurality of pixels. In one embodiment herein, each pixel includes a pixel circuit and a sensing circuit.

In one embodiment of the present specification, the pixel circuit includes a driving transistor that supplies a driving current to an organic light emitting diode, which is turned on by a scan signal supplied through a gate line and supplies a data voltage supplied through a data line to the driving transistor. It includes a first switching transistor and a second switching transistor that is turned on by a sensing signal supplied through a sensing signal line to initialize the driving transistor.

In addition, in one embodiment of the present specification, the sensing circuit is closed by an initialization signal and closed by a first switch that supplies a reference voltage through the reference line and a sampling signal to transmit the sensing voltage charged in the sensing capacitor to the data driver. Includes a second switch.

In addition, the display device according to an embodiment of the present specification includes a sensing capacitor connected to the reference line, a data driver that supplies the data voltage through a data line and senses the sensing voltage charged in the sensing capacitor, and a data driver that senses the sensing voltage charged in the sensing capacitor through the gate line. It includes a gate driver that supplies the scan signal and the sensing signal through the sensing signal line, and a timing controller that controls driving of the data driver and the gate driver and generates compensation data based on the sensing voltage.

In one embodiment of the present specification, the display device has two modes, a display mode that displays an image input from a host system through a display panel and a sensing mode that senses changes in the characteristic values of each pixel to compensate for deterioration of the display panel. It runs.

When the display device is driven in sensing mode, the operation section of the display device is divided into an initialization section, a sensing section, and a sampling section. In one embodiment of the present specification, when the display device is driven in a sensing mode, the sensing capacitors of all pixels are simultaneously charged with a sensing voltage in the sensing period. Accordingly, the length of the sensing section and the time during which the sensing mode is performed are reduced, thereby shortening the total time required for external compensation.

Additionally, in one embodiment of the present specification, when a sensing clock signal is input in a sensing section of the sensing mode, the gate driver simultaneously supplies the scan signal and the sensing signal to all pixels.

In one embodiment of the present specification, the gate driver includes a plurality of gate integrated circuits connected to the gate line and the scan line, and the sensing clock signal is simultaneously input to each gate integrated circuit in the sensing section of the sensing mode. do.

According to the display device and the control method of the display device according to an embodiment of the present specification, the time required for sensing characteristic values is reduced, so there is an advantage in that the total time required for external compensation is shortened.

Figure 1 shows the configuration of a display device according to an embodiment of the present specification.
Figure 2 is a detailed circuit diagram of a pixel according to an embodiment of the present specification.
Figure 3 shows the configuration of a gate driver according to an embodiment of the present specification.
Figure 4 shows the configuration of a gate driver according to another embodiment of the present specification.
FIG. 5 shows an operation section and waveforms of signals applied in each operation section when the display device according to an embodiment of the present specification is driven in a sensing mode.
Figure 6 is a flowchart showing a method of controlling a display device according to an embodiment of the present specification.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and the present embodiments only serve to ensure that the disclosure of the present specification is complete and that common knowledge in the technical field to which the present specification pertains is provided. It is provided to fully inform those who have the scope of the invention, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it includes multiple elements unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

Each feature of the various embodiments of the present specification can be partially or entirely combined or combined with each other, various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other or may be implemented in conjunction with each other. It may be possible.

Figure 1 shows the configuration of a display device according to an embodiment of the present specification.

Referring to FIGS. 1 and 2 , an organic light emitting display device 1 according to an embodiment of the present invention includes a display panel 10 and panel drivers 12, 14, and 16.

The display panel 10 includes a plurality of gate lines (GL), a plurality of sensing signal lines (SL), a plurality of data lines (DL), a plurality of driving power lines (PL), a plurality of reference lines (RL), and a plurality of Contains a pixel (P).

The difference voltage (Vdata-Vref) between the data voltage (Vdata) and the sensing reference voltage (Vref) is connected to the capacitor (Cst) connected between the gate electrode and the source electrode of the driving transistor (DT) to which the first driving power (VDD) is supplied. It is charged. Data current (Ioled) flows from the first driving power source (VDD) to the second driving power source (VSS) through the driving transistor (DT) by the charging voltage of the capacitor (Cst), and the data current (Ioled) flows into the organic light emitting diode. (OLED) emits light.

Each of the plurality of pixels P may be comprised of one of red pixels, green pixels, blue pixels, and white pixels. For example, one unit pixel displaying one image may be composed of adjacent red pixels, green pixels, and blue pixels, or may be composed of adjacent red pixels, green pixels, blue pixels, and white pixels.

Each pixel P is formed in a pixel area defined on the display panel 10 . The pixel area includes a plurality of gate lines (GL), a plurality of sensing signal lines (SL), a plurality of data lines (DL), a plurality of driving power lines (PL), and a plurality of reference lines (PL) disposed on the display panel 10. RL).

Each pixel P includes a pixel circuit for displaying an image and a sensing circuit for sensing changes in characteristic values of each pixel.

A plurality of gate lines GL and a plurality of sensing signal lines SL may be formed side by side in the first direction (eg, horizontal direction) within the display panel 10 . A scan signal (SCAN, gate driving signal) output from the gate driver 14 is applied to the gate line (GL), and a sensing signal (SENSE) output from the gate driver 14 is applied to the sensing signal line (SL). .

The plurality of data lines DL may be formed in a second direction (eg, vertical direction) to intersect the plurality of gate lines GL and the plurality of sensing signal lines SL. The data voltage Vdata output from the data driver 12 is supplied to the data line DL.

A plurality of reference lines RL are formed parallel to each of the plurality of data lines DL. The display reference voltage (Vpre_r) or the sensing reference voltage (Vref) output from the data driver 12 may be selectively supplied to the reference line (RL). The display reference voltage Vpre_r is supplied to each reference line RL during the data charging period of each pixel P. Sensing The sensing reference voltage (Vref) is applied to the reference line (RL) when the display device 1 is driven in the sensing mode to detect the characteristic value of the driving transistor (DT) of each pixel (P), such as the threshold voltage or mobility. supplied.

A plurality of driving power lines (PL) may be formed in parallel with the gate line (GL) and supply the first driving power (VDD) to the pixel (P). Additionally, a plurality of driving power lines (PL) may be formed in parallel with the data line (DL) and supply the first driving power (VDD) to the pixel (P).

The data driver 12 is connected to each of the plurality of driving power lines PL and can supply driving power (VDD, VSS) supplied from an external power supply (not shown) to the plurality of driving power lines PL.

The panel driver includes a data driver 12 that drives the data line DL of the display panel 10, a gate driver 14 that drives the gate line GL of the display panel 10, and a data driver 12 and a gate. It includes a timing controller 16 that controls the driving of the driver 14.

The timing controller 16 receives input image data (Idata) and timing synchronization signal (TSS) from a host system (not shown).

The timing controller 16 sorts the output image data generated based on the input image data Idata and supplies it to the data driver 12. The timing controller 16 receives input image data (Idata) and generates output image data by reflecting compensation data for compensating for deterioration of the display panel 10 in the input image data (Idata).

In addition, the timing controller 16 includes a data control signal and a data control signal that controls the driving timing of the data driver 12 using the dot clock, data enable signal, horizontal synchronization signal, and vertical synchronization signal included in the timing synchronization signal (TSS). A gate control signal that controls the driving timing of the gate driver 14 is generated and output.

Meanwhile, in one embodiment of the present specification, the display device 1 has a display mode and display that displays an image based on input image data (Idata) input from a host system (not shown) through the display panel 10. In order to compensate for the deterioration of the panel 10, it is operated in two modes, including a sensing mode that senses changes in the characteristic values of each pixel (P).

The gate driver 14 is connected to a plurality of gate lines (GL) and a plurality of sensing signal lines (SL).

In the display mode, the gate driver 14 generates a scan signal (SCAN) of the gate-on voltage level for each horizontal section according to the gate control signal (GCS) supplied from the timing controller 16 to control the plurality of gate lines (GL). supply to.

The scan signal SCAN has a gate-on voltage level during the data charging period of each pixel (P), and has a gate-off voltage level during the light-emitting period of each pixel (P).

In the sensing mode, the gate driver 14 supplies a scan signal (SCAN) through a plurality of gate lines (GL) and a sensing signal (SENSE) through a plurality of sensing signal lines (SL).

The gate driver 14 is connected to each of the plurality of driving power lines (PL1 to PLm) and supplies the first driving power (VDD) supplied from an external power supply (not shown) to the plurality of driving power lines (PL1 to PLm). supply.

The data driver 12 is connected to a plurality of data lines DL1 to DLn and operates in a display mode and a sensing mode according to mode control of the timing controller 16. The display mode for displaying an image includes a data charging section in which each pixel is charged with a data voltage and a light emitting section in which an organic light emitting diode (OLED) emits light. The sensing mode includes an initialization period, a sensing period, and a sampling period.

Figure 2 is a detailed circuit diagram of a pixel according to an embodiment of the present specification.

As shown in FIG. 2, each pixel (P) included in the display panel 10 according to an embodiment of the present specification includes an organic light emitting diode (OLED), a pixel circuit (PC), and a sensing circuit (SC). Includes. Here, each transistor (ST1, ST2, DT) is an N-type transistor and can be an a-Si transistor, poly-Si transistor, oxide transistor, organic transistor, etc. However, in other embodiments of the present specification, each transistor (ST1, ST2, and DT) may be a P-type transistor.

The organic light emitting diode (OLED) emits light by the data current (Ioled) supplied from the driving transistor (DT) and emits monochromatic light with luminance corresponding to the data current (Ioled).

The organic light emitting diode (OLED) includes an anode electrode (not shown) connected to the second node (n2) of the pixel circuit (PC), an organic layer (not shown) formed on the anode electrode, and a second driving power source formed on the organic layer. It includes a cathode electrode (not shown) to which (VSS) is supplied.

The organic layer may be formed to have a structure of a hole transport layer/organic emission layer/electron transport layer or a structure of a hole injection layer/hole transport layer/organic emission layer/electron transport layer/electron injection layer. Furthermore, the organic layer may further include a functional layer to improve the luminous efficiency and/or lifespan of the organic light-emitting layer. The second driving power source VSS may be supplied to the cathode electrode of the organic light emitting diode (OLED) through a second driving power line (not shown) formed in a line shape.

The pixel circuit P includes a driving transistor DT, a first switching transistor ST1, a second switching transistor ST2, and a storage capacitor Cst.

The driving transistor DT has a gate electrode commonly connected to the drain electrode of the first switching transistor ST1 and the first electrode of the storage capacitor Cst, and the driving transistor DT has a source connected to the driving power line PL. Contains electrodes. Additionally, the driving transistor DT includes a drain electrode commonly connected to the drain electrode of the second switching transistor ST2, the second electrode of the storage capacitor Cst, and the anode of the organic light emitting diode (OLED).

The driving transistor (DT) is turned on by the voltage of the storage capacitor (Cst) in each light emission period. Accordingly, a driving current is supplied to the organic light emitting diode (OLED) by the first driving power source (VDD).

The storage capacitor Cst is connected between the gate electrode and the drain electrode of the driving transistor DT, that is, between the first node n1 and the second node n2. The storage capacitor Cst is charged with the difference voltage between the voltages supplied to each of the first node n1 and the second node n2, and the driving transistor DT is turned on or off depending on the charged voltage.

The first switching transistor ST1 has a gate electrode connected to the gate line GL, a source electrode (first electrode) connected to the data line DL, and a first node (n1) connected to the gate electrode of the driving transistor DT. ) and a drain electrode (second electrode) connected to the terminal.

The first switching transistor ST1 is turned on by the scan signal SCAN at the gate-on voltage level supplied to the gate line GL, and transmits the data voltage Vdata supplied through the data line DL to the first node. (n1) That is, it is supplied to the gate electrode of the driving transistor (DT).

The second switching transistor ST2 is connected between the second node n2 of the pixel circuit PC and the reference line RL. The second switching transistor ST2 is turned on by the sensing signal SENSE at the gate-on voltage level supplied to the sensing signal line SL. When the second switching transistor (ST2) and the first switch (SW1) are turned on, the sensing reference voltage (Vref) is supplied to the sensing capacitor (Csen) through the reference line (RL) to initialize the sensing capacitor (Csen).

The digital data voltage Vdata supplied from the data driver 12 is converted into an analog voltage by a digital-to-analog converter (DAC, 122) and supplied to the pixel P through the data line DL. In FIG. 2 , the digital-analog converter 122 is shown separately from the data driver 12, but depending on the embodiment, the digital-analog converter 122 may be included in the data driver 12.

The sensing capacitor (Csen) is connected to the reference line (RL). The sensing capacitor (Csen) is charged with a sensing voltage by driving the sensing circuit (SC), and the magnitude of the sensing voltage charged in the sensing capacitor (Csen) is converted to a digital value by the analog-to-digital converter (ADC, 124). It is transmitted to the data driver 12. In FIG. 2 , the analog-to-digital converter 124 is shown separately from the data driver 12, but depending on the embodiment, the analog-to-digital converter 124 may be included in the data driver 12.

The sensing circuit (SC) includes a first switch (SW1) and a second switch (SW2).

The first switch (SW1) is connected between the reference line (RL) and a power supply that supplies the sensing reference voltage (Vref). The first switch (SW1) is closed by the initialization signal (SPRE) and supplies the sensing reference voltage (Vref) through the reference line (RL).

The second switch SW2 is disposed on the reference line RL. The second switch SW2 is closed by the sampling signal SAM and transfers the voltage of the device connected to the reference line RL to the data driver 12.

In one embodiment of the present specification, the sensing circuit (SC) and the data driver 12 may be implemented as a single integrated circuit.

Figure 3 shows the configuration of a gate driver according to an embodiment of the present specification. Figure 4 also shows the configuration of a gate driver according to another embodiment of the present specification.

The gate drivers 14, 14a, and 14b according to an embodiment of the present specification include a plurality of gate integrated circuits (ICs) 30_1 to 30_m. In one embodiment of the present specification, the gate drivers 14, 14a, and 14b may be implemented in a gate in panel (GIP) method including a plurality of gate integrated circuits 30_1 to 30_m. Additionally, each gate integrated circuit 30_1 to 30_m may include one or more shift registers.

As shown in FIG. 3, the gate driver 14 according to an embodiment of the present specification may be implemented in a single gate method. Each gate integrated circuit (30_1 to 30_m) is connected to one gate line (GL) and one sensing signal line (SL), respectively. However, in another embodiment, multiple gate lines and multiple sensing signal lines may be connected to one gate integrated circuit.

A clock signal CLKs is input to each gate integrated circuit 30_1 to 30_m. Each gate integrated circuit (30_1 to 30_m) generates a gate signal (SCAN) and a sensing signal (SENSE) based on the clock signal (CLKs), supplies the gate signal (SCAN) through the gate line (GL), and performs sensing. A sensing signal (SENSE) is supplied through the signal line (SL).

Each gate integrated circuit (30_1 to 30_m) can independently output a gate signal (SCAN) and a sensing signal (SENSE) according to the driving mode (display mode, sensing mode) and operation section of the display device 1. .

Additionally, a sensing clock signal (SENCLK) may be input to each gate integrated circuit (30_1 to 30_m). In one embodiment of the present invention, the sensing clock signal SENCLK may be simultaneously input to each gate integrated circuit 30_1 to 30_m in the sensing period when the display device 1 is driven in the sensing mode. When the sensing clock signal SENCLK is simultaneously input to each gate integrated circuit 30_1 to 30_m, each gate integrated circuit 30_1 to 30_m simultaneously outputs the gate signal SCAN and the sensing signal SENSE.

Meanwhile, as shown in FIG. 4, in another embodiment of the present specification, the gate drivers 14a and 14b may be implemented in a dual gate method. In the embodiment of FIG. 4 , the first gate driver 14a includes odd-numbered gate integrated circuits (30_1, 30_3, ..., 30_m-1), and the second gate driver 14b includes even-numbered gate integrated circuits (30_1, 30_3, ..., 30_m-1). 30_2, 30_4, ..., 30_m). However, the structure of the gate drivers 14a and 14b is not limited to this and may vary depending on the embodiment.

A sensing clock signal SENCLK may be input to each of the gate integrated circuits 30_1 to 30_m included in the dual gate type gate drivers 14a and 14b shown in FIG. 4 . As described above, the sensing clock signal SENCLK may be simultaneously input to each gate integrated circuit 30_1 to 30_m in the sensing period when the display device 1 is driven in the sensing mode. When the sensing clock signal SENCLK is simultaneously input to each gate integrated circuit 30_1 to 30_m, each gate integrated circuit 30_1 to 30_m simultaneously outputs the gate signal SCAN and the sensing signal SENSE.

FIG. 5 shows an operation section and waveforms of signals applied in each operation section when the display device according to an embodiment of the present specification is driven in a sensing mode. Below, the operation process of the display device according to an embodiment of the present specification will be described based on an embodiment in which the gate driver 14 is implemented in a single gate method as shown in FIG. 3.

Referring to FIG. 5, when the display device 1 is driven in the sensing mode, the operation section of the display device 1 is divided into an initialization section (Tini), a sensing section (Tsen), and a sampling section (Tsam).

In the initialization period Tini, initialization signals SPRE_1 to SPRE_m are sequentially applied to each first switch SW1 included in the sensing circuit SC of each pixel P. Additionally, scan signals SCAN_1 to SCAN_m are sequentially applied to each first switching transistor ST1 included in the pixel circuit PC of each pixel P. Accordingly, the first switch (SW1) of each pixel (P) is sequentially closed, the first switching transistor (ST1) is sequentially turned on, the first node (N1) is sequentially initialized with the data voltage (Vdata), and the sensing The capacitor Csen and the second node n2 are sequentially initialized to the reference voltage Vref.

Next, when the sensing period Tsen starts, the sensing clock signal SENCLK is simultaneously input to each gate integrated circuit 30_1 to 30_m of the gate driver 14. When the sensing clock signal SENCLK is input, each gate integrated circuit 30_1 to 30_m simultaneously outputs the gate signal SCAN and the sensing signal SENSE. Accordingly, the first switching transistor (ST1) and the second switching transistor (ST2) of all pixels (P) are turned on at the same time, and the voltage of the second node (n2) begins to rise. When the voltage of the second node n2 is saturated, the sensing voltage, which is a voltage reflecting the characteristic value (e.g., threshold voltage) of the driving transistor DT or its change, is simultaneously charged in the sensing capacitor Csen of each pixel P. do. Here, the sensing voltage may be the difference between the data voltage (Vdata) and the threshold voltage (Vth) or the difference between the data voltage (Vdata) and the threshold voltage deviation (ΔVth).

When the sensing section (Tsen) ends, the sampling section (Tsam) begins. When the sampling period Tsam starts, the sampling signals SAM_1 to SAM_m are sequentially applied to the second switch SW2 of each pixel P. Accordingly, the second switch SW2 is sequentially closed and the sensing voltage charged in the sensing capacitor Csen of each pixel P is sequentially sensed. The sensing voltage of each sensed pixel (P) is converted into sensing data (sd) through the analog-to-digital converter 124 and transmitted to the data driver 12.

The data driver 12 transmits the sensing data (sd) of each pixel (P) to the timing controller 16, and the timing controller 16 controls each pixel (P) based on the sensing data (sd) of each pixel (P). Compensation data of P) is generated to compensate for the deterioration of each pixel (P).

As explained through the embodiment of FIG. 5, when the display device 1 according to an embodiment of the present specification is driven in the sensing mode, the sensing capacitor Csen of each pixel P in the sensing section Tsen Control the sensing voltage to be charged simultaneously. Accordingly, the time required to perform the sensing section (Tsen), which takes the longest time in the sensing mode, is significantly reduced compared to the prior art, which has the effect of shortening the overall execution time of the sensing mode and the external compensation time based on the sensing mode.

Figure 6 is a flowchart showing a method of controlling a display device according to an embodiment of the present specification.

Referring to FIG. 6, when the display device 1 is driven in the sensing mode, the first switch SW1 of each pixel P is closed and the first switching transistor ST1 is turned on (602, initialization step). . In one embodiment of the present specification, the first switch (SW1) of each pixel (P) is sequentially closed, and the first switching transistor (ST1) of each pixel (P) is sequentially turned on. When the initialization step 602 is performed, the first node N1 of each pixel P is sequentially initialized to the data voltage Vdata, and the sensing capacitor Csen and the second node n2 are sequentially initialized to the reference voltage Vref. are initialized sequentially.

Next, the first switching transistor (ST1) and the second switching transistor (ST2) of each pixel are simultaneously turned on (604, sensing step). When the sensing step 604 is performed, the voltage of the second node n2 begins to rise, and when the voltage of the second node n2 is saturated, the characteristic value (e.g., threshold voltage) of the driving transistor DT or its change The sensing voltage, which is a voltage reflecting , is simultaneously charged in the sensing capacitor (Csen) of each pixel (P).

In one embodiment of the present specification, when the sensing step 604 starts, the sensing clock signal SENCLK is simultaneously input to each gate integrated circuit 30_1 to 30_m of the gate driver 14. When the sensing clock signal (SENCLK) is input, each gate integrated circuit (30_1 to 30_m) simultaneously supplies the gate signal (SCAN) and the sensing signal (SENSE) through the gate line (GL) and the sensing signal line (SL). .

Next, the second switching SW2 of each pixel P is closed (606, sampling step). In one embodiment of the present specification, the second switching SW2 of each pixel P is closed sequentially. When the sampling step 606 is performed, the second switch SW2 is sequentially closed and the sensing voltage charged in the sensing capacitor Csen of each pixel P is sequentially sensed. The sensing voltage of each sensed pixel (P) is converted into sensing data (sd) through the analog-to-digital converter 124 and transmitted to the data driver 12.

As described above, embodiments of the present specification have been described in more detail with reference to the attached drawings. However, the present specification is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present specification. Accordingly, the embodiments disclosed in this specification are not intended to limit the technical idea of the present specification, but rather to explain it, and the scope of the technical idea of the present specification is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of this specification should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of this specification.

Claims (12)

A driving transistor that supplies driving current to the organic light emitting diode, a first switching transistor that is turned on by a scan signal supplied through a gate line and supplies a data voltage supplied through a data line to the gate electrode of the driving transistor, and a sensing signal a pixel circuit including a second switching transistor that is turned on by a sensing signal supplied through a line and connects a second electrode of the driving transistor to a reference line;
A sensing capacitor connected to the reference line;
A sensing circuit including a first switch closed by an initialization signal to supply a reference voltage through the reference line and a second switch closed by a sampling signal to transfer the sensing voltage charged in the sensing capacitor to a data driver;
a data driver that supplies the data voltage through the data line and senses the sensing voltage charged in the sensing capacitor;
a gate driver that supplies the scan signal through the gate line and the sensing signal through the sensing signal line; and
A timing controller that controls driving of the data driver and the gate driver and generates compensation data based on the sensing voltage,
In the sensing section of the sensing mode, the sensing capacitors of all pixels are simultaneously charged with the sensing voltage,
The gate driver
When a sensing clock signal is input in the sensing section of the sensing mode, the scan signal and the sensing signal are simultaneously supplied to all pixels,
The first switching transistor and the second switching transistor of every pixel are:
Simultaneously turned on by each of the scan signal and the sensing signal
display device.
delete According to paragraph 1,
The gate driver
Comprising a plurality of gate integrated circuits connected to the gate line and the sensing signal line,
In the sensing section of the sensing mode, the sensing clock signal is simultaneously input to each gate integrated circuit.
display device.
According to paragraph 1,
In the initialization section of the sensing mode, the first switch of each pixel is sequentially closed and the first switching transistor of each pixel is sequentially turned on.
display device.
According to paragraph 1,
The second switch of each pixel is sequentially closed in the sampling section of the sensing mode.
display device.
According to paragraph 1,
The sensing circuit and the data driver are implemented as one integrated circuit.
display device.
A driving transistor that supplies driving current to the organic light emitting diode, a first switching transistor that is turned on by a scan signal supplied through a gate line and supplies a data voltage supplied through a data line to the gate electrode of the driving transistor, and a sensing signal A pixel circuit including a second switching transistor that is turned on by a sensing signal supplied through a line and connects the second electrode of the driving transistor and a reference line, a sensing capacitor connected to the reference line, and closed by an initialization signal. A sensing circuit including a first switch that supplies a reference voltage through a reference line and a second switch that is closed by a sampling signal and transmits the sensing voltage charged in the sensing capacitor to a data driver, and supplies the data voltage through the data line. A data driver that supplies and senses the sensing voltage charged in the sensing capacitor, a gate driver that supplies the scan signal through the gate line and supplies the sensing signal through the sensing signal line, and the data driver and the gate driver. A method of controlling a display device including a timing controller that controls driving and generates compensation data based on the sensing voltage,
An initialization step in which the first switch of each pixel is closed and the first switching transistor is turned on;
A sensing step in which the first switching transistor and the second switching transistor of each pixel are turned on simultaneously; and
A sampling step in which a second switch for each pixel is closed,
The sensing step is
When a sensing clock signal is input to the gate driver in the sensing section of the sensing mode, simultaneously supplying the scan signal and the sensing signal to all pixels,
The first switching transistor and the second switching transistor of all pixels are simultaneously turned on by each of the scan signal and the sensing signal.
Control method of display device.
delete In clause 7,
The gate driver
Comprising a plurality of gate integrated circuits connected to the gate line and the sensing signal line,
In the sensing step, the sensing clock signal is simultaneously input to each gate integrated circuit.
Control method of display device.
In clause 7,
In the initialization step, the first switch of each pixel is sequentially closed and the first switching transistor of each pixel is sequentially turned on.
Control method of display device.
In clause 7,
In the sampling step, the second switch of each pixel is sequentially closed.
Control method of display device.
In clause 7,
The sensing circuit and the data driver are implemented as a single integrated circuit.
Control method of display device.

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