KR102636379B1 - Three-dimensional memory device and method - Google Patents

Abstract

In one embodiment, the device includes a word line extending in a first direction; a data storage layer on the word line sidewall; a channel layer on the sidewall of the data storage layer; back gate isolation on sidewalls of the channel layer; and a bit line having a first main region in contact with the channel layer and a first extended region separated from the channel layer by the back gate isolator, and extending in a second direction perpendicular to the first direction. .

Description

Three-dimensional memory device and method {THREE-DIMENSIONAL MEMORY DEVICE AND METHOD}

[Priority Claims and Cross-References]

This application is a U.S. provisional application filed on July 30, 2020. No. 63/058,619, the entire contents of which are hereby incorporated by reference.

Semiconductor memories are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. There are two main categories of semiconductor memory. One is volatile memory and the other is non-volatile memory. Volatile memory includes random access memory (RAM), which can be further divided into two subcategories: static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM and DRAM are volatile because they lose the information they store when power is not supplied.

Meanwhile, non-volatile memory can retain stored data. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM). The advantages of FeRAM are fast write/read speeds and small size.

Aspects of the present disclosure are best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, for clarity of explanation, the sizes of various features may be arbitrarily enlarged or reduced.
Figures 1A, 1B and 1C are various diagrams of a memory array.
2-19C are various diagrams of intermediate steps in the fabrication of a memory array according to some embodiments.
20A-20J are diagrams of intermediate steps in the fabrication of staircase structures of a memory array according to some embodiments.
Figures 21A-21D are top views of a memory array according to some embodiments.
Figures 22A-22C are top views of a memory array according to some embodiments.
Figure 23 is a cross-sectional view of a memory array according to some embodiments.
Figure 24 is a cross-sectional view of a semiconductor device according to some embodiments.
25-27 are various diagrams of intermediate steps in the fabrication of a memory array according to some other embodiments.

The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. To simplify the disclosure, specific embodiments of components and arrangements are described below. Of course, these are just examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact; and Embodiments may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, the present disclosure may repeat reference numbers and/or letters in various embodiments. This repetition is for simplicity and clarity and does not by itself determine the relationships between the various embodiments and/or configurations discussed.

Additionally, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used in the drawing(s). As shown in , it may be used for convenience of explanation to explain the relationship of one element or feature to other element(s) or feature(s). The spatially relative terms are intended to include other orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may be otherwise oriented (rotated 90 degrees or in another direction) and the spatially relative descriptors used herein may be interpreted similarly accordingly.

According to various embodiments, a three-dimensional memory array is formed of transistors (eg, programmable thin film transistors (TFTs)) having source lines and bit lines provided with extension regions. The extended area serves as back gates. The data storage layer and channel layer of the transistor are disposed between the back gate for the transistor and the word line. During a write operation (e.g., erase or programming operation) on the transistor, the back gate may serve to control (e.g., reduce) the surface potential of the channel layer. Reducing the surface potential of the channel layer can improve the performance of the memory array.

1A, 1B, and 1C show an example of a memory array 50 according to some embodiments. 1A shows an embodiment of a portion of memory array 50 in three-dimensional view; Figure 1B shows a circuit diagram of memory array 50; Figure 1C shows a top view of a portion of memory array 50. The memory array 50 includes a plurality of memory cells 52, which may be arranged in a grid of rows and columns. Memory cells 52 can be further stacked vertically to increase device density by providing a three-dimensional memory array. The memory array 50 may be placed at the back end of line (BEOL) of a semiconductor die. For example, memory array 50 may be disposed in an interconnect layer of a semiconductor die, such as above one or more active devices (e.g., transistors) formed on the semiconductor substrate.

In some embodiments, memory array 50 is a memory array, such as a NOR memory array. Each memory cell 52 may include a transistor 54 (such as a TFT) with an insulating memory film 84 as a gate dielectric. In some embodiments, the gate of each transistor 54 is electrically coupled to a respective word line (e.g., conductive line 72) and the first source/drain of each transistor 54. The region is electrically coupled to each bit line (e.g., conductive line 64B), and the second source/drain region of each transistor 54 is connected to each source line (e.g., conductive line 64B). For example, conductive line 64S), which electrically couples the second source/drain region to ground. Memory cells 52 in the same horizontal row of memory array 50 may share a common word line, and memory cells 52 in the same vertical column of memory array 50 may share a common source line and a common bit line. You can share it.

The memory array 50 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines) and a dielectric layer 62 is disposed between adjacent ones of the conductive lines 72. Conductive lines 72 extend in a direction D ₁ parallel to the main surface of the underlying substrate (not explicitly shown in FIGS. 1A and 1B). Conductive line 72 may be a portion of the step structure such that lower conductive line 72 is longer than and extends laterally beyond the end point of upper conductive line 72. For example, as shown in Figure 1A, multiple stacked layers of conductive lines 72 are shown with the topmost conductive line 72 being the shortest and the bottommost conductive line 72 being the longest. The length of each conductive line 72 may increase in a direction toward the underlying substrate. In this manner, a portion of each conductive line 72 may be accessible from above the memory array 200 and a conductive contact 66 (see FIG. 1C ) may be placed on the exposed portion of each conductive line 72. can be formed. In embodiments where the memory array 50 is disposed in an interconnect layer of a semiconductor die, conductive contacts 66 may, for example, connect exposed portions of conductive lines 72 to interconnects 68 of the overlying interconnect layer (see Figure 1C). ) may be vias connecting to.

Memory array 50 further includes a plurality of conductive lines 64B (e.g., bit lines) and conductive lines 64S (e.g., source lines). The conductive lines 64B and 64S may each extend in a direction D ₃ perpendicular to the conductive line 72 . Isolation region 74 is disposed between and isolates adjacent ones of conductive lines 64B and 64S. Pairs of conductive lines 64B, 64S define the boundaries of each memory cell 52 with intersecting conductive lines 72, and an isolation region 76 is disposed between adjacent pairs of conductive lines 64B, 64S. and isolate them. In some embodiments, conductive line 64S is electrically coupled to ground. 1A illustrates a particular arrangement of conductive line 64B relative to conductive line 64S, it should be understood that in other embodiments the arrangement of conductive lines 64B and 64S may be reversed.

Memory array 50 may also include a semiconductor layer 82. Semiconductor layer 82 may provide a channel region for transistor 54 of memory cell 52. For example, when an appropriate voltage (e.g., a voltage higher than the respective threshold voltage (V _th ) of the corresponding transistor 54) is applied via the corresponding conductive line 72, the conduction The region of semiconductor layer 82 that intersects line 72 may allow current to flow from conductive line 64B to conductive line 64S (e.g., in the direction indicated by arrow 56).

Memory film 84 is disposed between conductive line 72 and semiconductor layer 82, and memory film 84 may provide a gate dielectric for transistor 54. In some embodiments, memory film 84 includes a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, etc. Accordingly, the memory array 50 may also be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the memory film 84 may include one silicon nitride layer between two silicon oxide layers (e.g., an oxide-nitride-oxide (ONO) structure), a different ferroelectric material, a different type of memory layer (e.g. For example, it may be a multi-layer structure including bits).

In embodiments where the memory film 84 includes a ferroelectric material, the memory film 84 may be polarized in one of two different directions, with the polarization direction being determined by an appropriate voltage differential across the memory film 84. It can be changed by applying a differential to create an appropriate electric field. The polarization may be relatively localized (e.g., generally contained within each boundary of memory cells 52), and a continuous region of memory film 84 may extend across a plurality of memory cells 52. there is. Depending on the polarization direction of a specific region of the memory film 84, the threshold voltage of the corresponding transistor 54 changes, and a digital value (eg, 0 or 1) may be stored. For example, when one region of the memory film 84 has a first electrical polarization direction, the corresponding transistor 54 may have a relatively low threshold voltage, and the corresponding transistor 54 may have a relatively low threshold voltage of the memory film 84. When the region has a second electrical polarization direction, the corresponding transistor 54 may have a relatively high threshold voltage. The difference between two threshold voltages may be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less error-prone) to read the digital value stored in the corresponding memory cell 52.

To perform a write operation on memory cell 52 in this embodiment, a write voltage is applied over a portion of memory film 84 corresponding to memory cell 52. The write voltage is applied, for example, by applying an appropriate voltage to the corresponding conductive line 72 (e.g., word line) and the corresponding conductive line 64B, 64S (e.g., bit line/source line). It can be. By applying a write voltage across this portion of memory film 84, the polarization direction of this region of memory film 84 can be changed. As a result, the corresponding threshold voltage of the corresponding transistor 54 can be switched from a low threshold voltage to a high threshold voltage or vice versa, and a digital value can be stored in the memory cell 52. Because conductive line 72 intersects conductive lines 64B and 64S, individual memory cells 52 may be selected for a write operation.

To perform a read operation on memory cell 52 in this embodiment, a read voltage (a voltage between a low threshold voltage and a high threshold voltage) is connected to the corresponding conductive line 72 (e.g., a word line). Depending on the polarization direction of the corresponding region of memory film 84, transistor 54 of memory cell 52 may or may not be turned on. As a result, conductive line 64B may or may not discharge through conductive line 64S (e.g., a source line coupled to ground), and the digital value stored in memory cell 52 may be determined. Because conductive line 72 intersects conductive lines 64B and 64S, individual memory cells 52 may be selected for a read operation.

Figure 1A further shows reference cross-sections of memory array 50 used in subsequent figures. The reference cross section B-B' lies along the longitudinal axis of the conductive line 72 and parallel to the direction D ₁ , for example the direction of current flow in the transistor 54 . Section C-C' is perpendicular to section B-B' and is perpendicular to the direction D ₂ , for example the longitudinal axis of the conductive line 72 . The subsequent drawings refer to these reference sections for clarity.

2-19C are diagrams of intermediate steps in the fabrication of memory array 50 according to some embodiments. Each memory cell 52 of memory array 50 includes a transistor 54 (see FIGS. 19B and 19C). Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 and 19a are three-dimensional drawings. FIG. 19B is a cross-sectional view taken along reference cross section B-B' of FIG. 1A. FIG. 19C is a cross-sectional view taken along reference cross-section C-C' of FIG. 1A. A portion of memory array 50 is shown. Some features, such as the staircase arrangement of word lines (see Figure 1A), are not shown in some figures for clarity of explanation.

In Figure 2, a substrate 102 is provided. Substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, semiconductor-on-insulator (SOI) substrate, etc., and may be doped (e.g., with a p-type or n-type dopant) or doped. It may not work. Substrate 102 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as multi-layered or gradient substrates may also be used. In some embodiments, the semiconductor material of substrate 102 is silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; mixed crystal semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and/or gallium indium arsenide phosphide; Or it may include a combination thereof. Substrate 102 may include dielectric material. For example, substrate 102 may be a dielectric layer or may include a dielectric layer on a semiconductor substrate. Acceptable dielectric materials for substrate 102 include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; etc; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, etc. In some embodiments, substrate 102 is formed of silicon carbide.

A multilayer stack 104 is formed over substrate 102 . Multilayer stack 104 includes alternating dielectric layers 106 and sacrificial layers 108. The dielectric layer 106 is formed of a first dielectric material, and the sacrificial layer 108 is formed of a second dielectric material. The dielectric material may each be selected from candidate dielectric materials for substrate 102. Multilayer stack 104 will be patterned in subsequent processing. Accordingly, the dielectric materials of dielectric layer 106 and sacrificial layer 108 both have high etching selectivity from etching of substrate 102 material. Patterned dielectric layer 106 will be used to isolate subsequently formed transistors. The patterned sacrificial layer 108 may also be referred to as a dummy layer and will optionally be replaced with a word line for the transistor in subsequent processing. Accordingly, the second dielectric material of sacrificial layer 108 also has a high etch selectivity from etching the first dielectric material of dielectric layer 106. In embodiments where substrate 102 is formed of silicon carbide, dielectric layer 106 may be formed of silicon oxide and sacrificial layer 108 may be formed of silicon nitride. Other combinations of dielectric materials with mutually acceptable etch selectivity may also be used.

Each layer of multilayer stack 104 may be formed by any acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The thickness of each layer may range from about 40 nm to about 50 nm. In some embodiments, dielectric layer 106 is formed at a different thickness than sacrificial layer 108. For example, the sacrificial layer 108 may be formed to be thicker than the dielectric layer 106. In the depicted embodiment, multilayer stack 104 includes five dielectric layers 106 and four sacrificial layers 108. It will be appreciated that the multilayer stack 104 may include different quantities of dielectric layers 106 and sacrificial layers 108. Multilayer stack 104 may have an overall height H ₁ ranging from about 1000 nm to about 10000 nm.

As discussed in more detail below, Figures 3-10 illustrate a process in which a multi-patterning process is used to form some features of a transistor. The multi-patterning process may be a double patterning process, a quadruple patterning process, etc. 3-10 illustrate a double patterning process. In a double patterning process, trenches 110A (see Figure 3) are patterned in a portion of multilayer stack 104 with a first etch process, and features for a first subset of transistors are formed in trenches 110A. . Trench 110B (see FIG. 7) is then patterned in another portion of multilayer stack 104 with a second etch process, and features for a second subset of transistors are formed in trench 110B. Forming the features of the transistor with a multi-patterning process allows each patterning process to be performed at a low pattern density, which can help reduce defects while still allowing the memory array 50 to have sufficient memory cell density. there is. Additionally, forming the transistor features with a multi-patterning process can prevent each patterned portion of the multilayer stack 104 from having an excessively large aspect ratio, thereby improving the structural stability of the resulting memory array. I do it. As discussed in more detail below (see FIGS. 25-27), a single patterning process may be used to form some features of the transistor.

In Figure 3, trenches 110A are patterned in multilayer stack 104. In the illustrated embodiment, trench 110A extends through multilayer stack 104 and exposes substrate 102. In another embodiment, trench 110A extends through some but not all layers of multilayer stack 104. Trench 110A may be formed by an acceptable photolithography and etching process, e.g., selective for multilayer stack 104 (e.g., by removing the dielectric material of dielectric layer 106 and sacrificial layer 108 over the material of substrate 102). They can be patterned using etching techniques such as selective removal at high speeds. The etching may be any acceptable etching process such as reactive ion etch (RIE), neutral beam etch (NBE), etc., or a combination thereof. The etching may be anisotropic. In embodiments in which substrate 102 is formed of silicon carbide, dielectric layer 106 is formed of silicon oxide, and sacrificial layer 108 is formed of silicon nitride, trench 110A is formed of hydrogen (H ₂ ) or oxygen ( It can be formed by dry etching using a fluorine-based gas (eg, C ₄ F ₆ ) mixed with O ₂ ) gas. After patterning, each portion of multilayer stack 104 is placed between respective trenches 110A. Each portion of the multilayer stack 104 has a width W ₁ in the second direction D ₂ (see FIGS. 1A and 1B), which may range from about 50 nm to about 500 nm. Additionally, each portion of the multilayer stack 104 is separated by a separation distance S ₁ in the second direction D ₂ , which may range from about 50 nm to about 200 nm.

In Figure 4, trench 110A is expanded to form sidewall recess 112A. Specifically, the sidewall portion of the sacrificial layer 108 exposed by the trench 110A is recessed from the sidewall portion of the dielectric layer 106 exposed by the trench 110A to form the sidewall recess 112A. Although the sidewalls of sacrificial layer 108 are shown as being straight, the sidewalls may be concave or convex. Sidewall recess 112A is selective to the material of sacrificial layer 108 (e.g., moves the material of sacrificial layer 108 at a faster rate than the material(s) of dielectric layer 106 and substrate 102. can be formed by an acceptable etching process, such as selective removal). The etching may be isotropic. In an embodiment in which substrate 102 is formed of silicon carbide, dielectric layer 106 is formed of silicon oxide, and sacrificial layer 108 is formed of silicon nitride, trench 110A is formed of phosphoric acid (H ₃ PO ₄ ). It can be expanded by using wet etching. In other embodiments, selective dry etching of the material of sacrificial layer 108 may be used.

After formation, sidewall recess 112A has a depth D ₄ in the second direction D ₂ (see FIGS. 1A and 1B ) and extends past the sidewall of dielectric layer 106 . A timed etch process may be used to stop etching of sidewall recess 112A after sidewall recess 112A reaches a desired depth D ₄ . For example, sidewall recess 112A may have a depth D ₄ ranging from about 10 nm to about 60 nm. Forming sidewall recess 112A may reduce the width of sacrificial layer 108 by about 5% to about 25%. Continuing with the previous embodiment, after etching, the sacrificial layer 108 may have a width W ₂ in the second direction D ₂ , which may range from about 50 nm to about 450 nm.

5, a conductive feature 114A (e.g., a metal line) is formed in sidewall recess 112A, completing the process to replace the first portion of sacrificial layer 108. Each conductive feature 114A may include one or more layers, such as a seed layer, glue layer, barrier layer, diffusion layer, fill layer, etc. In some embodiments, conductive features 114A include seed layer 114A _S (or barrier layer) and main layer 114A _M , respectively. Each seed layer 114A _S extends along three sides (eg, top surface, side wall, and bottom surface) of a corresponding main layer 114A _M located within a corresponding sidewall recess 112A. The seed layer 114A _S is a first conductive material that can be used to aid the growth or adhesion of a subsequently deposited material, such as a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, etc. is formed by The main layer 114A _M may be formed of a second conductive material, such as a metal such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, and alloys thereof. The material of the seed layer 114A _S is a material having good adhesion to the material of the dielectric layer 106, and the material of the main layer 114A _M is a material having good adhesion to the material of the seed layer 114A _S. am. In embodiments where dielectric layer 106 is formed of an oxide, such as silicon oxide, seed layer 114A _S may be formed of titanium nitride or tantalum nitride, and main layer 114A _M may be formed of tungsten. The materials of seed layer 114A _S and main layer 114A _M may be formed by any acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. An acceptable etch process, such as dry etch (e.g., reactive ion etch (RIE), neutral beam etch (NBE), etc.), wet etch, etc., or a combination thereof, may be used to form the dielectric layer 106. This may be performed to remove excess material from the sidewalls and top surface of the substrate 102. The etching may be anisotropic. Each conductive feature 114A may have an overall thickness similar to sacrificial layer 108 (described above with respect to FIG. 2) and an overall width similar to the depth D ₄ of sidewall recess 112A. (described above for Figure 4). Each seed layer 114A _S may have a thickness ranging from about 1 nm to about 10 nm, and each main layer 114A _M may have a thickness ranging from about 15 nm to about 35 nm, and the seed layer The thickness of (114A _S ) is smaller than the thickness of the main layer (114A _M ).

In Figure 6, memory film 116A, semiconductor layer 118A, back gate isolators 120A, and isolation region 122A are formed in trench 110A. Semiconductor layer 118A and back gate isolator 120A are formed over memory film 116A. Isolation region 122A extends through semiconductor layer 118A, separating semiconductor layers 118A of horizontally adjacent transistors along direction D ₂ (see FIGS. 1A and 1B). In the depicted embodiment, isolation region 122A is formed over memory film 116A. In another embodiment, isolation region 122A also extends through memory film 116A and substrate 102 to separate memory films 116A of horizontally adjacent transistors along direction D ₂ .

Portions of memory film 116A provide a data storage layer for the transistor and portions of semiconductor layer 118A provide a channel region for the transistor. As described in more detail below, back gate isolation 120A will be patterned and used to facilitate forming the T-shaped source/drain regions of the transistor. The T-type source/drain area has a main area and an extended area. Back gate isolator 120A is patterned such that the main source/drain region is in contact with semiconductor layer 118A, but the source/drain extension region is separate from the portion of semiconductor layer 118A that provides the channel region. Prevents shorting. The source/drain extension regions serve to control (e.g., reduce) the surface potential of the semiconductor layer 118 (particularly the portion of the semiconductor layer 118 distal to the word line 114) during a write operation. It can act as a back gate. Therefore, the window for writing operations can be widened.

Memory film 116A is formed of a material acceptable for storing digital values. In some embodiments, memory film 116A is made of hafnium zirconium oxide (HfZrO); zirconium oxide (ZrO); Hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), aluminum (Al), etc.; Undoped hafnium oxide (HfO); It is formed of high-k ferroelectric materials such as others. In some embodiments, memory film 116A includes one or more low-k dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. The material of memory film 116A may be formed by any acceptable deposition process such as ALD, CVD, physical vapor deposition (PVD), etc. In some embodiments, memory film 116A is formed from HfZrO deposited by ALD.

The semiconductor layer 118A is made of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), and zinc oxide (ZnO). , formed of an acceptable material to provide a channel region for a transistor, such as polysilicon, amorphous silicon, etc. The material of semiconductor layer 118A may be formed by any acceptable deposition process such as ALD, CVD, PVD, etc. In some embodiments, semiconductor layer 118A is formed from IGZTO deposited by ALD.

Back gate isolation 120A is formed of an acceptable material to electrically isolate the subsequently formed source/drain extension region from the portion of semiconductor layer 118A that provides the channel region. In some embodiments, back gate isolation 120A is formed of a dielectric material. Acceptable dielectric materials for back gate isolation 120A include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; etc; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, etc. The material of back gate isolation 120A may be formed by any acceptable deposition process such as ALD, CVD, flowable CVD (FCVD), etc. In some embodiments, back gate isolation 120A is formed of an oxide, such as aluminum oxide, deposited by ALD.

Isolation area 122A is formed of an acceptable material to protect and electrically insulate the underlying memory film 116A. Allowable dielectric materials for isolation region 122A include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; etc; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, etc. The material of isolation region 122 may be formed by any acceptable deposition process such as ALD, CVD, flowable CVD (FCVD), etc. Isolation region 122A and back gate isolation 120A are formed of different dielectric materials such that the material of isolation region 122A has a high etch selectivity from etching of back gate isolation 120A material. In some embodiments, isolation region 122A is formed of an oxide, such as silicon oxide deposited by FCVD.

Memory film 116A, semiconductor layer 118A, back gate isolator 120A, and isolation region 122A may be formed by a combination of deposition, etching, and planarization. For example, a tunneling layer is deposited conformally on multilayer stack 104 and within trench 110A (e.g., on the sidewalls of conductive feature 114A and the sidewalls of dielectric layer 106). . A semiconductor layer can then be conformally deposited on the tunneling layer. A dielectric layer can then be conformally deposited on the semiconductor layer. The dielectric layer can then be patterned by a suitable etch process, such as an anisotropic etch using the tunneling layer as an etch stop layer. The semiconductor layer can then be patterned by a suitable etch process, such as an anisotropic etch using the patterned dielectric layer as an etch mask. An insulating material may then be conformally deposited over the remaining portion of trench 110A (eg, over exposed portions of the patterned semiconductor layer, patterned dielectric layer, and tunneling layer). A removal process is then applied to the various layers to remove excess material above the top dielectric layer 106/sacrificial layer 108. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch-back, a combination thereof, etc. The portions of the tunneling layer, semiconductor layer, dielectric layer, and insulating material remaining in trench 110A form memory film 116A, semiconductor layer 118A, back gate isolator 120A, and isolation region 122A, respectively. The planarization process is such that the upper surfaces of memory film 116A, semiconductor layer 118A, back gate isolation 120A, isolation region 122A, and top dielectric layer 106/sacrificial layer 108 are formed after the planarization process (process variation). The top dielectric layer 106/sacrificial layer 108 is exposed so that it is coplanar (within the dielectric layer).

Optionally, isolation region 122A may also be formed to extend through memory film 116A and substrate 102. As described in more detail below, in some embodiments, memory array 50 is embedded in another semiconductor device. Specifically, the memory array 50 may be formed in an interconnect structure of a semiconductor device. In this embodiment, an opening may be formed through memory film 116A and substrate 102 prior to depositing the insulating material of isolation region 122A. Portions of isolation region 122A are subsequently replaced with the source/drain regions of the transistor, connecting the source/drain regions to the metallization layer of the interconnect structure underlying memory array 50. A suitable etch process may be performed on memory film 116A and substrate 102 using semiconductor layer 118A and back gate isolation 120A as an etch mask. The etch process is selective to the memory film 116A and the substrate 102 (e.g., to remove the material(s) of the memory film 116A and the substrate 102 from the semiconductor layer 118A and the back gate isolation 120A. ) is selectively removed at a faster rate than the substances in ). The etching may be anisotropic. In some embodiments, the etching process includes multiple etches. For example, a first etch may be performed to extend the opening through memory film 116A and a second etch may be performed to extend the opening through substrate 102. After the opening is formed, isolation area 122A may be formed in a similar manner as described above.

In Figure 7, trenches 110B are patterned in multilayer stack 104. In the illustrated embodiment, trench 110B extends through multilayer stack 104 and exposes substrate 102. In another embodiment, trench 110B extends through some but not all layers of multilayer stack 104. Trench 110B is subjected to an etch process that is selective to multilayer stack 104 (e.g., selectively removes dielectric material in dielectric layer 106 and sacrificial layer 108 at a faster rate than material in substrate 102). It can be patterned using acceptable photolithography and etching techniques, such as using . The etch may be any acceptable etch process, and in some embodiments may be similar to the etch used to form trench 110A (discussed above with respect to FIG. 3).

After patterning, each portion of multilayer stack 104 is placed between each pair of trenches 110A and 110B. Each portion of the multilayer stack 104 has a width W ₃ in the second direction D ₂ (see FIGS. 1A and 1B), which may range from about 50 nm to about 500 nm. Additionally, each portion of the multilayer stack 104 is spaced apart by a distance S ₂ in the second direction D ₂ , which may range from about 50 nm to about 200 nm. Misalignment may occur when patterning the trench 110B. If misalignment occurs, the patterned portions of the multilayer stack 104 do not all have the same width W ₃ . If misalignment does not occur, the patterned portion of the multilayer stack 104 has the same width W ₃ .

In Figure 8, trench 110B is expanded to form sidewall recess 112B. Specifically, the remaining portion of sacrificial layer 108 is removed to form sidewall recess 112B. Accordingly, sidewall recess 112B exposes the sidewall of conductive feature 114A (e.g., the sidewall of seed layer 114A _S ). Sidewall recess 112B may be formed by an acceptable etch process, such as one that is selective to the material of sacrificial layer 108 (e.g., selectively etching the material of sacrificial layer 108 to dielectric layer 106 and substrate ( Selectively removed at a faster rate than the substance(s) of 102). The etching may be any acceptable etching process, and in some embodiments may be similar to the etching used to form sidewall recess 112A (discussed above with respect to FIG. 4).

After formation, sidewall recess 112B extends past the sidewall of dielectric layer 106 with depth D ₅ in second direction D ₂ (see FIGS. 1A and 1B). A timed etch process may be used to stop etching of sidewall recess 112B after sidewall recess 112B reaches a desired depth D ₅ . As mentioned above, misalignment may occur when patterning trench 110B. When misalignment occurs the depth D ₅ is different (eg, larger or smaller) than the depth D ₄ (described above with respect to FIG. 4 ). If no misalignment occurs, depth D ₅ is similar to depth D ₄ .

9, conductive features 114B are formed in sidewall recess 112B, completing the process to replace the second portion of sacrificial layer 108. Conductive feature 114B may be formed from a material selected from the same group of candidate materials for conductive feature 114A, which may be formed using a method selected from the same group of candidate methods for forming the material of conductive feature 114A. there is. Conductive features 114A and conductive features 114B may be formed from the same material or may include different materials. In some embodiments, conductive features 114B include seed layer 114B _S (or barrier layer) and main layer 114B _M , respectively. The seed layer 114B _S and the main layer 114B _M may have thicknesses similar to those of the seed layer 114A _S and the main layer 114A _M , respectively. In some embodiments, seed layer 114A _S and seed layer 114B _S are formed of similar materials, in which case seed layer 114A _S and seed layer 114B _S are merged during formation with no distinguishable material between them. The interface may not exist. In other embodiments, the seed layer 114A _S and the seed layer 114B _S are formed of different materials, in which case the seed layer 114A _S and the seed layer 114B _S are not merged during formation so that there is no distinction between them. Possible interfaces may exist. As previously discussed, misalignment may occur when patterning trench 110B. When misalignment occurs, the main layer 114A _M has a different width from the main layer 114B _M along the second direction D ₂ (see FIGS. 1A and 1B). When misalignment does not occur, the main layer 114A _M has the same width as the main layer 114B _M along the second direction D ₂ . Portions of each seed layer 114A _S , 114B _S are laterally disposed between the main layer 114A _M and the main layer 114B _M.

Conductive features 114A and conductive features 114B are collectively referred to as word lines 114 of memory array 50. Adjacent pairs of conductive features 114A and 114B are in physical contact with each other and electrically coupled to each other. Accordingly, each pair of conductive features 114A, 114B functions as a single word line 114.

In Figure 10, memory film 116B, semiconductor layer 118B, back gate isolator 120B, and isolation region 122B are formed in trench 110B. Semiconductor layer 118B and back gate isolator 120B are formed over memory film 116B. Isolation region 122B extends through semiconductor layer 118B, separating the semiconductor layers 118B of horizontally adjacent transistors along direction D ₂ (see FIGS. 1A and 1B). In the illustrated embodiment, isolation region 122B is formed over memory film 116B. In another embodiment, isolation region 122B also extends through memory film 116B and substrate 102 to separate memory films 116B of horizontally adjacent transistors along direction D ₂ .

Memory film 116B may be formed from a material selected from the same group of candidate materials for memory film 116A, and may be formed using a method selected from the same group of candidate methods for forming materials for memory film 116A. . Memory film 116A and memory film 116B may be formed of the same material or may include different materials. Memory film 116A and memory film 116B are collectively referred to as memory film 116. The thickness of memory film 116 may range from about 2 nm to about 20 nm.

Semiconductor layer 118B may be formed of a material selected from the same group of candidate materials for semiconductor layer 118A, and may be formed using a method selected from the same group of candidate methods for forming materials of semiconductor layer 118A. . Semiconductor layer 118A and semiconductor layer 118B may be formed of the same material or may include different materials. Semiconductor layer 118A and semiconductor layer 118B are collectively referred to as semiconductor layer 118. The thickness of semiconductor layer 118 may range from about 9 nm to about 11 nm.

Back gate isolator 120B may be formed from a material selected from the same group of candidate materials as back gate isolator 120A, which may be formed from a method selected from the same group of candidate methods for forming the material of back gate isolator 120A. It can be formed using . Back gate isolation 120A and back gate isolation 120B may be formed of the same material or may include different materials. Back gate isolation 120a and back gate isolation 120B are collectively referred to as back gate isolation 120. The thickness of back gate isolation 120 may range from about 1 nm to about 20 nm.

Isolation region 122B may be formed from a material selected from the same group of candidate materials as isolation region 122A, which may be formed using a method selected from the same group of candidate methods for forming materials of isolation region 122A. there is. Isolation region 122A and isolation region 122B may be formed of the same material or may include different materials. Isolation region 122B and back gate isolation 120B are formed of different dielectric materials such that the material of isolation region 122B has a high etch selectivity from etching of back gate isolation 120B material. Isolation area 122A and isolation area 122B are collectively referred to as isolation area 122. The thickness of isolation region 122 may range from about 42 nm to about 192 nm.

Memory film 116B, semiconductor layer 118B, back gate isolator 120B, and isolation region 122B may be formed by a combination of deposition, etching, and planarization. For example, memory film 116B, semiconductor layer 118B, back gate isolator 120B, and isolation region 122B may include memory film 116A, semiconductor layer 118A, back gate isolator 120A, and It may be formed by steps similar to those used to form isolation region 122A (described above with respect to FIG. 6).

As described in more detail below, Figures 11-18 illustrate the process by which portions of isolation region 122 are replaced with the remaining features of the transistor. Specifically, portions of isolation region 122 are replaced with isolation region 142 (see Figure 16) and bit line 146B and source line 146S (see Figure 18). The remaining portions of isolation region 122 separate features of horizontally adjacent transistors along direction D ₁ (see FIGS. 1A and 1B). Bit line 146B and source line 146S also serve as source/drain regions of the transistor. During the process of replacing the portions of isolation region 122, back gate isolation 120 is patterned. Patterned back gate isolation 120 allows portions of bit line 146B/source line 146S to also act as back gates during write operations.

11, portions of isolation area 122 are removed to form opening 130. Aperture 130 is capable of performing an etch process selective to isolation region 122 (e.g., selectively removing material of isolation region 122 at a faster rate than material of memory film 116 and back gate isolation 120). can be formed as (removed). The etching may be any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. In embodiments where isolation region 122 is formed of silicon oxide, openings 130 may be formed through isolation region 122 by dry etching using ammonia (NH ₃ ) and hydrogen fluoride (HF) gas; This can be done using an etch mask with a pattern of openings 130.

12, a sacrificial region 132 is formed within the opening 130. The sacrificial region 132 is formed of a sacrificial material, such as a dielectric material, which will be replaced by the bit line and source line in subsequent processing. Accordingly, the dielectric material of sacrificial region 132 has a high etch selectivity from etch of memory film 116, semiconductor layer 118, and back gate isolation 120 material. Acceptable dielectric materials for sacrificial region 132 include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; etc; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, etc. The material of sacrificial region 132 may be formed by any acceptable deposition process such as ALD, CVD, flowable CVD (FCVD), etc. In some embodiments, sacrificial region 132 is formed of a nitride, such as silicon nitride deposited by CVD. To remove excess material above top dielectric layer 106/sacrificial layer 108, a removal process may be applied to the material of sacrificial region 132. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch-back, a combination thereof, etc. The planarization process exposes the top dielectric layer 106/sacrificial layer 108 such that the top surfaces of the sacrificial region 132 and the top dielectric layer 106/sacrificial layer 108 are coplanar (within process variations) after the planarization process. I order it.

13, back gate isolator 120 and sacrificial region 132 are patterned to form openings 136. Openings 136 may be formed with an etch process selective to the back gate isolator 120 and sacrificial region 132 (e.g., greater than the material of semiconductor layer 118 and/or memory film 116). Selectively removes material from the back gate isolator 120 and sacrificial area 132 at high rates). The etching may be any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. In embodiments in which the back gate isolation 120 is formed of aluminum oxide and the sacrificial region 132 is formed of silicon nitride, the opening 136 is formed of a fluorine-based gas mixed with hydrogen (H ₂ ) or oxygen (O ₂ ) gas. (e.g., C ₄ F ₆ ) may be formed through the back gate isolation 120 and sacrificial region 132 by dry etching using an etch mask with a pattern of openings 136. It can be done using

In FIG. 14 , additional material of sacrificial region 132 is redeposited in opening 136 to reform sacrificial region 132 . Accordingly, each sacrificial area 132 has a first part 132A and a second part 132B. As described above, the sacrificial area 132 will be replaced by a bit line and source line in subsequent processing, and the bit line/source line will have a main area and an extended area. The first portion 132A of sacrificial region 132 corresponds to the portion of sacrificial material that was not removed when forming opening 136 and will be replaced with an extended region of the bit line/source line. The second portion 132B of sacrificial region 132 corresponds to the portion of sacrificial material redeposited in opening 136 and will be replaced with the main region of the bit line/source line. Portions 132A, 132B of sacrificial region 132 may merge during redeposition so that no discernible interface exists between them.

15, an opening 140 for an isolation area is formed through sacrificial area 132. Opening 140 divides sacrificial area 132 into portions that will be replaced by bit lines and source lines in subsequent processing. Openings 140 may be formed in an etch process selective to sacrificial region 132 (e.g., selectively removing material in sacrificial region 132 at a faster rate than material in memory film 116). . The etching may be any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. In embodiments where sacrificial region 132 is formed of silicon nitride, openings 140 are dry etched using a fluorine-based gas (e.g., C ₄ F ₆ ) mixed with hydrogen (H ₂ ) or oxygen (O ₂ ) gas. It can be formed through the sacrificial region 132 by , which is performed with an etching mask having a pattern of openings 140.

Semiconductor layer 118 is patterned during processing such that semiconductor layers 118 of horizontally adjacent transistors are divided along direction D ₁ (see FIGS. 1A and 1B). As described in more detail below, semiconductor layer 118 may be patterned at one of several stages during processing, depending on the desired width of the divided semiconductor layers 118. In this embodiment, semiconductor layers 118 are patterned simultaneously with patterning of sacrificial region 132/opening 140 (see Figure 15). In another embodiment, the semiconductor layers 118 are patterned simultaneously with the patterning of the back gate isolator 120/opening 136 (see FIG. 13). In another embodiment, the semiconductor layers 118 are formed after patterning of the back gate isolator 120/opening 136 (see Figure 13) but by redeposition of sacrificial region 132 material in the opening 136 (see Figure 13). 14) or in a separate step prior to the patterning of the sacrificial region 132/opening 140 (see FIG. 15). When they are individually patterned, the semiconductor layers 118 are It may be patterned with a selective etch process (e.g., selectively removing material of semiconductor layer 118 at a faster rate than material of memory film 116). The etching may be any acceptable etching process such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. In embodiments where semiconductor layer 118 is formed of IGZTO, semiconductor layer 118 may be patterned by dry etching using Cl ₂ , BCl ₃ , CF ₄ , SF ₆ , etc.

16, an isolation region 142 is formed in the opening 140. Accordingly, the isolation area 142 extends through the sacrificial area 132. Isolation region 142 may be formed from a material selected from the same group of candidate materials for isolation region 122, which may be formed using a method selected from the same group of candidate methods for forming isolation region 122 materials. . Isolation region 122 and isolation region 142 may be formed of the same material or may include different materials. In some embodiments, isolation region 142 is formed from silicon oxide deposited by CVD. In an embodiment for forming the isolation region 142 , an insulating material is formed in the opening 140 . A removal process is then applied to the various layers to remove excess insulating material above the top dielectric layer 106/word line 114. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch-back, combinations thereof, etc. The remaining insulating material forms an isolation region 142 in the opening 140 .

17, sacrificial area 132 is removed to form opening 144. Openings 144 may be formed in an etch process selective to sacrificial region 132 (e.g., removing material from sacrificial region 132 to isolation region 142, back gate isolation 120, and isolation region 142). (122), which is selectively removed at a faster rate than the material of the semiconductor layer 118 and the memory film 116). The etching may be isotropic. In embodiments where sacrificial region 132 is formed of silicon nitride, opening 144 may be formed by wet etching using phosphoric acid (H ₃ PO ₄ ). In other embodiments, selective dry etching of the material of sacrificial region 132 may be used.

18, conductive lines (including bit line 146B and source line 146S) are formed in opening 144. Bit line 146B and source line 146S are conductive pillars and may also be referred to as bit line pillars and source line pillars. Each transistor includes a bit line 146B and a source line 146S, and an isolation region 122 is disposed between the bit line 146B and the source line 146S. In this embodiment, bit line 146B/source line 146S extends through semiconductor layer 118. In another embodiment, bit line 146B/source line 146S also extends through memory film 116 and substrate 102.

As an example for forming the bit line 146B/source line 146S, a liner such as a diffusion barrier layer, an adhesive layer, etc., and a main layer are formed in the opening 144. Liners can be formed from conductive materials such as titanium, titanium nitride, tantalum, tantalum nitride, etc. by conformal deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. may be deposited. In some embodiments, the liner can include an adhesive layer and at least a portion of the adhesive layer can be treated to form a diffusion barrier layer. The main layer may be formed of a conductive material such as tungsten, cobalt, ruthenium, aluminum, nickel, copper, copper alloy, silver, gold, etc., and may be deposited by ALD, CVD, PVD, etc. In some embodiments, bit line 146B/source line 146S includes a liner formed of titanium nitride and a main layer formed of tungsten. A removal process is then applied to the various layers to remove excess material(s) of bit line 146B/source line 146S above top dielectric layer 106/word line 114. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch-back, combinations thereof, etc. The remaining material(s) within opening 144 forms bit line 146B/source line 146S. The planarization process includes the bit line 146B/source line 146S, isolation region 142, isolation region 122, back gate isolation 120, semiconductor layer 118, memory film 116, and top dielectric layer ( The top dielectric layer 106/word line 114 is exposed such that the top surfaces of 106)/word line 114 are coplanar (within process variations) after the planarization process.

Bit line 146B/source line 146S each has a T-shaped cross-section in plan view. Specifically, bit line 146B has a main region 146B _M extending along a sidewall of semiconductor layer 118 and an extended region 146B _E extending along a sidewall of back gate isolation 120. . Similarly, source line 146S has a main region 146S _M extending along the sidewall of semiconductor layer 118 and an extended region 146S _E extending along the sidewall of back gate isolation 120. . The extended areas 146B _E and 146S _E and the isolation area 122 each have the same width in the second direction D ₂ (see FIGS. 1A and 1B). Patterned back gate isolator 120 allows main regions 146B _M , 146S _M to contact semiconductor layer 118, while extended regions 146B _E , 146S _E provide channel regions. ) and remain separated from the part of the part. Accordingly, the extension areas 146B _E and 146S _E can function as a back gate without shorting the channel area.

19A, 19B and 19C, an interconnect structure 160 is formed over the intermediate structure. Interconnect structure 160 may include, for example, a metallization pattern 162 in dielectric material 164 (not shown in FIG. 19A, see FIGS. 19B and 19C). Dielectric material 164 may include one or more dielectric layers, such as one or more layers of low-k (LK) or extra low-k (ELK) dielectric material. Metallization pattern 162 may be a metal interconnect (e.g., conductive line 162L, conductive via 162V, etc.) formed in dielectric material 164. Interconnect structure 160 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. Metallization pattern 162 of interconnect structure 160 is electrically connected to bit line 146B/source line 146S and interconnects transistors 54 to form functional memory.

As described above, the dielectric layer 106 and the word line 114 may be formed as a step structure. Dielectric layer 106 and word lines 114 may be patterned to form a step structure at any suitable step prior to formation of interconnect structure 160. Forming interconnect structure 160 includes forming conductive contacts connected to exposed portions of each word line 114 .

20A-20J are diagrams of intermediate steps in the fabrication of the staircase structure of memory array 50 according to some embodiments. FIGS. 20A to 20J are cross-sectional views taken along the reference cross-section B-B' shown in FIG. 1A. Some features of the transistor (see FIGS. 6-19C), such as memory film 116, semiconductor layer 118, back gate isolation 120, etc., are not shown for clarity of illustration. 20A-20J, multilayer stack 104 is patterned to form a staircase structure after sacrificial layer 108 is replaced with word lines 114. It should be understood that the depicted process may be performed in other suitable processing steps.

In Figure 20A, a mask 202 is formed over the multilayer stack 104. In this processing step, the multilayer stack 104 is comprised of alternating dielectric layers 204 (designated 204A, 204B, 204C, 204D) (such as dielectric layer 106 described above) and word lines 114 (described above). the same) and a conductive layer 206 (designated 206A, 206B, 206C). The mask 202 may be made of photoresist, etc., and may be formed by spin-on technology, etc.

In Figure 20B, mask 202 is patterned to expose multilayer stack 104 in area 210A and mask the remaining portion of multilayer stack 104. For example, the top layer of multilayer stack 104 (e.g., dielectric layer 204D) may be exposed in region 210A. Mask 202 may be patterned using any acceptable photolithography technique.

20C, the exposed portion of multilayer stack 104 in region 210A is etched using mask 202 as an etch mask. The etching may be any acceptable etching process such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. Etching may remove portions of dielectric layer 204D and conductive layer 206C in region 210A and define opening 212. Because dielectric layer 204D and conductive layer 206C have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, conductive layer 206C acts as an etch stop layer while etching dielectric layer 204D, and dielectric layer 204C acts as an etch stop layer while etching conductive layer 206C. As a result, portions of conductive layer 206C and dielectric layer 204D can be selectively removed without removing the remaining layers of multilayer stack 104, and opening 212 can be extended to a desired depth. Alternatively, a timed etch process can be used to stop etching of the opening 212 after the opening 212 has reached the desired depth. In the resulting structure, dielectric layer 204C is exposed in region 210A.

In Figure 20D, mask 202 is trimmed to expose additional portions of multilayer stack 104. Mask 202 may be trimmed using any acceptable photolithographic and/or etching technique. As a result of trimming, the width of mask 202 may be reduced and portions of multilayer stack 104 in region 210B may also be exposed. For example, the top surface of dielectric layer 204C may be exposed in area 210A and the top surface of dielectric layer 204D may be exposed in area 210B.

20E, dielectric layer 204D, conductive layer 206C, portions of dielectric layer 204C and conductive layer 206B in regions 210A, 210B are subjected to an acceptable etch process using mask 202 as an etch mask. is removed by The etching may be any acceptable etching process such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. Etching may extend opening 212 further into multilayer stack 104. Because the dielectric layers 204D/204C and conductive layers 206C/206B have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, conductive layer 206C acts as an etch stop layer while etching dielectric layer 204D; Dielectric layer 204C acts as an etch stop layer while etching conductive layer 206C; Conductive layer 206B acts as an etch stop layer while etching dielectric layer 204C; Dielectric layer 204B acts as an etch stop layer while etching conductive layer 206B. As a result, portions of dielectric layer 204D/204C and conductive layer 206C/206B can be selectively removed without removing the remaining layers of multilayer stack 104, and opening 212 can be expanded to a desired depth. there is. Additionally, during the etching process, the unetched portions of dielectric layer 204 and conductive layer 206 act as an etch mask for the underlying layers, resulting in dielectric layer 204D and conductive layer 206C (see Figure 20D). The previous pattern may be transferred to the lower dielectric layer 204C and conductive layer 206B. In the resulting structure, dielectric layer 204B is exposed in region 210A and dielectric layer 204C is exposed in region 210B.

In Figure 20F, mask 202 is trimmed to expose additional portions of multilayer stack 104. The photoresist can be trimmed using any acceptable photolithography technique. As a result of trimming, the width of mask 202 may be reduced and portions of multilayer stack 104 in region 210C may also be exposed. For example, the top surface of dielectric layer 204B may be exposed at area 210A; The top surface of dielectric layer 204C may be exposed in region 210B; The top surface of conductive layer 204D may be exposed at region 210C.

20G, portions of dielectric layers 204D, 204C, and 204B in regions 210A, 210B, and 210C are removed by an acceptable etch process using mask 202 as an etch mask. The etching may be any acceptable etching process such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. Etching may extend opening 212 further into multilayer stack 104. In some embodiments, conductive layer 206C acts as an etch stop layer while etching dielectric layer 204D; Conductive layer 206B acts as an etch stop layer while etching dielectric layer 204C; Conductive layer 206A acts as an etch stop layer while etching dielectric layer 204B. As a result, portions of dielectric layers 204D, 204C, and 204B can be selectively removed without removing the remaining layers of multilayer stack 104, and openings 212 can be expanded to a desired depth. Additionally, during the etching process, each conductive layer 206 acts as an etch mask for the underlying layers, such that the previous pattern of the conductive layer 206C/206B (see FIG. 20F) is similar to the underlying dielectric layer 204C/204B. ) can be transcribed as. In the resulting structure, conductive layer 206A is exposed in area 210A; Conductive layer 206B is exposed in region 210B; Conductive layer 206C is exposed in region 210C.

20H, mask 202 may be removed, for example, by an acceptable ashing or wet strip process. Accordingly, the staircase structure 214 is formed. The step structure includes a stack of alternating layers of dielectric layer 204 and conductive layer 206. The lower conductive layer 206 is wider and extends laterally past the upper conductive layer 206, with the width of each conductive layer 206 increasing in the direction toward the substrate 102. For example, conductive layer 206A can be longer than conductive layer 206B; Conductive layer 206B may be longer than conductive layer 206C. As a result, in subsequent processing steps conductive contacts can be formed with each conductive layer 206 from above the step structure 214 .

In Figure 20I, an inter-metal dielectric (IMD) 216 is deposited over the step structure 214. IMD 216 may be formed from a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials include phospho-silicate glass (PSG), boro-silicate glass (BSG), and boron-doped phospho-silicate glass (BPSG). , undoped silicate glass (USG), etc. Other insulating materials formed by acceptable processes may be used. IMD 216 extends along the sidewalls of dielectric layer 204 as well as the sidewalls of conductive layer 206. Additionally, IMD 216 may contact the top surface of each conductive layer 206.

As further shown in Figure 20I, a removal process is applied to IMD 216 to remove excess dielectric material over step structure 214. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc. may be used. The planarization process exposes the step structure 214 such that the top surfaces of the step structure 214 and IMD 216 are coplanar (within process variations) after the planarization process is complete.

In Figure 20J, portions of interconnect structure 160 are formed. For simplicity of illustration only one layer of interconnect structure 160 is shown. In this embodiment, forming interconnect structure 160 includes forming conductive contacts 166 via IMD 216. Conductive contacts 166 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. Conductive contacts 166 are connected to each conductive layer 206 (eg, word line 114 described above).

Figures 21A-21D are top views of memory array 50 according to some embodiments. Some features of the interconnect structure are shown. FIG. 21A shows a conductive via at a first level of an interconnect structure (e.g., first level conductive via 162V ₁ of FIGS. 19B and 19C). FIG. 21B shows a conductive line at a first level of the interconnect structure (e.g., first level conductive line 162L ₁ of FIGS. 19B and 19C). FIG. 21C shows a conductive via in a second level of an interconnect structure (e.g., second level conductive via 162V ₂ of FIGS. 19B and 19C). FIG. 21D shows a conductive line at a second level of the interconnect structure (e.g., second level conductive line 162L ₂ of FIGS. 19B and 19C).

Referring to Figure 21A, conductive via 162V ₁ is over and connected to bit line 146B/source line 146S. The bit lines 146B and source lines 146S are formed in an alternating pattern along the rows and columns of the memory array 50 in the plan view. Forming bit lines 146B and source lines 146S in an alternating pattern means that when word line 114 (see FIGS. 19B and 19C) is activated, adjacent bit lines 146B/source lines 146S ) helps prevent short circuit. In this embodiment, adjacent bit lines 146B and adjacent source lines 146S are laterally aligned with each other along first direction D ₁ (see FIGS. 1A and 1B). In some embodiments, the center of each conductive via 162V ₁ is laterally aligned with the center of each underlying bit line 146B/source line 146S.

Referring to FIG. 21B , conductive line 162L ₁ is over and connected to conductive via 162V ₁ . Conductive line 162L ₁ extends in first direction D ₁ (see FIGS. 1A and 1B) and laterally offsets the interconnection to the underlying bit line/source line. In other words, conductive lines 162L ₁ connected to bit lines 146B (see FIG. 21A) are connected to source lines 146S (see FIG. 21A) along second direction D ₂ (see FIGS. 1A and 1B). ) is laterally offset from the conductive lines 162L ₁ connected to ).

Referring to Figure 21C, conductive via 162V ₂ is over and connected to conductive line 162L ₁ . Because the conductive lines 162L ₁ laterally offset the interconnection to the underlying bit lines/source lines, the center of each conductive via 162V ₂ is therefore at the center of each underlying bit line/source line. Laterally offset from the center and the center of each underlying conductive via 162V ₁ . Conductive via 162V ₂ may be larger (eg, have a greater width) than conductive via 162V ₁ .

Referring to Figure 21D, conductive line 162L ₂ is over and connected to conductive via 162V ₂ . Conductive lines 162L ₂ include bit line interconnect 162B (which is connected to bit line 146B, see FIG. 21A) and source line interconnect 162S (which is connected to source line 146S, see FIG. 21A). do. Because conductive lines 162L ₁ (see FIG. 21C) laterally offset the interconnection to the underlying bit lines/source lines, bit line interconnect 162B and source line interconnect 162S are thus There may be straight conductive segments extending in two directions (D ₂ ) (see FIGS. 1A and 1B).

Figures 22A-22C are top views of memory cells according to various embodiments. Isolation region 122 may have a width W ₄ in the first direction D ₁ (see FIGS. 1A and 1B), which may range from about 1 nm to about 100 nm. Back gate isolator 120 may have a width W ₅ in the first direction D ₁ , which may range from about 1 nm to about 100 nm. In each illustrated embodiment, the width W ₅ is greater than the width W ₄ . The semiconductor layer 118 may have a width W ₆ in the first direction D ₁ , which may range from about 1 nm to about 100 nm.

Figure 22A shows an embodiment in which the semiconductor layer 118 is patterned concurrently with the patterning of the sacrificial region 132/opening 140 (see Figure 15). Therefore, the width W ₆ is greater than the width W ₅ . Additionally, width W ₆ may be equal to the combined width W ₇ of isolation region 122, source line 146S, and bit line 146B. In this embodiment, main regions 146B _M and 146S _M of bit line 146B/source line 146S are each separated from the sidewalls of memory film 116.

FIG. 22B shows semiconductor layer 118 after patterning of back gate isolator 120/opening 136 (see FIG. 13 ) but redeposition of material in sacrificial region 132 in opening 136 (see FIG. 14 ). ) or prior to patterning of the sacrificial region 132/aperture 140 (see FIG. 15 ), showing individually patterned embodiments. Therefore, the width W ₆ is greater than the width W ₅ . Additionally, width W ₆ is less than the combined width W ₇ of isolation region 122, source line 146S, and bit line 146B. In this embodiment, main regions 146B _M and 146S _M of bit line 146B/source line 146S contact a sidewall of memory film 116 and a plurality of sidewalls of semiconductor layer 118, respectively.

Figure 22C shows an embodiment in which the semiconductor layer 118 is patterned concurrently with the patterning of the back gate isolator 120/opening 136 (see Figure 13). Therefore, the width W ₆ is equal to the width W ₅ . Additionally, width W ₆ is less than the combined width W ₇ of isolation region 122, source line 146S, and bit line 146B. In this embodiment, main regions 146B _M and 146S _M of bit line 146B/source line 146S contact a single sidewall of semiconductor layer 118 and a sidewall of memory film 116, respectively.

Figure 23 is a cross-sectional view of a memory array 50 according to some other embodiments. Figure 23 is shown along a similar cross section to Figure 20b. In this embodiment, memory film 116 is formed from a plurality of low-k dielectric layers. Specifically, each memory film 116 includes a first sub-layer 116L ₁ , a second sub-layer 116L ₂ on the first sub-layer 116L 1 , and a third sub-layer 116L ₂ on the second sub-layer 116L ₂ . It includes a sub-layer (116L ₃ ). In some embodiments, first sub-layer 116L ₁ and third sub-layer 116L ₃ are formed of a first dielectric material (e.g., an oxide such as silicon oxide), and second sub-layer 116L ₂ is formed of a different second dielectric material (eg, a nitride such as silicon nitride). The low-k dielectric layer can allow the transistor to operate as a floating gate transistor.

In the embodiment described above with respect to FIGS. 2-23, memory array 50 is formed over substrate 102. In some embodiments, memory array 50 is formed as part of a stand-alone device (e.g., a memory die) that is integrated with another device (e.g., a logic die) through device packaging. In some embodiments, memory array 50 is embedded in another device, such as a logic die. In this embodiment, substrate 102 may be omitted, or may be an underlying layer, such as an underlying dielectric layer, an underlying semiconductor substrate, etc.

Figure 24 is a cross-sectional view of a semiconductor device 300 according to some embodiments. FIG. 24 is a cross-sectional view taken along reference cross-section B-B' of FIG. 1A. Figure 24 is a simplified drawing, and some features have been omitted for clarity of explanation. The semiconductor device 300 includes a logic area 300L and a memory area 300M. A memory device (eg, memory) is formed in the memory area 300M, and a logic device (eg, a logic circuit) is formed in the logic area 300L. For example, the memory array 50 (see FIG. 1) may be formed in the memory area 300M, and the logic device may be formed in the logic area 300L. The memory area 300M may be placed at the edge of the logic area 300L, or the logic area 300L may surround the memory area 300M.

The logic area 300L and the memory area 300M are formed on the same semiconductor substrate 302. Semiconductor substrate 302 may be silicon, doped or undoped, or may be an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 302 is made of germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide and/or indium antimonide; mixed crystal semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or other semiconductor materials such as combinations thereof. Other substrates such as multilayer or gradient substrates may also be used.

Device 304 is formed on the active surface of semiconductor substrate 302. Device 304 may be an active device or a passive device. For example, the electrical component may be a transistor, diode, capacitor, resistor, etc. formed by any suitable forming method. Devices 304 are interconnected to form the memory device and logic device of semiconductor device 300.

One or more inter-layer dielectric (ILD) layer(s) 306 are formed on the semiconductor substrate 302 and an electrically conductive feature, such as a contact plug 308, is electrically connected to the device 304. is formed ILD layer(s) 306 may be, for example, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (boron). -doped phosphosilicate glass (BPSG), etc.; nitrides such as silicon nitride; It may be formed of any suitable dielectric material, such as others. The ILD layer(s) may be formed by any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or combinations thereof. The electrically conductive features of the ILD layer(s) may be formed through any suitable process, such as deposition, damascene (e.g., single damascene, double damascene, etc.), etc., or a combination thereof. there is.

An interconnect structure 310 is formed over the semiconductor substrate 302. Interconnect structures 310 interconnect devices 304 to form integrated circuits in logic region 300L and memory region 300M, respectively. Interconnect structure 310 includes multiple metallization layers (M1-M5). Although five metallization layers are shown, it should be understood that more or fewer metallization layers may be included. Each metallization layer (M1-M5) includes a metallization pattern in the dielectric layer. The metallization pattern is connected to the device 304 of the semiconductor substrate 302 and includes metal lines (L1-L5) and metal vias (V1-V5), respectively, formed in one or more intermetallic dielectric (IMD) layers. Interconnect structure 310 may be formed by a single damascene process, a damascene process, such as a dual damascene process, etc. In some embodiments, contact plug 308 is also part of a metallization pattern, such as a portion of metal via V1 in the bottom layer.

In this embodiment, memory array 50 is formed in interconnect structure 310. Memory array 50 can be formed in any of the metallization layers (M1-M5), and is shown as being formed in the middle metallization layer (M4), but it can also be formed in the lower metallization layer (M1-M3) or the upper metallization layer (M4). It may be formed in the fire layer (M5). Memory array 50 is electrically connected to device 304. In this embodiment, a metallization layer overlying memory array 50 (e.g., metallization layer M5) includes interconnects to source line 146S and bit line 146B. The metallization layer overlying memory array 50 (e.g., metallization layer M5) may also include interconnects to word lines 114, such as conductive contacts 166 (see FIG. 20J). In another embodiment, a metallization layer (e.g., metallization layer M3) underlying memory array 50 provides interconnects to source lines 146S, bit lines 146B, and/or word lines 114. Includes.

In some embodiments, interconnect structure 310 may be formed by first forming a layer underlying memory array 50, such as metallization layers M1-M3. Memory array 50 may then be formed on metallization layer M3, where substrate 102 may be an etch stop layer on the IMD of metallization layer M3. After forming the memory array 50, depositing and planarizing the IMD for metallization layer M4 and then forming metal lines L4 and metal vias V4, which are connected to IMD 216 and conductive contacts 166. The remainder of the metallization layer M4 may be formed, as shown (see FIG. 20J). A layer overlying memory array 50 (if present) may then be formed, for example metallization layer M5.

25-27 are diagrams of intermediate steps in the fabrication of memory array 50 according to some other embodiments. Figures 25 to 27 are three-dimensional drawings. A portion of memory array 50 is shown. Some features, such as the staircase arrangement of word lines (see Figure 1A), are not shown in some figures for clarity of explanation.

25, a substrate 102 is provided and a multilayer stack 104 is formed on the substrate 102. Substrate 102 and multilayer stack 104 are similar to those described above with respect to FIG. 2, except that in this embodiment multilayer stack 104 includes alternating dielectric layers 106 and conductive layers 168. It can be formed in this way. Conductive layer 168 may be formed of a material selected from the same group of candidate materials as main layers 114A _M , 114B _M of conductive features 114A, _114B , and , 114B _M ) can be formed using a method selected from the same group of candidate methods for forming the material.

26, trenches 110 are patterned in multilayer stack 104. Trench 110 may be formed in a manner similar to that described above with respect to FIG. 3 . In this embodiment, forming trench 110 patterns conductive layer 168 to form word lines 114. The word lines 114 in this embodiment may not include multiple layers, but may instead each be a continuous layer of a conductive material (eg, tungsten).

27, memory film 116, semiconductor layer 118, back gate isolator 120, and isolation region 122 are formed in trench 110. These features may be formed in a manner similar to that described above with respect to FIG. 6 . The features of the transistor are thus formed by a single patterning process, where only the patterning process is used to form the trench 110 and the layers of the transistor in the multilayer stack 104. After this processing step, portions of isolation region 122 may be replaced with the remaining features of the transistor as described above with respect to FIGS. 11-18. The interconnect structure may then be formed in a manner similar to that described above with respect to FIGS. 19A, 19B and 19C.

Embodiments may benefit from this. The patterned back gate isolation 120 causes the extension regions 146B _E and 146S _E of bit line 146B/source line 146S to also act as a back gate during write operations. Back gates control the surface potential of the semiconductor layer 118 (particularly the portion of the semiconductor layer 118 distal to the word line 114) during a write operation (e.g. , reduction) can be pursued. Therefore, the window for the write operation can be widened. Reducing the surface potential of the semiconductor layer 118 during a write operation also seeks to increase the write voltage applied across the memory film 116 during a write operation. Therefore, the performance of the memory array 50 can be improved.

In one embodiment, the device includes a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on sidewalls of the data storage layer; back gate isolation on sidewalls of the channel layer; and a bit line having a first main region in contact with the channel layer and a first extended region separated from the channel layer by the back gate isolator, and extending in a second direction perpendicular to the first direction. .

In some embodiments of the device, the first main region of the bit line is separated from the sidewall of the data storage layer by the channel layer. In some embodiments of the device, the first main region of the bit line contacts a single sidewall of the channel layer and the sidewall of the data storage layer. In some embodiments of the device, the first main region of the bit line contacts the sidewall of the data storage layer and a plurality of sidewalls of the channel layer. In some embodiments, the device has a second main region in contact with the channel layer and a second extended region separated from the channel layer by the back gate isolation, a source line extending in the second direction; and an isolation area between the source line and the bit line. In some embodiments of the device, the isolation area, the first extended area of the bit line, and the second extended area of the source line have the same direction in the first direction and a third direction perpendicular to the second direction. It has width. In some embodiments of the device, the isolation region has a first width in the first direction and the back gate isolation has a second width in the first direction that is greater than the first width. In some embodiments of the device, the back gate isolation includes aluminum oxide.

In some embodiments, the device includes a bit line extending in a first direction and having a first T-shaped cross-section in plan view; a source line extending in the first direction and having a second T-shaped cross-section in the plan view; an isolation region between the source line and the bit line; a word line extending in a second direction perpendicular to the first direction; a back gate isolation between the word line and each of the isolation region, the first portion of the bit line, and the second portion of the source line; a channel layer between the back gate isolator and the word line; and a data storage layer between the channel layer and the word line.

In some embodiments of the device, the isolation region has a first width in the second direction, the back gate isolation has a second width in the second direction, and the second width is greater than the first width. It's bigger. In some embodiments of the device, the channel layer has the second width in the second direction. In some embodiments of the device, the channel layer has a third width in the second direction, the combination of the bit line, the source line, and the isolation region has a fourth width in the second direction, and the The third width is larger than the second width and smaller than the fourth width. In some embodiments of the device, the channel layer has a third width in the second direction, and the combination of the bit line, the source line, and the isolation region has the third width in the second direction, and The third width is larger than the second width. In some embodiments, the device includes a source line interconnect coupled to the source line over the source line; and a bit line interconnect connected to the bit line over the bit line. In some embodiments of the device, the back gate isolation includes aluminum oxide.

In one embodiment, the method includes forming a word line between a pair of first dielectric layers; depositing a data storage layer on the sidewalls of the first dielectric layers and the word line; depositing a channel layer on sidewalls of the data storage layer; depositing a first dielectric layer on sidewalls of the channel layer; forming a first isolation region on a sidewall of the first dielectric layer; removing a first portion of the first isolation area, with a second portion of the first isolation area remaining after the removal; After removing the first portion of the first isolation region, patterning the first dielectric layer to form a back gate isolation; and forming a bit line and a source line on either side of the second portion of the first isolation region, wherein the back gate isolation separates the channel layer from the first portion of the bit line and the second portion of the source line. Separated - Includes.

In some embodiments, the method further includes patterning the channel layer while patterning the first dielectric layer. In some embodiments, the method includes forming a second isolation region extending through the channel layer; and patterning the channel layer while forming the second isolation region. In some embodiments, the method includes forming a second isolation region extending through the channel layer; and patterning the channel layer after patterning the first dielectric layer and before forming the second isolation region. In some embodiments of the method, the first dielectric layer is formed of aluminum oxide.

The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the present invention. Those skilled in the art may readily use the present disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes as the invention and/or achieve the same advantages as the embodiments introduced herein. You must understand. Those skilled in the art should recognize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present invention.

<Boogie>

1. In the device,

a word line extending in a first direction;

a data storage layer on a sidewall of the word line;

a channel layer on sidewalls of the data storage layer;

a back gate isolator on the sidewall of the channel layer; and

A bit line having a first main region and a first extended region, wherein the first main region contacts the channel layer, the first extended region is separated from the channel layer by the back gate isolation, and the bit line extends in a second direction perpendicular to the first direction -

A device containing.

2. The device of claim 1, wherein a first main region of the bit line is separated from a sidewall of the data storage layer by the channel layer.

3. The device of claim 1, wherein a first main region of the bit line contacts a single sidewall of the data storage layer and a single sidewall of the channel layer.

4. The device of claim 1, wherein the first main area of the bit line contacts a sidewall of the data storage layer and a plurality of sidewalls of the channel layer.

5. In paragraph 1,

a source line having a second main area and a second extended area, the second main area contacting the channel layer, the second extended area being separated from the channel layer by the back gate isolation, and the source line extends in the second direction -; and

Isolation area between the source line and the bit line

A device further comprising:

6. The method of claim 5, wherein the isolation area, the first extended area of the bit line, and the second extended area of the source line have the same width in the first direction and a third direction perpendicular to the second direction. A device with .

7. The method of clause 5, wherein the isolation region has a first width in the first direction, and the back gate isolation has a second width in the first direction, wherein the second width is greater than the first width. Bigger, device.

8. The device of clause 1, wherein the back gate isolation comprises aluminum oxide.

9. In the device,

a bit line extending in a first direction and having a first T-shaped cross-section in plan view;

a source line extending in the first direction and having a second T-shaped cross-section in the plan view;

an isolation region between the source line and the bit line;

a word line extending in a second direction perpendicular to the first direction;

a back gate isolation between the word line and each of the isolation region, the first portion of the bit line, and the second portion of the source line;

a channel layer between the back gate isolator and the word line; and

Data storage layer between the channel layer and the word line

A device containing.

10. The method of clause 9, wherein the isolation region has a first width in the second direction, and the back gate isolation has a second width in the second direction, wherein the second width is greater than the first width. Bigger, device.

11. The device of clause 10, wherein the channel layer has the second width in the second direction.

12. The method of clause 10, wherein the channel layer has a third width in the second direction, and the combination of the bit line, the source line, and the isolation region has a fourth width in the second direction, and A third width is greater than the second width and less than the fourth width.

13. The method of clause 10, wherein the channel layer has a third width in the second direction, and the combination of the bit line, the source line, and the isolation region has the third width in the second direction, and The device wherein the third width is greater than the second width.

14. Paragraph 10:

a source line interconnect over and coupled to the source line; and

A bit line interconnect over and connected to the bit line.

A device further comprising:

15. The device of clause 10, wherein the back gate isolation comprises aluminum oxide.

16. In the method,

forming a word line between the pair of first dielectric layers;

depositing a data storage layer on the sidewalls of the pair of first dielectric layers and the sidewalls of the word line;

depositing a channel layer on sidewalls of the data storage layer;

depositing a first dielectric layer on sidewalls of the channel layer;

forming a first isolation region on a sidewall of the first dielectric layer;

removing a first portion of the first isolation area, with a second portion of the first isolation area remaining after the removing step;

After removing the first portion of the first isolation region, patterning the first dielectric layer to form a back gate isolation; and

forming a bit line and a source line on either side of the second portion of the first isolation region, wherein the back gate isolation separates the channel layer from the first portion of the bit line and the second portion of the source line. -

Method, including.

17. According to paragraph 16,

Patterning the channel layer while patterning the first dielectric layer

A method further comprising:

18. According to paragraph 16,

forming a second isolation region extending through the channel layer; and

Patterning the channel layer while forming the second isolation region

A method further comprising:

19. According to paragraph 16,

forming a second isolation region extending through the channel layer; and

patterning the channel layer after patterning the first dielectric layer and before forming the second isolation region.

A method further comprising:

20. The method of clause 16, wherein the first dielectric layer is formed of aluminum oxide.

Claims (10)

In the device,
a word line extending in a first direction;
a data storage layer on a sidewall of the word line;
a channel layer on sidewalls of the data storage layer;
a back gate isolator on the sidewall of the channel layer; and
A bit line having a first main region and a first extended region, wherein the first main region contacts the channel layer, the first extended region is separated from the channel layer by the back gate isolation, and the bit line extends in a second direction perpendicular to the first direction -
Including,
A first main region of the bit line is separated from a sidewall of the data storage layer by the channel layer. delete In the device,
a word line extending in a first direction;
a data storage layer on a sidewall of the word line;
a channel layer on sidewalls of the data storage layer;
a back gate isolator on the sidewall of the channel layer; and
A bit line having a first main region and a first extended region, wherein the first main region contacts the channel layer, the first extended region is separated from the channel layer by the back gate isolation, and the bit line extends in a second direction perpendicular to the first direction -
Including,
A first main region of the bit line contacts a sidewall of the data storage layer and a single sidewall of the channel layer. In the device,
a word line extending in a first direction;
a data storage layer on a sidewall of the word line;
a channel layer on sidewalls of the data storage layer;
a back gate isolator on the sidewall of the channel layer; and
A bit line having a first main region and a first extended region, wherein the first main region contacts the channel layer, the first extended region is separated from the channel layer by the back gate isolation, and the bit line extends in a second direction perpendicular to the first direction -
Including,
A first main region of the bit line contacts a sidewall of the data storage layer and a plurality of sidewalls of the channel layer. According to paragraph 1,
a source line having a second main area and a second extended area, the second main area contacting the channel layer, the second extended area being separated from the channel layer by the back gate isolation, and the source line extends in the second direction -; and
Isolation area between the source line and the bit line
A device further comprising: The method of claim 5, wherein the isolation area, the first extended area of the bit line, and the second extended area of the source line have the same width in the first direction and a third direction perpendicular to the second direction. , device. 6. The method of claim 5, wherein the isolation region has a first width in the first direction and the back gate isolation has a second width in the first direction, the second width being greater than the first width. , device. The device of claim 1, wherein the back gate isolation comprises aluminum oxide. In the device,
a bit line extending in a first direction and having a first T-shaped cross-section in plan view;
a source line extending in the first direction and having a second T-shaped cross-section in the plan view;
an isolation region between the source line and the bit line;
a word line extending in a second direction perpendicular to the first direction;
a back gate isolation between the word line and each of the isolation region, the first portion of the bit line, and the second portion of the source line;
a channel layer between the back gate isolator and the word line; and
Data storage layer between the channel layer and the word line
A device containing. In the method,
forming a word line between the pair of first dielectric layers;
depositing a data storage layer on the pair of sidewalls of the first dielectric layer and the sidewall of the word line;
depositing a channel layer on sidewalls of the data storage layer;
depositing a first dielectric layer on sidewalls of the channel layer;
forming a first isolation region on a sidewall of the first dielectric layer;
removing a first portion of the first isolation area, with a second portion of the first isolation area remaining after the removing step;
After removing the first portion of the first isolation region, patterning the first dielectric layer to form a back gate isolation; and
forming a bit line and a source line on either side of the second portion of the first isolation region, wherein the back gate isolation separates the channel layer from the first portion of the bit line and the second portion of the source line. -
Method, including.

Images