KR102547663B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, the sacrificial layer is formed of multiple layers including different materials, thereby reducing the manufacturing time of the semiconductor device.

Description

Manufacturing method of semiconductor device {MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a plurality of material films.

A semiconductor device may include a memory cell array including a plurality of memory cells. A memory cell array may include memory cells arranged in various structures. In order to improve the degree of integration of a semiconductor device, memory cells may be three-dimensionally arranged on a substrate. A stack in which a plurality of material films are stacked may be used to manufacture memory cells arranged in three dimensions.

An embodiment of the present invention relates to a method of manufacturing a semiconductor device capable of reducing manufacturing time.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first material layer on a lower layer; forming a second material layer different from the first material layer on the first material layer; forming a third material layer identical to the first material layer on the second material layer; forming an upper layer on the third material layer; forming slits penetrating the upper layer and the first to third material layers; The first to third material layers are formed with an etchant that etches the first and third material layers faster than the second material layer through the slit to open an interlayer space between the upper layer and the lower layer. removing; and filling the interlayer space with a fourth material film.

A method of manufacturing a semiconductor device according to an embodiment of the present invention forms a laminate in which interlayer insulating layers and multiple sacrificial layers are alternately stacked, wherein the multiple sacrificial layers are formed by stacking first material films and second material films that are different from each other. forming; forming channel structures penetrating the stack; forming slits passing through the laminate between the channel structures; removing the multi-sacrificial layer through the slit using an etchant that etches the first material layer faster than the second material layer; and filling a region from which the multiple sacrificial layers are removed with a conductive pattern.

A method of manufacturing a semiconductor device according to an embodiment of the present invention forms a stack in which a source layer and multiple sacrificial layers are alternately stacked, wherein the multiple sacrificial layers are formed by stacking first material layers and second material layers that are different from each other. doing; forming gate stacks penetrated by channel structures on the stack; forming a slit penetrating the multiple sacrificial layers exposed between the gate stacks; removing the multi-sacrificial layer through the slit using an etchant that etches the first material layer faster than the second material layer; and filling a region from which the multiple sacrificial layers are removed with a contact source layer.

In the present technology, by forming the sacrificial layer into multiple layers including different materials, the exposed area of the sacrificial layer can be increased by using a difference in etching rate between the multiple layers with respect to an etching material for removing the sacrificial layer. Thus, the present technology can shorten the manufacturing time of the semiconductor device.

1A to 1E are process-step cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.
2A and 2B are block diagrams schematically illustrating semiconductor devices according to example embodiments.
3 is a cross-sectional view schematically illustrating a peripheral circuit structure.
4A to 4E are perspective views schematically illustrating semiconductor devices according to example embodiments.
5 is a cross-sectional view illustrating a gate stack of a semiconductor device according to example embodiments.
6A to 6G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.
7 is a cross-sectional view illustrating a gate stack and a source layer of a semiconductor device according to an exemplary embodiment.
8A to 8F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.
9 is a block diagram showing the configuration of a memory system according to an exemplary embodiment of the present invention.
10 is a block diagram showing the configuration of a computing system according to an embodiment of the present invention.

The technical spirit of the present invention can be configured with various modifications and embodiments that can have various aspects. Hereinafter, the technical spirit of the present invention will be described through some examples so that those skilled in the art can easily practice the present invention.

In embodiments of the present invention, terms such as first and/or second may be used to describe various components, but the components should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from another component, e.g., without departing from the scope of rights according to the concept of the present invention, a first component may be termed a second component, and similarly The second component may also be referred to as the first component.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when an element is referred to as “directly connected” or “directly connected” to another element, it should be understood that no other element exists in the middle. Other expressions describing the relationship between elements, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", etc., should be interpreted similarly.

Terms used in the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "have" are intended to designate that the described feature, number, step, operation, component, part, or combination thereof exists, but one or more other features or numbers However, it should be understood that it does not preclude the presence or addition of steps, operations, components, parts, or combinations thereof.

1A to 1E are process-step cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention. 1A to 1E show a method of manufacturing a semiconductor device using a replacement process in manufacturing a semiconductor device including a pattern disposed between a lower layer and an upper layer.

Referring to FIG. 1A , a lower layer 20 , multiple sacrificial layers 30 , and an upper layer 40 may be sequentially formed on a substrate 10 . The lower layer 20 and the upper layer 40 may be formed of a material different from that of the multi-sacrificial layer 30 .

The multiple sacrificial layer 30 may include a first material layer 33 , a second material layer 35 , and a third material layer 37 sequentially stacked.

The second material layer 35 is formed of a material different from that of the first material layer 33 and the third material layer 37, and the third material layer 37 is formed of the same material as the first material layer 33. It can be. More specifically, the second material layer 35 may be formed of a material having an etching rate different from that of the first material layer 33 and the third material layer 37 . Any one of the first material layer 33 and the third material layer 37 may be omitted.

The second material layer 35 may be formed thicker than each of the first material layer 33 and the third material layer 37 that are removed at a relatively high speed in a subsequent process.

Next, the upper layer 40 , the multiple sacrificial layer 30 , and the lower layer 20 may be etched to form slits 51 penetrating them.

Referring to FIG. 1B , the multi-sacrificial layer 30 is formed through the slit 51 using an etchant that etches the first and third material layers 33 and 37 faster than the second material layer 35 . can be etched. In this case, since the upper layer 40 and the lower layer 20 have high etching resistance to an etchant, the multiple sacrificial layers 30 may be selectively removed during the etching process.

While the multiple sacrificial layers 30 are selectively etched, the first and third material layers 33 and 37 are formed by a difference in etching rate between the first and third material layers 33, 35, and 37. It is etched faster than the two-material layer 35 . Thus, gaps 53 may be formed between the upper layer 40 and the second material layer 35 and between the lower layer 20 and the second material layer 35 during the etching process. The surface area of the second material layer 35 exposed to the etchant through the gap 53 may increase during the etching process.

For example, each of the first material layer 33 and the third material layer 37 includes at least one of boron phosphorus silicate glass (BPSG), undopedsilicata glass (USG), phosphorus silicate glass (PSG), and a porous nitride layer. And, the second material layer 35 may include a silicon nitride layer. In this case, the etching material may be phosphoric acid (H ₃ PO ₄ ). Each of BPSG, USG, and PSG is etched faster by phosphoric acid than silicon nitride. Since the porous nitride film has a lower density than the silicon nitride film, it is etched more quickly by phosphoric acid than the silicon nitride film having a relatively dense film quality.

For another example, each of the first material layer 33 and the third material layer 37 may include doped silicon, and the second material layer 35 may include undoped silicon. In this case, the etching material may be composed of chemicals including hydrogen fluoride (HF), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH). Doped silicon is etched more quickly by these chemicals than undoped silicon.

Referring to FIG. 1C , the first and third material layers 33 and 37 shown in FIG. 1B may be removed before the second material layer 35 is completely removed, and the second material layer 35 The etching rate of can be increased due to the increase in the surface area exposed to the etching material.

Referring to FIG. 1D , by removing the second material layer 35 shown in FIG. 1C , an interlayer space 61 is defined between the upper layer 40 and the lower layer 20 . According to an embodiment of the present invention, the removal rate of the multiple sacrificial layers can be increased by increasing the surface area of the multiple sacrificial layers exposed to an etchant, thereby reducing the manufacturing time of the semiconductor device.

Referring to FIG. 1E , the inside of the interlayer space 61 shown in FIG. 1D may be filled with a fourth material layer 63 . The lower layer 20 , the fourth material layer 63 , and the upper layer 40 may be formed of a combination of various materials.

As described above, the embodiment of the present invention including the replacement process of replacing the multiple sacrificial layers with the fourth material film through the slit increases the removal rate of the multiple sacrificial layers by forming the multiple sacrificial layers with different material films. can increase

Although not shown in the drawings, multiple sacrificial layers may be formed to fill vertically extending trenches or vertically extending holes, and the multiple sacrificial layers may be removed in the process of opening the trenches or holes.

Hereinafter, various embodiments of a semiconductor device formed using the above-described manufacturing method will be described.

2A and 2B are block diagrams schematically illustrating semiconductor devices according to example embodiments.

Referring to FIGS. 2A and 2B , each of the semiconductor devices according to example embodiments may include a peripheral circuit structure (PC) and a cell array (CAR) disposed on a substrate (SUB).

The substrate SUB may be a single crystal semiconductor film. For example, the substrate SUB may be a bulk silicon substrate, a silicon on insulator substrate, a germanium substrate, a germanium on insulator substrate, a silicon-germanium substrate, or an optional It may be an epitaxial thin film formed through a selective epitaxial growth method.

The cell array CAR may include a plurality of memory blocks. Each of the memory blocks may include a plurality of cell strings. Each of the cell strings is electrically connected to bit lines, source lines, word lines and select lines. Each of the cell strings may include memory cells and select transistors connected in series. Each of the select lines is used as a gate electrode of a corresponding select transistor, and each of the word lines is used as a gate electrode of a corresponding memory cell.

The peripheral circuit structure PC may include NMOS and PMOS transistors, resistors, and capacitors electrically connected to the cell array CAR. NMOS and PMOS transistors, resistors, and capacitors may be used as elements constituting row decoders, column decoders, page buffers, and control circuits.

As shown in FIG. 2A , the peripheral circuit structure PC may be disposed on a partial area of the substrate SUB that does not overlap the cell array CAR.

Alternatively, as shown in FIG. 2B , the peripheral circuit structure PC may be disposed between the cell array CAR and the substrate SUB. In this case, since the peripheral circuit structure PC overlaps the cell array CAR, the area of the substrate SUB occupied by the cell array CAR and the peripheral circuit structure PC can be reduced.

3 is a cross-sectional view schematically illustrating a peripheral circuit structure PC. The peripheral circuit structure PC shown in FIG. 3 may be included in the peripheral circuit structure shown in FIG. 2A or included in the peripheral circuit structure shown in FIG. 2B.

Referring to FIG. 3 , the peripheral circuit structure PC includes peripheral gate electrodes PG, peripheral gate insulating film PGI, junctions Jn, peripheral circuit lines PCL, peripheral contact plugs PCP, and a peripheral circuit insulating layer (PIL).

Each of the peripheral gate electrodes PG may be used as a gate electrode of an NMOS transistor and a PMOS transistor of the peripheral circuit structure PC. The peripheral gate insulating layer PGI is disposed between each of the peripheral gate electrodes PG and the substrate SUB.

The junctions Jn are regions defined by implanting n-type or p-type impurities into the active region of the substrate SUB, and are disposed on both sides of each of the peripheral gate electrodes PG to be used as a source junction or a drain junction. . An active region of the substrate SUB may be partitioned by an isolation layer (ISO) formed inside the substrate SUB. The element isolation layer ISO is formed of an insulating material.

The peripheral circuit lines PCL may be electrically connected to circuits of the peripheral circuit structure PC through the peripheral contact plugs PCP.

The peripheral circuit insulating layer PIL may cover the circuit of the peripheral circuit structure PC, the peripheral circuit lines PCL, and the peripheral contact plugs PCP. The peripheral circuit insulating layer PIL may include insulating layers stacked in multiple layers.

4A to 4E are perspective views schematically illustrating semiconductor devices according to example embodiments. For convenience of recognition, interlayer insulating layers are not shown in FIGS. 4A to 4E.

Referring to FIGS. 4A to 4E , a semiconductor device according to an embodiment of the present invention may include a memory string CST having a 3D structure. The memory string CST having a 3D structure can improve the degree of integration of a semiconductor device. The memory string CST may include memory cells and select transistors arranged along each of the channel structures CH.

Each of the channel structures CH may be electrically connected to a corresponding bit line BL. The bit line BL may extend in a second direction II on a horizontal plane crossing the first direction I. As an example, the bit line BL may directly contact the corresponding channel structure CH as shown in FIGS. 4A to 4D . As an example, the bit line BL may be connected to a corresponding channel structure CH via a contact plug DCT, as shown in FIG. 4E . The contact plug DCT may be in contact with the bit line BL and may extend toward a corresponding channel structure CH.

The gates of the memory cells and the gates of the select transistors may be spaced apart from each other in the first direction I and connected to the stacked conductive patterns CP1 to CPn. The conductive patterns CP1 to CPn may be used as word lines WL, source select lines SSL, and drain select lines DSL. The conductive patterns CP1 to CPn may be sequentially arranged in the first direction I and may be disposed in an n-th layer from a first layer spaced apart from each other. The first layer is defined as a layer disposed farthest from the bit line BL, and the n-th layer is defined as a layer disposed closest to the bit line BL. Each of the conductive patterns CP1 to CPn may extend in a horizontal direction.

Referring to FIGS. 4A to 4D , among the conductive patterns CP1 to CPn, nth patterns CPn disposed on at least an nth layer may be used as drain select lines DSL. The present invention is not limited thereto, and conductive patterns disposed on two or more layers may be used as the drain select lines DSL. As an example, the nth patterns CPn disposed on the nth layer and the n−1th patterns CPn−1 disposed on the n−1th layer may be used as the drain select lines DSL. there is.

The first patterns CP1 disposed on at least a first layer among the conductive patterns CP1 to CPn may be used as source select lines SSL. The present invention is not limited thereto, and conductive patterns disposed on two or more layers may be used as the source select lines SSL. As an example, the first patterns CP1 disposed on the first layer and the second patterns CP2 disposed on the second layer may be used as the source select lines SSL.

Conductive patterns (for example, CP3 to CPn−2) disposed between the drain select lines DSL and the source select lines SSL may be used as word lines WL.

The conductive patterns CP1 to CPn may be separated from each other by the first slit SI1 in each layer. Among the conductive patterns CP1 to CPn, patterns used as the drain select lines DSL may be separated from each other by the first slit SI1 and the second slit SI2 in each layer. The present invention is not limited thereto. Although not shown in the drawing, as an example, the patterns used for the source select lines SSL among the conductive patterns CP1 to CPn are separated from each other by the third slit as well as the first slit SI1 in each layer. It can be. Although not shown in the drawings, as an example, the second slit SI2 may be omitted. In this case, the patterns used as the drain select lines DSL are separated from each other by the first slit SI1 in each layer. It can be. The aforementioned second slit SI2 and third slit may overlap each layer of the word lines WL separated by the first slit SI1 and are formed to a depth that does not penetrate the word lines WL. It can be.

The first slit SI1 and the second slit SI2 may extend along the third direction III in a horizontal plane. The third direction (III) is defined as a direction crossing the first direction (I) and the second direction (II). The channel structures CH shared by each of the word lines WL may be divided into groups controlled by different drain select lines DSL. As an example, the drain select lines DSL may include a first drain select line and a second drain select line separated from each other by a second slit SI2. In this case, the channel structures CH shared by each of the word lines WL may be divided into a first group controlled by the first drain select line and a second group controlled by the second drain select line. .

Each of the word lines WL, drain select lines DSL, and source select lines SSL may commonly wrap one or more columns of channel structures CH. The channel structures CH surrounded by each of the word lines WL, drain select lines DSL, and source select lines SSL may be arranged in a zigzag pattern.

The first slit SI1 may be disposed at a boundary between memory blocks. The drain select lines DSL disposed on the same layer in each of the memory blocks may be separated from each other by the second slit SI2. Each of the word lines WL may extend to overlap the second slit SI2 without being separated by the second slit SI2. Although not shown in the drawing, the source select lines SSL disposed on the same layer in each of the memory blocks may be separated by a third slit. Each of the word lines WL may extend to overlap the third slit without being separated by the third slit.

Referring to FIGS. 4A, 4B, and 4D , each of the channel structures CH may pass through drain select lines DSL, word lines WL, and source select lines SSL. Referring to FIG. 4C , each of the channel structures CH may pass through drain select lines DSL and word lines WL.

Referring to FIGS. 4A and 4B , the channel structures CH may be directly connected to the source layer SL disposed under the conductive patterns CP1 to CPn. The source layer SL may be formed in various structures.

Referring to FIG. 4A , the source layer SL may contact the bottom surface of each of the channel structures CH. The source layer SL may be formed of a doped semiconductor layer including a source dopant. The source dopant may include an n-type impurity. As an example, the source layer SL may be formed by injecting a source dopant to a partial thickness from the surface of the substrate SUB described with reference to FIG. 2A. As an example, the source film SL may be formed by depositing a doped semiconductor film on the substrate SUB described with reference to FIG. 2B. In this case, an insulating layer may be disposed between the substrate SUB and the doped semiconductor layer. As an example, the doped semiconductor film may be a doped silicon film.

Each of the channel structures CH is in contact with the upper surface of the source film SL, passes through the conductive patterns CP1 to CPn, and moves in a first direction I from the source film SL toward the bit line BL. can be extended along A sidewall of each of the channel structures CH may be surrounded by a multilayer film ML. The multilayer film ML may extend along the sidewall of the corresponding channel structure CH. The top and bottom surfaces of each of the channel structures CH may be opened without being blocked by the multilayer film ML.

Referring to FIG. 4B , the channel structures CH may pass through the conductive patterns CP1 to CPn and extend into the source layer SL. A sidewall of each of the channel structures CH may contact the source layer SL.

The source layer SL may include a first source layer SL1 and a contact source layer CTS. The source layer SL may further include a second source layer SL2. The channel structures CH may pass through the second source layer SL2 and the contact source layer CTS and extend into the first source layer SL1.

The first source layer SL1 may be formed of a doped semiconductor layer including a source dopant. The source dopant may include an n-type impurity. As an example, the first source layer SL1 may be formed by implanting a source dopant to a partial thickness from the surface of the substrate SUB described with reference to FIG. 2A . As an example, the first source layer SL1 may be formed by depositing a doped semiconductor layer on the substrate SUB described with reference to FIG. 2B. In this case, an insulating layer may be disposed between the substrate SUB and the doped semiconductor layer. As an example, the doped semiconductor film may be a doped silicon film. The first source layer SL1 may cover lower ends of each of the channel structures CH.

The contact source layer CTS is disposed on the first source layer SL1 and may contact an upper surface of the first source layer SL1. The contact source film (CTS) contacts the sidewall of each of the channel structures (CH) and surrounds the channel structures (CH).

The multilayer film extending along the sidewall of each of the channel structures CH is separated into a first multilayer pattern ML1 and a second multilayer pattern ML2 by the contact source film CTS. The first multi-layer pattern ML1 is defined as a pattern surrounding the top of each of the channel structures CH, and the second multi-layer pattern ML2 is disposed between the first source layer SL1 and each channel structure CH. defined as a pattern.

The second source layer SL2 may be disposed between the contact source layer CTS and the source select line SSL. The second source layer SL2 may be formed to surround the first multi-layer pattern ML1. The second source layer SL2 may be omitted in some cases. The second source layer SL2 may be penetrated by the first slit SI1.

Each of the aforementioned contact source layer CTS and second source layer SL2 may be formed of a doped semiconductor layer including a source dopant. The source dopant may include an n-type impurity. As an example, the doped semiconductor layer may include a doped silicon layer.

Referring to FIG. 4C , each of the channel structures (CH) may be connected to a corresponding lower channel structure (LPC).

The lower channel structure (LPC) is connected below the corresponding channel structure (CH). Each channel structure CH may be surrounded by a multilayer film ML. The multilayer film ML may extend along the sidewall of the corresponding channel structure CH. The top and bottom surfaces of the channel structure CH are open without being blocked by the multilayer film ML.

The lower channel structure LPC passes through at least one source select line SSL disposed below the word lines WL. A sidewall of the lower channel structure LPC may be surrounded by a gate insulating layer GI. The gate insulating layer GI may extend along sidewalls of the lower channel structure LPC. Top and bottom surfaces of the lower channel structure LPC may be open without being blocked by the gate insulating layer GI.

The source layer SL may contact the bottom surface of the lower channel structure LPC. The source layer SL may be formed of the same material as the source layer SL described with reference to FIG. 4A.

Referring to FIG. 4D , each of the channel structures CH may include pillar parts PL passing through the conductive patterns CP1 to CPn and horizontal parts HP extending in a horizontal direction from the pillar parts PL. can The horizontal portions HP of the channel structures CH may extend along lower surfaces of the first patterns CP1. The horizontal parts HP may be separated from each other by the slit extension part SIE extending from the first slit SI1. A doped area DA may be disposed below the horizontal portions HP. In other words, the horizontal portions HP may be disposed between the doped area DA and the first patterns CP1.

As an example, the doped area DA may be formed of a doped semiconductor layer including a well dopant. The well dopant may include a p-type impurity. As an example, the doped area DA may be formed by implanting a well dopant to a partial thickness from the surface of the substrate SUB described with reference to FIG. 2A . As an example, the doped area DA may be formed by depositing a doped semiconductor film on the substrate SUB described with reference to FIG. 2B. In this case, an insulating layer may be disposed between the substrate SUB and the doped semiconductor layer. As an example, the doped semiconductor film may be a doped silicon film.

A sidewall of each of the pillar parts PL may be surrounded by a multilayer film ML. The multilayer film ML may extend between the corresponding horizontal portion HP and the first pattern CP1. The multilayer film ML may extend between the corresponding horizontal portion HP and the doped area DA.

Referring to FIG. 4E , the conductive patterns CP1 to CPn may be divided into source-side conductive patterns CP_S and drain-side conductive patterns CP_D by a slit SI.

The source-side n-th pattern CPn disposed on at least the n-th layer among the source-side conductive patterns CP_S may be used as the source select line SSL. The present invention is not limited thereto, and each of the conductive patterns disposed on two or more layers may be used as the source select line SSL. As an embodiment, the source-side n-th pattern CPn and the source-side n-1-th pattern CPn-1 respectively disposed on the n-layer and the n-1-th layer among the source-side conductive patterns CP_S are source select. line (SSL). Among the source-side conductive patterns CP_S, conductive patterns (for example, CP1 to CPn-2) disposed below the source select line SSL may be used as the source-side word lines WL_S.

Among the drain-side conductive patterns CP_D, the drain-side n-th pattern CPn disposed on at least the n-th layer may be used as the drain select line DSL. The present invention is not limited thereto, and each of the conductive patterns disposed on two or more layers may be used as the drain select line DSL. As an example, among the drain-side conductive patterns CP_D, the drain-side n-th pattern CPn and the drain-side n-1-th pattern CPn-1 disposed on the n layer and the n-1 layer, respectively, drain select It can be used as a line (DSL). Among the drain-side conductive patterns CP_D, the conductive patterns (for example, CP1 to CPn-2) disposed under the drain select line DSL may be used as the drain-side word lines WL_D.

A common source line CSL may be disposed on the source-side conductive patterns CP_S. The common source line CSL is disposed on a different layer from the bit line BL. The common source line CSL and the bit line BL are formed of a conductive material and are spaced apart from each other. For example, the common source line CSL may be disposed between the bit line BL and the source-side conductive patterns CP_S.

Each of the channel structures CH may include a source-side pillar S_PL, a drain-side pillar D_PL, and a horizontal portion HP. The drain-side pillar D_PL may be electrically connected to the bit line BL. The drain-side pillar D_PL extends through the drain-side conductive patterns CP_D and is connected to the horizontal portion HP. The source-side pillar S_PL may be electrically connected to the common source line CSL. The source-side pillar S_PL extends through the source-side conductive patterns CP_S and is connected to the horizontal portion HP. The horizontal portion HP is buried inside the pipe gate PG. The source-side pillar S_PL and the drain-side pillar D_PL extend along the first direction I from the horizontal portion HP. The pipe gate PG may be disposed below the source-side conductive patterns CP_S and the drain-side conductive patterns CP_D and may surround the horizontal portion HP. The pipe gate PG may be used as a gate of a pipe transistor. The pipe transistor may electrically connect the source-side pillar S_PL and the drain-side pillar D_PL through the horizontal portion HP according to a signal transmitted to the pipe gate PG.

An outer wall of each of the channel structures CH may be surrounded by a multilayer film ML. The multilayer film ML extends along the sidewall of the drain-side pillar D_PL, the outer wall of the horizontal portion HP, and the sidewall of the source-side pillar S_PL of the corresponding channel structure CH.

The slit SI may be disposed between the source-side conductive patterns CP_S and the drain-side conductive patterns CP_D adjacent to each other in the second direction II, and may extend along the third direction III. Each of the source-side conductive patterns CP_S, the drain-side conductive patterns CP_D, and the common source line CSL may be formed in a line shape extending along the third direction III.

The word lines WL, WL_D or WL_S described above with reference to FIGS. 4A to 4E are used as gates of memory cells, the drain select line DSL is used as a gate of a drain select transistor, and the source select line ( SSL) is used as the gate of the source select transistor. The multilayer film ML or ML1 disposed between each of the word lines WL, WL_D or WL_S and each channel structure CH may include a data storage film for storing data.

The gate stack including the word lines WL, WL_D or WL_S, the drain select line DSL and the source select line SSL described above with reference to FIGS. 4A to 4E may be formed using various manufacturing methods. there is. According to an embodiment of the present invention, the manufacturing time of the semiconductor device can be reduced by forming the gate stacked body using the replacement process described above with reference to FIGS. 1A to 1E .

5 is a cross-sectional view illustrating a gate stack of a semiconductor device according to example embodiments. 5 may correspond to an enlarged cross-sectional view of a gate stack including the conductive patterns shown in FIGS. 4A to 4E .

Referring to FIG. 5 , gate stacks GST may be separated from each other by slits SI. Each of the gate stacks GST may include interlayer insulating layers ILD and conductive patterns CP alternately stacked in the first direction I. The conductive patterns CP may correspond to the conductive patterns CP1 to CPn shown in any one of FIGS. 4A to 4E . Each of the conductive patterns CP is disposed between interlayer insulating layers ILD adjacent to each other in the first direction I.

Each of the conductive patterns CP may be formed of various conductive materials. Each of the conductive patterns CP may include at least one of a silicon layer, a metal silicide layer, a metal layer, and a metal nitride layer. As an example, each of the conductive patterns CP may include a metal layer A such as tungsten (W) for low-resistance wiring. When each of the conductive patterns CP includes the metal layer A, each of the conductive patterns CP may further include a barrier layer B.

The barrier film (B) may block diffusion of metal from the metal film (A) to the outside. The barrier film (B) may have a C-shaped cross-sectional structure surrounding the metal film (A) and opening toward the slit (SI). The barrier layer B may extend between the channel structure CH and the metal layer A and between the metal layer A and each of the interlayer insulating layers ILD. The barrier layer (B) may be formed of a metal nitride layer. For example, the barrier layer B may include a titanium nitride layer, a tungsten nitride layer, or a tantalum nitride layer.

The interlayer insulating layers ILD may be formed of various insulating materials. For example, the interlayer insulating layers ILD may be formed of a silicon oxide layer.

The channel structure CH penetrating each of the gate stacks GST is surrounded by interlayer insulating layers ILD and conductive patterns CP. A multilayer film ML may be disposed between the channel structure CH and each of the conductive patterns CP. The multilayer film ML may correspond to the multilayer film ML shown in FIGS. 4A and 4C to 4D , or may correspond to the first multilayer pattern ML1 shown in FIG. 4B .

The multilayer film ML may extend along the sidewall of the channel structure CH. Embodiments of the present invention are not limited thereto. Although not shown in the drawings, as an example, the multilayer film ML includes interfaces between the conductive patterns CP and the interlayer insulating layers ILD and interfaces between the channel structure CH and the conductive patterns CP. can be extended along the The barrier layer B may extend between the corresponding metal layer A and the multilayer layer ML.

The channel structure CH may include a semiconductor layer SE. As an example, the semiconductor layer SE may be formed of a silicon layer. The semiconductor layer SE may be conformally formed on an inner wall of the multilayer layer ML or may be formed to completely fill a central region of the multilayer layer ML.

As shown in FIG. 5 , when the semiconductor film SE is conformally formed on the inner wall of the multilayer film ML, the channel structure CH includes the core insulating film CO filling the central region of the semiconductor film SE. can include more.

The multilayer ML includes a tunnel insulating layer TI surrounding the channel structure CH, a data storage layer DL surrounding the tunnel insulating layer TI, and a first blocking insulating layer BI1 surrounding the data storage layer DL. can do.

The data storage layer DL may be formed of a charge trap layer, a material layer including conductive nano dots, or a phase change material layer.

The data storage layer DL is changed using Fowler-Nordheim tunneling caused by a voltage difference between a pattern used as word lines among the conductive patterns CP and the channel structure CH. data can be stored. To this end, the data storage layer DL may be formed of a silicon nitride layer capable of trapping charges.

The data storage layer DL may store data based on an operating principle other than Fowler-Nordheim tunneling. For example, the data storage layer DL is formed of a phase change material layer and may store data according to the phase change.

The first blocking insulating layer BI1 may include an oxide layer capable of blocking charges. The tunnel insulating layer TI may be formed of a silicon oxide layer capable of charge tunneling. A second blocking insulating layer BI2 may be further formed along an interface between each of the conductive patterns CP and the interlayer insulating layers ILD. The second blocking insulating layer BI2 may extend on sidewalls of each of the interlayer insulating layers ILD facing the slit SI. The second blocking insulating layer BI2 may be formed of an insulating material having a high dielectric constant. For example, the second blocking insulating layer BI2 may be formed of an aluminum oxide layer. Either one of the first blocking insulating layer BI1 and the second blocking insulating layer BI2 may be omitted.

The slit SI may correspond to the first slit SI1 illustrated in FIGS. 4A to 4D , or may correspond to the slit SI illustrated in FIG. 4E . The slit SI may be filled with the vertical structure VP. As an example, the vertical structure VP may be formed by completely filling the slit SI with an insulating material. As an example, the vertical structure VP may include a conductive material and a side wall insulating film surrounding the conductive material.

6A to 6G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment. Specifically, FIGS. 6A to 6G are cross-sectional views illustrating a method of manufacturing a gate stack using a replacement process.

Referring to FIG. 6A , a laminate 130 is formed by alternately stacking interlayer insulating layers 115 and multiple sacrificial layers 127 in a first direction (I).

The interlayer insulating layers 115 are formed of a material different from that of the multiple sacrificial layers 127 . The interlayer insulating layers 115 may be formed of oxide such as silicon oxide. Each of the multiple sacrificial layers 127 may be formed by alternately stacking different materials. As an example, each of the multiple sacrificial layers 127 may include a first material layer 121 , a second material layer 123 , and a third material layer 125 sequentially stacked.

The second material layer 123 is formed of a material different from that of the first material layer 121 and the third material layer 125, and the third material layer 125 is formed of the same material as the first material layer 121. It can be. More specifically, the second material layer 123 may be formed of a material having an etch rate different from that of the first material layer 121 and the third material layer 125 . Any one of the first material layer 121 and the third material layer 125 may be omitted.

The second material layer 123 may be formed thicker than each of the first material layer 121 and the third material layer 125 that are removed at a relatively high speed in a subsequent process.

Referring to FIG. 6B , channel structures 159 penetrating the laminate 130 may be formed. Forming the channel structures 159 may include forming holes 141 penetrating the laminate 130 and filling the holes 141 with the channel structures 159 , respectively. Before forming the channel structures 159 , a step of forming a multilayer film 149 on sidewalls of each of the holes 141 may be further included. In this case, the channel structures 159 may be formed on the multilayer film 149 .

In the step of forming the multilayer film 149, the first blocking insulating film 143, the data storage film 145, and the tunnel insulating film 147 are sequentially formed from the sidewalls of each of the holes 141 toward the central region of each of the holes 141. It may include layering. Examples of materials for each of the first blocking insulating layer 143 , the data storage layer 145 , and the tunnel insulating layer 147 are the same as those described with reference to FIG. 5 .

Each of the channel structures 159 may include the semiconductor film 151 as described above with reference to FIG. 5 or may include the semiconductor film 151 and the core insulating film 153 .

Subsequently, slits 161 penetrating the laminate 130 may be formed between the channel structures 159 .

Referring to FIG. 6C , the multiple sacrificial layers 127 are formed through the slit 161 by using an etchant that etches the first and third material layers 121 and 125 faster than the second material layer 123 . ) can be etched. In this case, since the interlayer insulating layers 115 have high etching resistance to an etching material, the multiple sacrificial layers 127 may be selectively removed during an etching process.

At the beginning of an etching process for selectively etching the multiple sacrificial layers 127 , an etchant may flow in the direction of an arrow indicated in region C through the slit 161 . At this time, the first and third material layers 121 and 125 are etched faster than the second material layer 123 due to a difference in etching speed between the first to third material layers 121 , 123 , and 125 . . As a result, a gap 163 may be formed between each of the interlayer insulating layers 115 and the second material layer 123 .

For example, each of the first material layer 121 and the third material layer 125 includes at least one of boron phosphorus silicate glass (BPSG), undopedsilicata glass (USG), phosphorus silicate glass (PSG), and a porous nitride layer. And, the second material layer 123 may include a silicon nitride layer. In this case, the etching material may be phosphoric acid (H ₃ PO ₄ ). Each of BPSG, USG, and PSG is etched faster by phosphoric acid than silicon nitride. Since the porous nitride film has a lower density than the silicon nitride film, it is etched faster in phosphoric acid than the silicon nitride film having a relatively dense film quality.

Referring to FIG. 6D , an etching material may be introduced through the gap 163 shown in FIG. 6C . Accordingly, during the process of selectively etching the multiple sacrificial layers 127 , the second material layer 123 may be etched in the direction of the arrow indicated in region D. According to an embodiment of the present invention, since the surface area of the second material layer 123 exposed to the etchant can be increased through the gap 163 shown in FIG. 6C, the etching rate of the second material layer 123 can be increased. can

As described above, according to the embodiment of the present invention, the interlayer insulating layers 115 adjacent to each other in the first direction (I) at a faster speed than in the case of disposing a sacrificial layer formed of a single film between the interlayer insulating layers 115. ) can be exposed. Thus, according to an embodiment of the present invention, the time for which the patterns of the semiconductor device are exposed to the etchant may be reduced. As a result, an embodiment of the present invention can reduce a phenomenon in which patterns of a semiconductor device are contaminated by an etchant. Accordingly, embodiments of the inventive concept may improve reliability of a semiconductor device.

Referring to FIG. 6E , after the multiple sacrificial layers are removed through a selective etching process, interlayer spaces 165 between adjacent interlayer insulating layers 115 in the first direction (I) may be opened. According to an embodiment of the present invention, the time required to open the interlayer spaces 165 between the interlayer insulating layers 115 can be shortened through the multiple sacrificial layers, thereby reducing the manufacturing time of the semiconductor device.

Referring to FIG. 6F , the interior of the interlayer spaces 165 shown in FIG. 6E is filled with a conductive material 179 through the slit 161 . Before filling the interlayer spaces 165 with the conductive material 179 , a second blocking insulating layer 171 may be further formed on each surface of the interlayer spaces 165 . The second blocking insulating layer 171 corresponds to the second blocking insulating layer described with reference to FIG. 5 . The second blocking insulating layer 171 may extend to cover each of the sidewalls of the interlayer insulating layers 115 facing the slit 161 .

The conductive material 179 may include at least one of a silicon layer, a metal silicide layer, a metal layer, and a metal nitride layer. As an example, the conductive material 179 may include a metal film 175 such as tungsten (W) for low-resistance wiring. In this case, the conductive material 179 may further include a barrier layer 173 . The barrier film 173 may be conformally formed on each surface of the interlayer spaces 165 shown in FIG. 6E before forming the metal film 175 . The barrier layer 173 may be formed of a metal nitride layer. For example, the barrier layer 173 may include a titanium nitride layer, a tungsten nitride layer, or a tantalum nitride layer.

Referring to FIG. 6G , the conductive material 179 is etched so that the conductive material 179 can be separated into a plurality of conductive patterns 179P. As a result, a gate stacked body GST including the conductive patterns 179P and the interlayer insulating layer 115 alternately stacked in the first direction (I) may be formed.

Subsequently, the slit 161 may be filled with the vertical structure VP described above with reference to FIG. 5 .

7 is a cross-sectional view illustrating a gate stack and a source layer of a semiconductor device according to an exemplary embodiment. FIG. 7 is an enlarged cross-sectional view of a source layer and a gate stack adjacent to the source layer shown in FIG. 4B.

Referring to FIG. 7 , gate stacks GST according to example embodiments may be separated from each other by a slit SI1. Each of the gate stacked bodies GST may have the same structure as described above with reference to FIG. 5 .

The channel structure CH passing through each of the gate stacks GST may extend into the source layer SL. As described above with reference to FIG. 4B , the source layer SL may include the first source layer SL1 and the contact source layer CTS, and may further include a second source layer SL2.

As described above with reference to FIG. 4B , the channel structure CH is surrounded by the first multi-layer pattern ML1 and the second multi-layer pattern ML2 separated from each other by the contact source layer CTS. The channel structure CH may include a semiconductor layer SE. As an example, the semiconductor layer SE may be formed of a silicon layer. The semiconductor layer SE may be conformally formed on the inner wall of the first multi-layer pattern ML1 or may be formed to completely fill the central region of the hole defined by the first multi-layer pattern ML1. The semiconductor layer SE extends on the second multi-layer pattern ML2.

As shown in FIG. 7 , when the semiconductor film SE is conformally formed on the inner wall of the first multi-layer pattern ML1, the channel structure CH is a core insulating film filling the central region of the semiconductor film SE. CO) may be further included.

Each of the first multi-layer pattern ML1 and the second multi-layer pattern ML2 includes a tunnel insulating layer TI surrounding the channel structure CH, a data storage layer DL surrounding the tunnel insulating layer TI, and a data storage layer DL. ) may include a first blocking insulating layer BI1 surrounding the .

Materials of the tunnel insulating layer TI, the data storage layer DL, and the first blocking insulating layer BI1 are the same as those described with reference to FIG. 5 .

The slit SI1 may correspond to the first slit SI1 shown in FIG. 4B. The slit SI1 may be filled with the vertical structure VP. As an example, the vertical structure VP includes a spacer insulating layer SP covering sidewalls of each of the gate stacks GST and a conductive vertical contact structure VCT filling the inside of the slit SI1 on the spacer insulating layer SP. can include

8A to 8F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment. Specifically, FIGS. 8A to 8F are cross-sectional views illustrating a method of manufacturing a source film using a replacement process.

Referring to FIG. 8A , a source stack structure (STS) including a first source layer 201 and multiple sacrificial layers 217 is formed. A second source layer 221 may be further formed on the multi-sacrificial layer 217 . Before forming the multi-sacrificial layer 217 on the first source layer 201, a first passivation layer 203 may be further formed. In this case, the multiple sacrificial layer 217 is formed on the first passivation layer 203 . Before forming the second source layer 221 , a second passivation layer 219 may be further formed on the multi-sacrificial layer 217 . In this case, the second source layer 221 may be formed on the second passivation layer 219 . At least one of the first passivation layer 203 , the second passivation layer 219 , and the second source layer 221 may be omitted in some cases.

Each of the first source layer 201 and the second source layer 221 may be a doped semiconductor layer including a source dopant. The source dopant may include an n-type impurity. As an example, each of the first source layer 201 and the second source layer 221 may be formed of an n-type doped silicon layer. The first protective layer 203 and the second protective layer 219 may be formed of an oxide layer.

The multiple sacrificial layer 217 may include a first material layer 211 , a second material layer 213 , and a third material layer 215 sequentially stacked.

The second material layer 213 is formed of a material different from that of the first material layer 211 and the third material layer 215 , and the third material layer 215 is formed of the same material as the first material layer 211 . It can be. Any one of the first material layer 211 and the third material layer 215 may be omitted. The second material layer 213 may be formed thicker than each of the first material layer 211 and the third material layer 215 that are removed at a relatively high speed in a subsequent process.

Subsequently, a slit is formed on the source stack structure (STS) including the first source layer 201, the first passivation layer 203, the multi-sacrificial layer 217, the second passivation layer 219, and the second source layer 221. Gate stacks GST separated by 261 are formed. The gate stacks GST are penetrated by the channel structures 259 .

The gate stacks GST described above may be formed using the processes described above with reference to FIGS. 6A to 6G . In an embodiment of the present invention, the channel structures 259 may pass through the gate stacks GST and extend into the source stack STS.

A multilayer film 249 may be formed along outer walls of each of the channel structures 259 . The multilayer film 249 is disposed between the corresponding channel structure 259 and the gate stacked structure GST, and extends between the corresponding channel structure 259 and the source stacked structure STS. The channel structure 259 may completely penetrate the first passivation layer 203 , the multi-sacrificial layer 217 , the second passivation layer 219 and the second source layer 221 . A bottom surface of the channel structure 259 may be disposed inside the first source layer 201 .

The multilayer film 249 may include a first blocking insulating film 243 , a data storage film 245 , and a tunnel insulating film 247 . The first blocking insulating layer 243, the data storage layer 245, and the tunnel insulating layer 247 are sequentially formed from the surface of the corresponding gate stack structure (GST) or source stack structure (STS) toward the surface of the channel structure 259. are layered with Each of the first blocking insulating layer 243 , the data storage layer 245 , and the tunnel insulating layer 247 may be formed of the same materials as described above with reference to FIG. 5 .

Each of the channel structures 259 may include the semiconductor film 251 as described above with reference to FIG. 5 or may include the semiconductor film 251 and the core insulating film 253 .

A spacer insulating layer 271 may be formed on sidewalls of each of the gate stacks GST exposed by the slit 261 . The spacer insulating layer 271 may be formed of an oxide layer. The bottom surface of the slit 261 is exposed without being blocked by the spacer insulating film 271 .

Referring to FIG. 8B , the second source layer 221 exposed through the bottom surface of the slit 261 may be etched, and the etched surface of the second source layer 221 may be oxidized. A sidewall passivation layer 223 may be formed on a sidewall of the oxidized second source layer 221 . Subsequently, the second passivation layer 219 exposed through the slit 261 and the multiple sacrificial layer 217 are etched to form the slit extension portion 281 . The slit extension 281 is connected to the slit 261 .

Referring to FIG. 8C , multiple sacrificial layers are formed through the slit extension part 281 by using an etchant that etches the first and third material layers 211 and 215 faster than the second material layer 213. 217) can be etched. In this case, since the sidewall passivation layer 223, the first passivation layer 219, and the second passivation layer 203 have high etching resistance to an etchant, the multiple sacrificial layers 217 can be selectively removed during the etching process. there is.

While the multiple sacrificial layers 217 are selectively etched, the first passivation layer 203 and the second material layer 213 are formed by a difference in etching rate between the first to third material layers 211 , 213 , and 215 . A gap 283 may be formed between the gap 283 and between the second passivation layer 219 and the second material layer 213 .

Each of the first material layer 211 and the third material layer 215 may include doped silicon, and the second material layer 213 may include undoped silicon. In this case, the etching material may be composed of chemicals including hydrogen fluoride (HF), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH). Doped silicon is etched more quickly by these chemicals than undoped silicon.

Referring to FIG. 8D , since the surface area of the second material layer 213 exposed to the etching material may be increased through the gap 283 shown in FIG. 8C , the etching rate of the second material layer 213 may be increased. .

Referring to FIG. 8E , the opening time of the interlayer space 285 between the first source film 201 and the second source film 221 is reduced by rapidly removing the multiple sacrificial layers according to an embodiment of the present invention. can be shortened While removing the multiple sacrificial layers, the first passivation layer 203 and the second passivation layer 219 shown in FIG. 8C may prevent loss of the first source layer 201 and the second source layer 221 .

After removing the multiple sacrificial layers, the first source layer 201 and the second source layer 221 may be exposed by removing the first passivation layer 203 and the second passivation layer 219 shown in FIG. 8D . As a result, the width of the interlayer space 285 may be expanded. While the first passivation layer 203 and the second passivation layer 219 are removed, the sidewall passivation layer 223 shown in FIG. 8D may be removed to expose the sidewall of the second source layer 221 .

The first blocking insulating layer 243, the data storage layer 245, and the tunnel insulating layer 247 exposed between the first source layer 201 and the second source layer 221 form sidewalls of each of the channel structures 259. It may be removed to be exposed between the first source layer 201 and the second source layer 221 . Accordingly, the width of the interlayer space 285 may be expanded. The semiconductor layer 251 of each of the channel structures 259 is exposed through the expanded interlayer space 285 .

Referring to FIG. 8F , the interlayer space 285 shown in FIG. 8E is filled with a contact source layer 287 . The contact source layer 287 directly contacts sidewalls of the channel structures 259 and the first and second source layers 201 and 221 . The contact source layer 287 may be formed of a doped silicon layer including a source dopant.

The contact source layer 287 may be formed using a selective growth method (eg, selective epitaxial growth (SEG)) or a non-selective deposition method (eg, chemical vapor deposition (CVD)). In the case of using the selective growth method, the semiconductor film 251 of each of the channel structures 259 and the first and second source films 201 and 221 may serve as a seed layer.

Subsequently, the slit 261 may be filled with the vertical structure VP described above with reference to FIG. 7 .

9 is a block diagram showing the configuration of a memory system according to an exemplary embodiment of the present invention.

Referring to FIG. 9 , a memory system 1100 according to an exemplary embodiment includes a memory device 1120 and a memory controller 1110 .

The memory device 1120 may be a multi-chip package including a plurality of flash memory chips. The memory device 1120 may include at least one of the structures shown in FIGS. 4A to 4E.

The memory controller 1110 is configured to control the memory device 1120, and includes a static random access memory (SRAM) 1111, a CPU 1112, a host interface 1113, an error correction code (ECC) 1114, a memory interface 1115. The SRAM 1111 is used as an operating memory of the CPU 1112, the CPU 1112 performs various control operations for data exchange of the memory controller 1110, and the host interface 1113 is connected to the memory system 1100. It has the data exchange protocol of the host to be used. In addition, the ECC 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 performs interfacing with the memory device 1120. In addition, the memory controller 1110 may further include a read only memory (ROM) for storing code data for interfacing with a host.

The above-described memory system 1100 may be a memory card or a solid state disk (SSD) in which the memory device 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 may include Universal Serial Bus (USB), MultiMedia Card (MMC), Peripheral Component Interconnection-Express (PCI-E), and Serial Advanced Technology Attachment (SATA). ), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), etc. can communicate with

10 is a block diagram showing the configuration of a computing system according to an embodiment of the present invention.

Referring to FIG. 10 , a computing system 1200 according to an embodiment of the present invention includes a CPU 1220 electrically connected to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, and a modem ( 1250) and a memory system 1210. Also, when the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor, a mobile DRAM, and the like may be further included.

The above-described embodiments are only presented as specific examples to easily explain the technical idea of the present invention and help understanding, and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that other modified examples based on the technical idea of the present invention can be implemented in addition to the embodiments disclosed herein.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have meanings commonly understood in the art to which this invention belongs. Unless explicitly defined in the present invention, it is not to be construed in an ideal or overly formal sense.

20: lower film 40: upper film
30, 127, 217: multi-sacrificial layer 33, 121, 211: first material layer
35, 123, 213: second material film 37, 125, 215: third material film
63: fourth material film 61, 165, 285: interlayer space
ILD, 115: interlayer insulating layer CH, 159, 259: channel structure
51, SI1, SI2, SI, 161, 261: slits
SIE, 281: slit extension
CP1 to CPn, CP, 179P: conductive pattern
SL, SL1, SL2, 201, 221: source film
GST: Gate Stack
CTS, 287: contact source film

Claims (17)

forming a first material layer on the lower layer;
forming a second material layer different from the first material layer on the first material layer;
forming a third material layer identical to the first material layer on the second material layer;
forming an upper layer on the third material layer;
forming slits penetrating the upper layer and the first to third material layers;
The first to third material layers are formed with an etchant that etches the first and third material layers faster than the second material layer through the slit to open an interlayer space between the upper layer and the lower layer. removing; and
Filling the interlayer space with a fourth material layer;
While removing the first to third material layers, gaps are formed between the upper layer and the second material layer and between the lower layer and the second material layer to expose a surface of the second material layer. manufacturing method. ◈Claim 2 was abandoned when the registration fee was paid.◈ According to claim 1,
The second material layer is formed to be thicker than each of the first material layer and the third material layer. ◈Claim 3 was abandoned when the registration fee was paid.◈ According to claim 1,
Each of the first material film and the third material film includes at least one of Boron Phosphorus Silicate Glass (BPSG), Undopedsilicata Glass (USG), Phosphorus Silicate Glass (PSG), and a porous nitride film,
The second material layer includes a silicon nitride layer,
The etching material is a method of manufacturing a semiconductor device comprising phosphoric acid (H ₃ PO ₄ ). ◈Claim 4 was abandoned when the registration fee was paid.◈ According to claim 1,
Each of the first material layer and the third material layer includes doped silicon,
The second material layer includes undoped silicon,
The etching material is a method of manufacturing a semiconductor device composed of chemicals including hydrogen fluoride (HF), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH). forming a laminate in which interlayer insulating layers and multiple sacrificial layers are alternately stacked, wherein the multiple sacrificial layers are formed by stacking first material films and second material films that are different from each other;
forming channel structures penetrating the stack;
forming slits passing through the laminate between the channel structures;
removing the multi-sacrificial layer through the slit using an etchant that etches the first material layer faster than the second material layer; and
Filling a region from which the multiple sacrificial layers are removed with a conductive pattern,
A gap exposing a surface of the second material layer is formed between the interlayer insulating layer and the second material layer while the multiple sacrificial layers are removed. ◈Claim 6 was abandoned when the registration fee was paid.◈ According to claim 5,
The second material layer is formed to be thicker than the first material layer. ◈Claim 7 was abandoned when the registration fee was paid.◈ According to claim 5,
The first material film includes at least one of Boron Phosphorus Silicate Glass (BPSG), Undopedsilicata Glass (USG), Phosphorus Silicate Glass (PSG), and a porous nitride film,
The second material layer includes a silicon nitride layer,
The etching material is a method of manufacturing a semiconductor device comprising phosphoric acid (H ₃ PO ₄ ). ◈Claim 8 was abandoned when the registration fee was paid.◈ According to claim 5,
The multi-sacrificial layer further includes a third material layer identical to the first material layer, and the second material layer is disposed between the first material layer and the third material layer. ◈Claim 9 was abandoned when the registration fee was paid.◈ According to claim 8,
The second material layer is formed to be thicker than each of the first material layer and the third material layer. ◈Claim 10 was abandoned when the registration fee was paid.◈ According to claim 8,
Each of the first material film and the third material film includes at least one of Boron Phosphorus Silicate Glass (BPSG), Undopedsilicata Glass (USG), Phosphorus Silicate Glass (PSG), and a porous nitride film,
The second material layer includes a silicon nitride layer,
The etching material is a method of manufacturing a semiconductor device comprising phosphoric acid (H ₃ PO ₄ ). forming a stack in which source layers and multiple sacrificial layers are alternately stacked, wherein the multiple sacrificial layers are formed by stacking first material layers and second material layers that are different from each other;
forming gate stacks penetrated by channel structures on the stack;
forming a slit penetrating the multiple sacrificial layers exposed between the gate stacks;
removing the multi-sacrificial layer through the slit using an etchant that etches the first material layer faster than the second material layer; and
Filling a region from which the multiple sacrificial layers are removed with a contact source layer;
A gap exposing a surface of the second material layer is formed between the source layer and the second material layer while the multiple sacrificial layers are removed. ◈Claim 12 was abandoned when the registration fee was paid.◈ According to claim 11,
The channel structures pass through the multi-sacrificial layer and extend into the source film;
Sidewalls of each of the channel structures are exposed through regions where the multiple sacrificial layers are removed;
The contact source layer is in contact with sidewalls of each of the channel structures. ◈Claim 13 was abandoned when the registration fee was paid.◈ According to claim 11,
The second material layer is formed to be thicker than the first material layer. ◈Claim 14 was abandoned when the registration fee was paid.◈ According to claim 11,
The first material layer includes doped silicon,
The second material layer includes undoped silicon,
The etching material is a method of manufacturing a semiconductor device composed of chemicals including hydrogen fluoride (HF), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH). ◈Claim 15 was abandoned when the registration fee was paid.◈ According to claim 11,
The multi-sacrificial layer further includes a third material layer identical to the first material layer, and the second material layer is disposed between the first material layer and the third material layer. ◈Claim 16 was abandoned when the registration fee was paid.◈ According to claim 15,
The second material layer is formed to be thicker than each of the first material layer and the third material layer. ◈Claim 17 was abandoned when the registration fee was paid.◈ According to claim 15,
Each of the first material layer and the third material layer includes doped silicon,
The second material layer includes undoped silicon,
The etching material is a method of manufacturing a semiconductor device composed of chemicals including hydrogen fluoride (HF), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH).

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