KR102623784B1 - Led pixel package capable of controlling light emitting time - Google Patents

Abstract

The LED pixel package according to the present invention includes a unit pixel including R (Red), G (Green), and B (Blue) LEDs, and a data signal corresponding to the emission time of the R, G, and B LEDs included in the unit pixel, It includes a control circuit that receives a control signal in which a clock signal including a plurality of pulses and an activation signal are embedded and controls a unit pixel.

Description

LED pixel package with controllable light emission time {LED PIXEL PACKAGE CAPABLE OF CONTROLLING LIGHT EMITTING TIME}

The present invention relates to an LED pixel package capable of controlling light emission time.

Recently, in the implementation of commercial outdoor and indoor electronic signboards, there has been a trend toward enlarging the display area of the electronic signboard and increasing the resolution of the display. In addition, there is a trend to adopt LED as a light emitting device to achieve high brightness, high contrast ratio, and good color reproduction.

The need to adopt an active matrix is also emerging for displays using LEDs. In this case, there is an advantage that the number of control pins can be significantly reduced compared to the passive matrix method by controlling the horizontal and vertical axes using active elements rather than directly controlling the LEDs configured in the pixel. Accordingly, the driving circuit for driving is simplified, which is advantageous in reducing pixel size and pixel spacing, and power consumption can also be reduced.

In an LED display, the narrower the spacing between individual LEDs is, the more densely the number of pixels is. As the luminance of individual LEDs is increased, the clarity of the entire display increases, improving image quality. Preferably, when the LED display is implemented as an active matrix, the physical LED displays can be implemented more efficiently in terms of size and cost.

To achieve this, pins for power supply, data input, grounding, etc. must be configured in the LED pixel package. In addition, switch control pins for enable and emission operations of each red LED, green LED, and blue LED must be configured in the LED pixel package. It must be composed.

In a conventional LED pixel package, the luminance of the LED is controlled by the voltage charged in the capacitor. Therefore, the display driving circuit essentially includes a capacitor that stores the emission luminance information of each pixel, which is disadvantageous to linearity of brightness control and has limitations in expressing low luminance in particular.

The problem to be solved with this technology is to solve the problems of the prior art described above and to provide an economical LED pixel package.

The LED pixel package according to the present invention includes a unit pixel including R (Red), G (Green), and B (Blue) LEDs, and a data signal corresponding to the emission time of the R, G, and B LEDs included in the unit pixel, It includes a control circuit that receives a control signal in which a clock signal containing a plurality of pulses and an activation signal are embedded and controls a unit pixel, wherein the control circuit: Separates the activation signal and the clock signal and separates the signals to be output respectively. , is activated by an activation signal, forms R driving time data, G driving time data, and B driving time data from the data signal, and R driving time data, G driving time data, and B driving time are provided by a load signal. A data control unit that latches up and outputs data, receives a clock signal, a load signal, R driving time data, G driving time data, and B driving time data, and outputs data corresponding to the emission times of R, G, and B LEDs. A light emission control unit that forms R, G, and B emission signals with pulse widths and the R, G, and B emission signals are input, and for a time corresponding to the pulse width of the input R, G, and B emission signals, It includes a driving circuit that drives the G and B LEDs to emit light.

As an example of the LED pixel package according to the present invention, the control signal includes an activation signal that swings between a first level and a second level that is greater than the first level, and an activation signal that swings between the second level and a third level that is greater than the second level. A clock signal including a plurality of pulses swinging at is embedded, and the signal separator includes a transistor having a threshold voltage between the first level and the second level to separate the activation signal between the first level and the third level. A clock signal separation circuit that separates the clock signal and outputs it to swing between the first level and the third level, including a transistor having a threshold voltage between the second level and the third level, and an activation signal separation circuit that outputs the signal to swing between the first and third levels. Includes.

As an example of the LED pixel package according to the present invention, the data signal is a signal in which R driving time data, G driving time data, and B driving time data are serially continuous, and the data control unit includes R driving time data, G driving time data, and B driving time data. The driving time data is separated and output in parallel for each bit.

As an example of the LED pixel package according to the present invention, the data control unit includes a shift register that receives serial data signals bit by bit, and R driving time data, G driving time data, and B driving time data output by the shift register. Includes a latch that latches up.

As an example of the LED pixel package according to the present invention, R driving time data, G driving time data, and B driving time data output from the shift register are output in parallel.

As an example of the LED pixel package according to the present invention, the light emission control unit includes a counter that receives a clock signal and counts the number of pulses included in the clock signal, and an R match signal when the R driving time data and the number of pulses match. Outputs a G match signal when the G drive time data and the number of pulses match, and a calculation unit that outputs a B match signal when the B drive time data and the number of pulses match, and provides a load signal. An R emission latch receives a load signal and forms the first edge of the R emission signal, forms the second edge of the R emission signal with the R coincidence signal and outputs it, and receives the load signal to form the first edge of the G emission signal. and a G emission latch that forms and outputs the second edge of the G emission signal with the G coincidence signal, receives the load signal and forms the first edge of the B emission signal, and generates the B emission signal with the B coincidence signal. It includes a B emission latch that forms a second edge and outputs it.

As an example of the LED pixel package according to the present invention, the pulse width from the first edge to the second edge of the R emission signal corresponds to the R driving time data, and the pulse width from the first edge to the second edge of the G emission signal The pulse width corresponds to the G driving time data, and the pulse width from the first edge to the second edge of the B emission signal corresponds to the B driving time data.

As an example of the LED pixel package according to the present invention, the driving circuit unit includes an R driving circuit, a G driving circuit, and a B driving circuit that respectively drive the R, G, and B LEDs included in the unit pixel, and the R driving circuit and the G driving circuit. Each of the circuit and B driving circuit includes an LED driving switch connected to one electrode of the LED, and an emission control switch that provides an emission signal to control conduction of the LED driving switch.

As an example of the LED pixel package according to the present invention, each of the R driving circuit, G driving circuit, and B driving circuit provides a driving voltage through one input, and provides a driving voltage replicated through the other input to the other electrode of the LED driving switch, , an operational amplifier whose output is connected to the control electrode of the LED driving switch, the output of the operational amplifier and one electrode are connected, the ground voltage is connected to the other electrode, and the emission signal is provided to the control electrode and conduction according to the emission signal. It further includes an emission control switch, and when the emission control switch is blocked, the LED driving switch is turned on.

As an example of the LED pixel package according to the present invention, each of the R driving circuit, G driving circuit, and B driving circuit further includes a current limiting resistor that is connected between the other electrode of the LED driving switch and the ground voltage to limit the current provided to the LED. Includes.

As an example of the LED pixel package according to the present invention, the LED pixel package is connected in an active matrix form.

According to the present invention, an advantage is provided in that the brightness emitted by each pixel can be adjusted by adjusting the emission time of the R, G, and B LEDs to correspond to the input signal.

1 is a diagram showing an outline of an LED pixel package according to this embodiment.
Figure 2 is a diagram showing the outline of a control circuit according to this embodiment.
Figure 3(A) is a schematic circuit diagram of the signal separator, and Figure 3(B) is a diagram showing an outline of the control signal and the activation signal and pulse train output from the signal separator.
Figure 4 is a diagram showing an outline of the data control unit.
Figure 5 is a schematic timing diagram of signals input and output to the data control unit.
FIG. 6(a) is a diagram showing an outline of the light emission control unit, and FIG. 6(b) is a timing diagram showing an outline of signals input and output signals to the light emission control unit.
Figure 7 is a circuit diagram illustrating an outline of an R driving circuit that drives the R LED included in the driving circuit unit.
Figure 8 is a diagram showing a state in which LED pixel packages according to this embodiment are arranged in an array and implemented as an active matrix.

Since the description of the present invention is only an example for structural or functional explanation, the scope of the present invention should not be construed as limited by the examples described in the text. In other words, since the embodiments can be modified in various ways and can have various forms, the scope of rights of the present invention should be understood to include equivalents that can realize the technical idea.

Figure 1 is a diagram showing the outline of the LED pixel package 1 according to this embodiment. Referring to FIG. 1, the LED pixel package 1 according to this embodiment includes a unit pixel 10 including R (Red), G (Green), and B (Blue) LEDs whose anodes are commonly connected. and a control circuit 20 that controls the unit pixel 10.

Figure 2 is a diagram showing an outline of the control circuit 20 according to this embodiment. Referring to FIG. 2, the control circuit 20 according to this embodiment receives a data signal (DATA) and a control signal (S_SIG) and controls a unit pixel.

The control circuit 20 is activated by a signal separation unit 100 that separates and outputs the activation signal (ON) and clock signal (CLK) embedded in the control signal (S_SIG), and the activation signal (ON), and generates data Forms R driving time data (R[9:0]), G driving time data (G[9:0]), and B driving time data (B[9:0]) from the signal (DATA), and LOAD ) signal to latch up and output R driving time data (R[9:0]), G driving time data (G[9:0]), and B driving time data (B[9:0]) A data control unit 200, a clock signal (CLK), a load signal (LOAD), R driving time data (R[9:0]), G driving time data (G[9:0]), and B driving time data A light emission control unit that receives (B[9:0]) and forms R, G, and B emission signals (/EMI_R, /EMI_G, /EMI_B) with pulse widths corresponding to the emission times of the R, G, and B LEDs. (300) and R, G and B emission signals (/EMI_R, /EMI_G, /EMI_B) are input, and the time corresponding to the input R, G and B emission signals (/EMI_R, /EMI_G, /EMI_B) It includes a driving circuit unit 400 that drives the R, G, and B LEDs to emit light.

Figure 3(A) is a schematic circuit diagram of the signal separator 100, and Figure 3(B) shows the control signal (S_SIG) and the activation signal (ON) and pulse string (S_OUT) output from the signal separator 110. This is a drawing showing the outline.

Referring to FIGS. 3A and 3B, the control signal S_SIG may swing between a first level, a second level, and a third level. For example, the first level may be a ground voltage level, the third level may be a driving voltage (VCC) level, and the second level may be greater than the threshold voltage of the NMOS transistor included in the signal separation unit 100, It may be a level that is smaller than the third level and smaller than twice the threshold voltage of the NMOS transistor.

The control signal (S_SIG) is a signal in which a pulse train including an activation signal that swings between the ground voltage and the second level and a pulse that swings between the second level and the third level that is the driving voltage (VCC) is embedded.

The signal separation unit 100 includes an activation signal separation circuit 112 that separates the activation signal (ON) from the control signal (S_SIG) and a clock signal separation circuit 114 that separates the clock signal (CLK) from the control signal (S_SIG). Includes.

The activation signal separation circuit 112 includes an inverter (I1) including a resistor (Ra) and a transistor (N1) having a threshold voltage between the first level and the second level, a Schmitt trigger (ST), and an inverter I2 in cascade. connected. The threshold voltage of transistor N1 is greater than the first level but less than the second level. Therefore, when the first level control signal (S_SIG) is input to the inverter (I1), transistor N1 is blocked and outputs a third level logic high signal. However, when the second level or third level control signal (S_SIG) is input to transistor N1, it is conducted. Accordingly, the inverter I1 outputs a first level logic low signal.

A Schmitt trigger is a circuit that does not respond to momentary noise because the output response depending on the size and direction of the input has the characteristics of a hysteresis curve. When the input rises, the output response has a relatively high threshold voltage. When the input falls, the output response is characterized by a relatively low threshold voltage.

The output of Schmitt trigger (ST) is provided to inverter I2 and is a signal that swings between the first and third levels. The output of inverter I2 is an activation signal (ON) that controls activation of the subsequent light emission control unit 120.

The clock signal isolation circuit 114 may include inverters I3 and I4 connected in cascade, and the inverter I3 of the first stage is connected across a ground voltage and a diode-connected NMOS transistor N3. The NMOS transistor N4 included in the inverter I3 is conducted at a voltage that is the sum of the threshold voltage of the diode-connected NMOS transistor N3 and the threshold voltage of transistor N4.

As described above, the voltage obtained by adding the threshold voltage of N3 and the threshold voltage of N4 is greater than the second level. Accordingly, when the control signal (S_SIG) having the first and second levels is provided to the inverter (I3), the NMOS transistor (N4) is not conducted and the inverter (I3) outputs a third level logic high signal. However, when the control signal S_SIG having the third level is provided to the inverter I3, the NMOS transistor N4 is conducted and the inverter I3 outputs a first level logic low signal. Accordingly, the pulse train embedded in the control signal (S_SIG) can be separated. Inverter I4 inverts the output signal of inverter I3 and outputs it as a clock signal (CLK) swinging between the first level and the third level.

FIG. 4 is a diagram showing an outline of the data control unit 200, and FIG. 5 is a schematic timing diagram of signals input and output to the data control unit. Referring to FIGS. 4 and 5, the data control unit 200 includes a shift register 240 that receives a serial data signal (DATA) bit by bit, and R driving time data (R) output by the shift register 240. [9:0]), G driving time data (G[9:0]), and B driving time data (B[9:0]) including a latch unit 250 that latches up by the load signal (LOAD). do.

In the embodiment illustrated in FIGS. 4 and 5, the data signal (DATA) input to the data control unit 200 is 10 bits of R[9:0] corresponding to the driving time of the R LED and the driving time of the G LED. It may include 10 bits of G[9:0] corresponding to it and 10 bits of B[9:0] corresponding to the driving time of the B LED.

The data control unit 200 is reset by an activation signal (ON), receives a clock signal (CLK), and includes a counter 210 that counts pulses included in the clock, and the counting result of the counter 210 is set to a predetermined value. It includes a load signal forming unit 220 that outputs a load signal LOAD when . The predetermined value may correspond to the value at which all bits of the data signal DATA are stored in the shift register 240.

In addition, the data control unit 200 receives an activation signal (ON) and forms a first edge of the clock activation signal (EN), and an SR latch receives a load signal (LOAD) and forms a second edge of the clock activation signal. Includes (230).

Let's look at the operation of the data control unit 200 having this configuration. As the signal separation unit 100 outputs the activation signal (ON), the counter 210 included in the data control unit 200 is reset, and the clock activation signal (EN) output by the SR latch 230 is in a logic high state. is converted to

As the clock activation signal EN switches to the logic high state, the CLK_EN signal is provided to the shift register 240, and each bit of the data signal DATA signal is sequentially stored in the shift register 240.

The reset counter 210 counts the number of pulses included in the clock CLK provided by the signal separation unit 100 and outputs the count. The load signal forming unit 220 outputs a load signal LOAD when the count result output by the counter 210 corresponds to a predetermined value. As an example, the load signal generator may output the load signal LOAD while all bits of the data signal DATA are stored in the shift register 240. In the example illustrated in Figure 4, R, G and B drive time data are each 10 bits. The load signal forming unit 220 receives the result of the counter counting from [0000 0] to [11111] and outputs a load signal (LOAD).

As the load signal (LOAD) is output, the input provided as the Set input of the SR latch is switched to logic low (not shown), the clock activation signal (EN) is switched to logic low, and the clock is transferred to the shift register 240. Not input. In addition, as the load signal LOAD is output, the latch unit 250 generates R driving time data (R[9:0]), G driving time data (G[9:0]), and B driving time data (B[ 9:0]) is latched up for each bit and output.

FIG. 6(a) is a diagram illustrating an outline of the emission control unit 300, and FIG. 6(b) is a timing diagram illustrating an outline of signals input and output signals to the emission control unit 300. Referring to FIGS. 6(a) and 6(b), the light emission control unit 300 includes a counter 310 that is reset by the load signal LOAD and counts the number of pulses included in the clock signal CLK. Whether the coefficient result output by (310) matches the R driving time data (R[9:0]), G driving time data (G[9:0]), and B driving time data (B[9:0]) A calculation unit 320 that calculates and a load signal (LOAD) and an SR latch 332 that forms an R emission signal (EMI_R) according to the matching signal output by the calculation unit 320, a load signal (LOAD) and the calculation unit 320 SR latch 334 forms a G emission signal (EMI_G) according to the matching signal output by ), and forms a B emission signal (EMI_B) according to the matching signal output by the load signal (LOAD) and the operation unit 320. It includes an SR latch 336 that does.

As the data control unit 200 outputs the load signal LOAD, the counter 310 is reset, and the counter 310 counts the number of pulses included in the clock signal CLK and outputs the count. In addition, the R emission signal (EMI_R), emission signal (EMI_G), and B emission signal (EMI_B) output from the SR latches (332, 334, and 336) have rising edges and change from logic low to logic high. It changes.

As the data control unit 200 outputs the load signal (LOAD), R driving time data (R[9:0]), G driving time data (G[9:0]), and B driving time data (B[9:0]) 0]) is provided to the coincidence signal calculation unit 320. The coincidence signal operation unit 320 includes R driving time data (R[9:0]), G driving time data (G[9:0]), and B driving time data (B[9:0]) and the counter 310. If the coefficient results match, a match signal is output.

As an example, R driving time data (R[9:0]) is [1111 1111 01], G driving time data (G[9:0]) is [1111 1111 11], and B driving time data (B[9:0]) is [1111 1111 01]. :0]) corresponds to [1111 1111 10], the operation unit 320 sends an R match signal to the SR latch 332 when the number of clocks (CLK) counted by the counter 310 reaches 1024(?). Output to the Reset input of . The SR latch 332 forms a second edge to change the state of the R emission signal (EMI_R).

When the number of clocks (CLK) counted by the counter 310 reaches 1024 (?), the operation unit 320 outputs a G match signal to the Reset input of the SR latch 334. The SR latch 334 changes the state of the G emission signal (EMI_G) by forming the second edge of the G emission signal. Likewise, when the number of clocks (CLK) counted by the counter 310 reaches 1023 (?), the operation unit 320 outputs a B match signal to the SR latch 336 to determine the state of the B emission signal (EMI_B). change

Therefore, the R emission signal (EMI_R), G emission signal (EMI_G), and B emission signal (EMI_B) are R driving time data (R[9:0]), respectively, as illustrated in FIG. 6(b). It has pulse widths corresponding to G driving time data (B[9:0]) and B driving time data (B[9:0]).

FIG. 7 is a circuit diagram illustrating an outline of the R driving circuit 410R that drives the R LED included in the driving circuit unit 400. As illustrated in FIG. 2, the driving circuit unit 400 includes an R driving circuit 410R for driving the R LED, a G driving circuit 410G for driving the G LED, and a B driving circuit 410B for driving the B LED. do. Since the R driving circuit 410R, G driving circuit 410G, and B driving circuit may have the same configuration, the R driving circuit 410R will be described below as an example for easy understanding.

Referring to FIG. 7, the R driving circuit 410R may include an LED driving switch 412, an emission control switch 414, and an operational amplifier 416. As the R emission signal (/EMI_R) is maintained in the logic high state, the emission control switch 414 is turned on to maintain the voltage of the output node of the operational amplifier 416 at the ground voltage (GND). Therefore, the LED driving switch 412 is blocked and the R LED does not emit light.

As the logic low R emission signal (/EMI_R) is provided, the emission control switch 414 is blocked. Accordingly, the voltage at the output node of the operational amplifier 416 remains logic high and the LED drive switch 412 conducts. Additionally, the driving voltage (Vref) is replicated at the non-inverting input of the operational amplifier 416 and provided to the source electrode of the LED driving switch 412. Accordingly, current (i) flows through the current limiting resistor (Rlimit) to provide driving power to the R LED.

The current (i) flowing through the LED can be expressed as Equation 1 below.

As shown in Equation 1, the value of the current (i) can be limited by adjusting the resistance value of the current limiting resistor (Rlimit), and the luminance of the R LED can be controlled therefrom.

In this embodiment, R driving time data (R[9:0]), G driving time data (G[9:0]), and B driving time data (B[9:0]) provided as data signals (DATA). ), the pulse width of the R emission signal (EMI_R), G emission signal (EMI_G), and B emission signal (EMI_B) can be controlled. From this, the time during which the R LED, G LED, and B LED emit light can be adjusted, thereby controlling the emission luminance of R, G, and B.

FIG. 8 is a diagram illustrating a state in which the LED pixel packages 1 according to this embodiment are arranged in an array and implemented as an active matrix. Referring to FIG. 8, the same control signal (S_SIG) is provided to LED pixel packages arranged in the same row, and the same data signal (DATA) is provided to LED pixel packages arranged in the same column.

Accordingly, the LED pixel package array according to this embodiment implemented as an active matrix provides control signals (S_SIG) and data signals (DATA), so that light emission data is provided individually and can be controlled to emit light simultaneously.

The present invention has been described with reference to the embodiments shown in the drawings to aid understanding of the present invention, but these are embodiments for implementation and are merely illustrative, and various modifications and equivalents can be made by those skilled in the art. It will be appreciated that other embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the appended claims.

1: LED pixel package 10: Unit pixel
20: control circuit 100: signal separation unit
112: activation signal separation circuit 114: clock signal separation circuit
200: data control unit 210: counter
220: load signal forming unit 230: SR latch
240: shift register 250: latch unit
300: Light emission control unit 310: Counter
320: operation unit 332, 334, 336: latch
400: Driving circuit part 412: LED driving switch
414: Emission control switch 416: Operational amplifier (416)

Claims (5)

A unit pixel including R (Red), G (Green) and B (Blue) LEDs and
Data signals corresponding to the emission times of the R, G and B LEDs included in the unit pixel;
A control circuit that receives a control signal in which a clock signal including a plurality of pulses and an activation signal are embedded and controls the unit pixel,
The control circuit is:
a signal separator that separates the activation signal and the clock signal and outputs them respectively;
It is activated by the activation signal, forms R driving time data, G driving time data, and B driving time data from the data signal, and generates the R driving time data, G driving time data, and B driving time as a load signal. a data control unit that latches up and outputs data;
R, G, and B emissions having pulse widths corresponding to the emission times of the R, G, and B LEDs by receiving the clock signal, the load signal, and the R driving time data, G driving time data, and B driving time data. A light emission control unit that forms a signal; and
A driving circuit unit that receives the R, G, and B emission signals and drives the R, G, and B LEDs to emit light for a time corresponding to the pulse width of the input R, G, and B emission signals. ,
The control signal is,
the activation signal swinging between a first level and a second level greater than the first level, and a plurality of pulses swinging between the second level and a third level greater than the second level. A clock signal is embedded,
The signal separator,
An activation signal separation circuit including a transistor having a threshold voltage between the first level and the second level to separate the activation signal and output it to swing between the first level and the third level;
A clock signal separation circuit including a transistor having a threshold voltage between the second level and the third level to separate the clock signal and output the clock signal to swing between the first level and the third level,
The light emission control unit,
a counter that receives the clock signal and counts the number of pulses included in the clock signal;
An R match signal is output when the R drive time data and the number of pulses match, a G match signal is output when the G drive time data and the number of pulses match, and the B drive time data and the pulse It has an operation unit that outputs a B match signal when the number of matches,
An R emission latch that receives the load signal and forms a first edge of the R emission signal, forms a second edge of the R emission signal with the R coincidence signal and outputs it, and receives the load signal and generates a G emission A G emission latch that forms the first edge of the Sean signal, forms the second edge of the G emission signal with the G coincidence signal and outputs it, and receives the load signal and forms the first edge of the B emission signal. and a B emission latch that forms a second edge of the B emission signal with the B coincidence signal and outputs it,
The pulse width from the first edge to the second edge of the R emission signal corresponds to the R driving time data, and the pulse width from the first edge to the second edge of the G emission signal corresponds to the G driving time data. Corresponds to, the pulse width from the first edge to the second edge of the B emission signal corresponds to the B driving time data,
The driving circuit part,
An R driving circuit, a G driving circuit, and a B driving circuit respectively drive the R, G, and B LEDs included in the unit pixel, wherein the R driving circuit, the G driving circuit, and the B driving circuit each include:
An LED driving switch connected to one electrode of the LED; an emission control switch provided with the emission signal to control conduction of the LED driving switch; an operational amplifier that provides a driving voltage as one input, provides the duplicated driving voltage as another input to another electrode of the LED driving switch, and has an output connected to a control electrode of the LED driving switch; the emission control switch, in which one electrode is connected to the output of the operational amplifier, a ground voltage is connected to the other electrode, and the emission signal is provided as a control electrode to be conducted according to the emission signal; and a current limiting resistor connected between the other electrode of the LED driving switch and the ground voltage to limit the current provided to the LED, wherein when the emission control switch is turned off, the LED driving switch is turned on,
The data control unit,
A shift register that receives a data signal in which the R driving time data, G driving time data, and B driving time data are serially continuous, bit by bit,
a latch unit that latches up the R driving time data, G driving time data, and B driving time data output from the shift register;
A counter that is reset by an activation signal, receives a clock signal, and counts pulses included in the clock;
a load signal forming unit that outputs a load signal when the counting result of the counter reaches a predetermined value;
An SR latch receiving the activation signal and forming a first edge of the clock activation signal, and receiving the load signal and forming a second edge of the clock activation signal,
The R driving time data, G driving time data, and B driving time data are separated and output in parallel for each bit,
The data signal is,
10 bits of R[9:0] corresponding to the driving time of the R LED, 10 bits of G[9:0] corresponding to the driving time of the G LED, and B[9:0] corresponding to the driving time of the B LED Contains 10 bits of
An LED pixel package characterized by being connected in an active matrix form. delete delete delete delete

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