CN115836343A

CN115836343A - LED pixel package with controllable light emitting time

Info

Publication number: CN115836343A
Application number: CN202180001973.5A
Authority: CN
Inventors: 金钟善; 李龙云; 尹炳震
Original assignee: Beijing Xinneng Electronic Technology Co ltd
Current assignee: Beijing Xinneng Electronic Technology Co ltd
Priority date: 2021-06-29
Filing date: 2021-06-30
Publication date: 2023-03-21
Also published as: WO2023277214A1; KR20230001717A; KR102623784B1

Abstract

The LED pixel package according to the present invention includes: data signals corresponding to light emitting times of the unit pixels of the R (red), G (green), and B (blue) LEDs and R, G and B LEDs included in the unit pixels; and a control circuit which receives a control signal embedded with a clock signal including a plurality of pulses and an activation signal to unit pixels.

Description

LED pixel package with controllable light emitting time

Technical Field

The invention relates to an LED pixel package with controllable light-emitting time.

Background

Recently, the electronic signage in the outdoor and indoor of the business tends to increase the area of the electronic display screen and improve the display resolution. In addition, LEDs are employed as light emitting elements for achieving high luminance, high contrast, and good color reproducibility.

In a display screen using LEDs, the necessity of employing an Active Matrix (Active Matrix) is increasingly highlighted. In this case, the horizontal and vertical axes are controlled using the active element, instead of using a method of directly controlling the LEDs constituting the pixels, thereby having an advantage that the number of control pins can be significantly reduced compared to the passive matrix method. Accordingly, since the driving circuit for driving is very simplified, it is very advantageous to reduce the pixel size and the pixel pitch, and also to reduce the power consumption.

In the LED display panel, the number of pixels is denser as the interval between each LED is narrower, and the definition of the entire display is increased as the luminance of each LED is increased, so that the picture quality is improved. Preferably, if the LED display screen is implemented with an active matrix, the LED display screen can be implemented more efficiently in terms of physical size or cost.

For this reason, pins for power supply, data input, ground, and the like must be configured in the LED pixel package. In addition, switch control pins for enabling and emission operations of the red LED, the green LED, and the blue LED, respectively, must be provided in the LED pixel package.

Disclosure of Invention

Technical problem

In a conventional LED pixel package, the brightness of the LED is controlled by the voltage charged in the capacitor. Accordingly, the display driving circuit must include a capacitor for storing luminance information of each pixel, but this is disadvantageous to linearity of luminance control, and particularly has a limitation to display of low luminance.

The problem to be solved by the present technology is to provide an economical LED pixel package by solving the problems of the prior art.

Technical scheme

The LED pixel package according to the present invention includes: data signals corresponding to light emitting times of the unit pixels of the R (red), G (green), and B (blue) LEDs and R, G and B LEDs included in the unit pixels; and a control circuit receiving a control signal embedded (embed) with a clock signal including a plurality of pulses and an activation signal to control the unit pixel, wherein the control circuit includes: a signal separation unit which separates and outputs an activation signal and the clock signal; a data control part which is activated by the activation signal, forms R driving time data, G driving time data, and B driving time data from the data signal, and outputs the R driving time data, the G driving time data, and the B driving time data after being latched (latch up) as a load signal; and a driving circuit section to which R, G, B emission signals are input and which drives R, G and the B LED to emit light during a pulse width corresponding to the input R, G and B emission signals.

As an example of an LED pixel package according to the present invention, a control signal is embedded with: an activation signal that swings (swing) between a first level and a second level that is greater than the first level; and a clock signal including a plurality of pulses that swing between a second level and a third level that is greater than the second level, and the signal separating section includes: an activation signal separation circuit including a transistor having a threshold voltage between a first level and a second level to separate an activation signal and output it to swing between the first level and a third level; and a clock signal splitting circuit including a transistor of a threshold voltage between the second level and the third level to split the clock signal and output it to swing between the first level and the third level.

As an example of the LED pixel package according to the present invention, the data signal is a signal in which R driving time data, G driving time data, and B driving time data are serially continuous, and the data control section separates the R driving time data, the G driving time data, and the B driving time data, and then separates them in parallel for each bit to output them.

As an example of the LED pixel package according to the present invention, the data control section includes: a shift register which receives a data signal in serial succession for each bit; and a latch for latching the R driving time data, the G driving time data, and the B driving time data output from the shift register.

As an example of the LED pixel package according to the present invention, R driving time data, G driving time data, and B driving time data output from a shift register are output in parallel.

As an example of the LED pixel package according to the present invention, the light emission control section includes: a counter that receives the clock signal and counts a number of pulses included in the clock signal; and an operation part outputting an R matching signal when R driving time data matches a pulse number, outputting a G matching signal when G driving time data matches the pulse number, and outputting a G matching signal when B driving time data matches the pulse number, a pulse matching B matching signal, wherein the light emission control part further includes: an R-launch latch that receives the load signal to form a first edge of the R-launch signal and that is formed with the R-match signal to output a second edge of the R-launch signal; a G-launch latch that receives the load signal to form a first edge of the G-launch signal; a G-launch latch that forms and outputs a second edge of the G-launch signal with the G-match signal; and a B-launch latch that receives the load signal and forms a first edge of the B-launch signal, and forms and outputs a second edge of the B-launch signal with the B-match signal.

As an example of the LED pixel package according to the present invention, a pulse width from a first edge to a second edge of the R emission signal corresponds to the R driving time data, a pulse width from a first edge to a second edge of the G emission signal corresponds to the G driving time data, and a width from a first edge to a second edge of the B emission signal corresponds to the B driving time data.

As an example of the LED pixel package according to the present invention, the driving circuit section includes an R driving circuit, a G driving circuit, and a B driving circuit for R, G and the B LED included in the driving section pixel, respectively, and the R driving circuit, the G driving circuit, and the B driving circuit include: a driving switch connected to the LED of one electrode of the LED; and a light emission control switch supplied with the emission signal to control the LED driving switch to be turned on.

As an example of the LED pixel package according to the present invention, the LED pixel package further includes: an operational amplifier which supplies as one input driving voltages to the R driving circuit, the G driving circuit, and the B driving circuit, respectively, and supplies the driving voltage copied as the other input terminal to the other electrode of the LED driving switch, while the output terminal is connected to the control electrode of the LED driving switch; and a transmission control switch having an output terminal of the operational amplifier connected to one electrode and a ground voltage connected to the other electrode, the transmission signal being supplied to the control electrode so as to be turned on in response to the transmission signal. Wherein if the emission control switch is turned off, the LED driving switch is turned on.

As an example of the LED pixel package according to the present invention, the R driver circuit, the G driver circuit, and the B driver circuit each further include: and a current limiting resistor connected between the other electrode of the LED driving switch and a ground voltage to limit a current supplied to the LED.

As an example of the LED pixel package according to the present invention, the LED pixel package is connected in an active matrix form.

Effects of the invention

According to the present invention, the luminance of each pixel can be adjusted corresponding to an input signal by adjusting the light emitting time of R, G and the B LED.

Drawings

Fig. 1 is a diagram showing an outline of an LED pixel package according to the present embodiment;

fig. 2 is a diagram showing an outline of a control circuit according to the present embodiment;

fig. 3 (a) is a schematic circuit diagram of the signal separating section, and fig. 3 (B) is a diagram showing an outline of a control signal, an activation signal, and a pulse train output from the signal separating section;

fig. 4 is a diagram showing an outline of the data control section;

fig. 5 is a schematic timing chart of signals input and output to the data control section;

fig. 6 (a) is a diagram showing an outline of the light emission control section, and fig. 6 (b) is a timing chart showing an outline of input and output of signals to and from the light emission control section;

fig. 7 is a circuit diagram schematically showing an R drive circuit for driving the R LED included in the drive circuit section;

fig. 8 is a diagram showing a state in which the LED pixel packages according to the present embodiment are configured in an array and implemented as an active matrix.

Best mode for carrying out the invention

An LED pixel package with controllable light emitting time according to an embodiment of the present invention is characterized by comprising: data signals corresponding to light emitting times of the unit pixels of the R (red), G (green), and B (blue) LEDs and R, G and B LEDs included in the unit pixels; and a control circuit that receives a control signal embedded (embedded) with a clock signal including a plurality of pulses and an activation signal to unit pixels.

Detailed Description

Since the description of the present invention is merely a structural or functional description of an embodiment, the scope of the present invention should not be construed as being limited to the embodiments described herein. That is, the embodiments can be variously modified and can have various forms, and therefore it should be understood that the scope of the present invention includes equivalents that can achieve the technical spirit.

Fig. 1 is a diagram showing an outline of an LED pixel package according to the present embodiment. Referring to fig. 1, an LED pixel package 1 of the present embodiment includes: a unit pixel 10 including R (red), G (green), and B (blue) LEDs whose anodes (anode) are commonly connected; and a control circuit 20 that controls the unit pixel 10.

Fig. 2 is a diagram showing an outline of a control circuit according to the present embodiment. Referring to fig. 2, the control circuit 20 according to the present embodiment receives a DATA signal (DATA) and a control signal (S _ SIG) and controls a unit pixel.

The control circuit section 20 includes: a signal separation section 100 that separates and outputs an activation signal (ON) and a clock signal (CLK) each embedded in a control signal (S _ SIG); a DATA control unit which is activated by an activation signal (ON), forms R drive time DATA (R9:0), G drive time DATA (G9:0), and B drive time DATA (B9:0) from a DATA signal (DATA), and latches (latch up) the R drive time DATA (R9:0), the G drive time DATA (G9:0), and the B drive time DATA (B9:0) with a LOAD (LOAD) signal and outputs the DATA; a light emission control section 300 that receives a clock signal (CLK), a LOAD signal (LOAD) and R drive time data (R9:0), G drive time data (G9:0) and B drive time data (B9:0) to form R, G and B emission signals (/ EMI _ R,/EMI _ G,/EMI _ B) having pulse widths corresponding to light emission times of R, G and BLED; and a driving circuit section 400 to which R, G and B emission signals (/ EMI _ R,/EMI _ G,/EMI _ B) are input, and which drives R, G and B LED to emit light for a time corresponding to input R, G and B emission signals (/ EMI _ R,/EMI _ G,/EMI _ B).

Fig. 3 (a) is a schematic circuit diagram of the signal separating unit, and fig. 3 (B) is a diagram showing an outline of the control signal, the activation signal, and the pulse train output from the signal separating unit.

Referring to fig. 3 (a) and 3 (B), the control signal (S _ SIG) may swing (swing) between a first level, a second level, and a third level. As an example, the first level may be a ground voltage level, the third level may be a driving Voltage (VCC) level, the second level is higher than a threshold voltage of an NMOS transistor included in the signal separating part 100 but lower than the third level, and may be less than twice the threshold voltage of the NMOS transistor.

The control signal (S _ SIG) is a pulse train embedded with pulses including an activation signal swinging between a ground voltage and a second level and a pulse swinging between the second level and a third level as a driving Voltage (VCC).

The signal separating section 100 includes: an activation signal separation circuit 112 that separates an activation signal (ON) from a control signal (S _ SIG); and a clock signal separation circuit 114 that separates the clock signal (CLK) from the control signal (S _ SIG).

The activation signal separation circuit 112 includes a cascade of a resistor (Ra) and a transistor (N1) having a threshold voltage between a first level and a second level, and a Schmitt Trigger (ST) and an inverter (I2). The threshold voltage of the transistor (N1) is greater than the first level but less than the second level. Accordingly, if the first level control signal (S _ SIG) is input to the inverter (N1), the transistor (N1) is turned off, thereby outputting a third level logic high signal. However, if the second level or third level control signal (S _ SIG) is input to the transistor (N1), it is turned on. Accordingly, the inverter (N1) outputs a logic low signal of a first level.

Schmitt trigger (schmitt trigger) is a circuit that does not respond to transient noise because the output response according to the magnitude and direction of the input has the characteristics of a hysteresis curve. When the input rises, the response of the output has a relatively high threshold voltage, and when the input falls, the response of the output has a relatively low threshold voltage.

The output of the Schmitt Trigger (ST) is a signal supplied to an inverter (I2) and oscillating between a first level and a third level. The output of the inverter (I2) is an activation signal (ON) for controlling the subsequent activation of the light emission control section 120.

The clock signal separation circuit 114 may include cascaded inverters (I3, I4), and the inverter (I3) of the first stage is connected to a ground voltage via an NMOS transistor (N3) diode-connected. The NMOS transistor (N4) included in the inverter (I3) is turned on at a voltage obtained by adding the threshold voltage of the diode-connected NMOS transistor (N3) and the threshold voltage of the transistor (N4).

As described above, the voltage obtained by adding the threshold voltage of N3 and the threshold voltage of N4 is greater than the second level. Accordingly, if the control signal (S _ SIG) having the first and second levels is supplied to the inverter (I3), the NMOS transistor (N4) is not turned on and the inverter (I3) outputs a logic high signal of the third level. However, if the control signal (S _ SIG) having the third level is supplied to the inverter (I3), the NMOS transistor (N4) is turned on and the inverter (I3) outputs a logic low signal of the first level. Accordingly, the burst embedded in the control signal (S _ SIG) can be separated. The inverter (I4) inverts the output signal of the inverter (I3) and outputs the inverted output signal as a clock signal (CLK) swinging between a first level and a third level.

Fig. 4 is a diagram showing an outline of the data control section, and fig. 5 is a schematic timing chart of signals input and output to the data control section. Referring to fig. 4 and 5, the DATA control part 200 includes a shift register 240 receiving serially continuous DATA signals (DATA) for each bit; and a latch section 250 that latches the R drive time data (R [9:0 ]), the G drive time data (G [9:0 ]) and the B drive time data (B [9:0 ]) output from the shift register 240 by a load signal.

In the embodiments shown in fig. 4 and 5, the DATA signal (DATA) input to the DATA control part 200 may include: 10 bits of R [9:0] corresponding to the drive time of the R LED, 10 bits of G [9:0] corresponding to the drive time of the G LED, and 10 bits of B [9:0] corresponding to the drive time of the B LED.

The data control unit 200 includes: a counter 210 which receives a clock signal (CLK) after being reset (reset) to an activation signal (ON) and counts pulses included in the clock; and a LOAD signal forming part 220 outputting a LOAD signal (LOAD) when a count result of the counter 210 reaches a predetermined value. The predetermined value may correspond to a value at which all bits of the DATA signal (DATA) are stored in the shift register 240.

In addition, the data control unit 200 includes: the SR latch 230 receives the activation signal (ON) to form a first edge of the clock activation signal (EN) and receives the LOAD signal (LOAD) to form a second edge of the clock activation signal.

The operation of the data control section 200 having such a configuration is described below. The counter 210 included in the data control part 200 is reset as the signal separating part 100 outputs the active signal (ON), and the clock active signal (EN) output from the SR latch 230 transitions to a logic high state.

With the clock enable signal (EN) transitioning to a logic high state, the CLK _ EN signal is provided to the shift register 240 and each bit of the DATA signal (DATA) signal is stored sequentially in the shift register 240.

The reset counter 210 counts the number of pulses included in the Clock (CLK) supplied from the demultiplexer 100 and outputs the counted number. The LOAD signal forming part 220 outputs a LOAD signal (LOAD) if the count result output from the counter 210 corresponds to a predetermined value. As an example, the LOAD signal forming part may output the LOAD signal (LOAD) in a state where all bits of the DATA signal (DATA) are stored in the shift register 240. In the example shown in fig. 4, R, G and B drive time data are both 10 bits. The LOAD signal forming part 220 receives the result of the counter counting from [0000 0] to [11111] and outputs a LOAD signal (LOAD).

With the LOAD signal (LOAD) output, the input provided to the set input terminal of the SR latch is converted to a logic low (not shown), and the clock enable signal (EN) is converted to a logic low, while the clock is not input to the shift register 240. Further, the latch section 250 latches and outputs R drive time data (R [9:0 ]), G drive time data (G [9:0 ]), and B drive time data (B [9:0 ]) as the LOAD signal (LOAD) is output.

Fig. 6 (a) is a diagram showing an outline of the light emission control unit, and fig. 6 (b) is a timing chart showing an outline of input and output of signals to and from the light emission control unit. Referring to fig. 6 (a) and 6 (b), the light emission control section 300 includes: a counter 310 that counts the number of pulses included in the clock signal (CLK) after the LOAD signal (LOAD) is reset; an arithmetic unit 320 for calculating whether or not the count result outputted from the counter 310 matches the R drive time data (R [9:0 ]), the G drive time data (G [9:0 ]), and the B drive time data (B [9:0 ]); and an SR latch 332 forming an R transmission signal (EMI _ R) based on the LOAD signal (LOAD) and the matching signal output from the operation section 320, an SR latch 334 forming a G transmission signal (EMI _ G) based on the LOAD signal (LOAD) and the matching signal output from the operation section 320, and an SR latch 336 forming a B transmission signal (EMI _ B) based on the LOAD signal (LOAD) and the matching signal output from the operation section 320.

The counter 310 is reset as the data control part 200 outputs the LOAD signal (LOAD). The counter 310 counts the number of pulses included in the clock signal (CLK) and outputs the counted number. In addition, the R emission signal (EMI _ R), the emission signal (EMI _ G), and the B emission signal (EMI _ B) output by the SR latches 332, 334, 336 form a rising edge and change from a logic low state to a logic high state.

As the data control section 200 outputs the LOAD signal (LOAD), R drive time data R [9:0], G drive time data G [9:0], and B drive time data B [9:0] are supplied to the matching signal calculation section 320. If the R drive time data (R [9:0 ]), the G drive time data (G [9:0 ]) and the B drive time data (B [9:0 ]) match with the result of the count by the counter 310, a matching signal is output.

As an example, when R drive time data (R [9:0 ]) corresponds to [1111 1111 01], G drive time data (G [9:0 ]) corresponds to [1111 1111 11], and B drive time data (B [9:0 ]) corresponds to [1111 1111 10], if the number of Clocks (CLK) counted by the counter 310 reaches 1024 (?, the arithmetic section 320 outputs an R match signal to the reset input terminal of the SR latch 332. The SR latch 332 forms a second edge to change the state of the R transmit signal (EMI _ R).

If the number of Clocks (CLK) counted by the counter 310 reaches 1024 (. The SR latch 334 forms a second edge of the G transmit signal to change the state of the G transmit signal (EMI _ G). Likewise, if the number of Clocks (CLK) counted by the counter 310 reaches 1023 (.

Accordingly, as shown in fig. 6 (B), the R emission signal (EMI _ R), the G emission signal (EMI _ G), and the B emission signal (EMI _ B) have pulse widths corresponding to the R drive time data (R [9:0 ]), the G drive time data (B [9:0 ]), and the B drive time data (B [9:0 ]), respectively.

Fig. 7 is a circuit diagram schematically showing an R drive circuit for driving the R LED included in the drive circuit section. As shown in fig. 2, the driving circuit section 400 includes: an R drive circuit (410R) for driving the R LED, a G drive circuit (410G) for driving the G LED, and a B drive circuit (410B) for driving the BLED. The R drive circuit (410R), the G drive circuit (410G), and the B drive circuit may have the same configuration, and the R drive circuit (410R) is exemplarily described below for ease of understanding.

Referring to fig. 7,R drive circuit (410R) may include LED drive switch 412, emission control switch 414, and operational amplifier 416. The emission control switch 414 is turned on to maintain the voltage of the output node of the operational amplifier 416 at the ground voltage (GND) with the R emission signal (/ EMI _ R) maintained at the logic high state. Accordingly, the LED driving switch 412 is turned off and the R LED does not emit light.

The emission control switch 414 is turned off as a logic low R emission signal (/ EMI _ R) is provided. Accordingly, the voltage at the output node of the operational amplifier 416 remains in a logic high state and the LED drive switch 412 is turned on. In addition, the driving voltage (Vref) is provided to the source of the LED driving switch 412 after being copied to the non-inverting input of the operational amplifier 416. Thus, the current (i) is supplied with the driving power through the current limiting resistor (Rlimit) red LED.

The current (i) flowing on the LED can be displayed as shown in equation 1 below.

[ EQUATION 1]

As shown in equation 1, the value of the current (i) may be limited by adjusting the resistance value of the current limiting resistor (Rlimit), and thus the light emission luminance of the R LED may be controlled.

In the present embodiment, the pulse widths of the R emission signal (EMI _ R), the G emission signal (EMI _ G), and the B emission signal (EMI _ B) can be controlled by adjusting R drive time DATA (R [9:0 ]), G drive time DATA (G [9:0 ]), and B drive time DATA (B [9:0 ]) supplied as the DATA signal (DATA). Therefore, the time for emitting light of the R LED, the G LED and the B LED can be controlled, and the light emitting brightness of R, G and B is controlled.

Fig. 8 is a diagram showing a state in which the LED pixel package according to the present embodiment is configured in an array and implemented as an active matrix. Referring to fig. 8, the same control signal (S _ SIG) is supplied to the LED pixel packages arranged in the same row, and the same DATA signal (DATA) is supplied to the LED pixel packages arranged in the same column.

Accordingly, the LED pixel package array according to the present embodiment implemented as an active matrix may be controlled to emit light while being separately supplied with light emission DATA by supplying a control signal (S _ SIG) and a DATA signal (DATA).

The description has been made with reference to the embodiments shown in the drawings in order to assist understanding of the invention, but this is for the embodiment to be carried out and is exemplary only. It will be appreciated by those of ordinary skill in the art that various modifications and equivalent other embodiments may be made thereto. Accordingly, the appended claims should be construed to cover all such modifications and changes as fall within the true spirit of the invention.

Claims

1. An LED pixel package, comprising:

the LED pixel package according to the present invention includes:

data signals corresponding to light emitting times of the unit pixels of the R (red), G (green), and B (blue) LEDs and R, G and B LEDs included in the unit pixels; and

a control circuit receiving a control signal embedded with a clock signal including a plurality of pulses and an activation signal to control the unit pixel,

wherein the control circuit comprises:

a signal separation section that separates the output activation signal and the clock signal;

a data control part which is activated by the activation signal, forms R driving time data, G driving time data, and B driving time data from the data signal, and outputs the R driving time data, the G driving time data, and the B driving time data as a load signal after being latched;

a light emission control section that receives the clock signal, the load signal, and the R, G, and B drive time data to form R, G and B emission signals having pulse widths corresponding to light emission times of the R, G and B LEDs; and

a drive circuit section to which the R, G, B emission signal is input and which drives R, G and B LEDs to emit light during a pulse width corresponding to the R, G and B emission signal input,

wherein the control signal is embedded with:

the activation signal swings between a first level and a second level that is greater than the first level; and

the clock signal comprising a plurality of pulses that swing between the second level and a third level that is greater than the second level,

wherein the signal separating part includes:

an activation signal separation circuit including a transistor having a threshold voltage between the first level and the second level to separate the activation signal and output it to swing between the first level and the third level; and

a clock signal separation circuit including a transistor of a threshold voltage between the second level and the third level to separate the clock signal and output it to swing between the first level and the third level,

wherein the light emission control section is provided with:

a counter that receives the clock signal and counts a number of pulses included in the clock signal; and

an operation part for outputting an R matching signal when the R driving time data matches the pulse number, outputting a G matching signal when the G driving time data matches the pulse number, outputting a G matching signal when the B driving time data matches the pulse number, pulse matching a B output matching signal,

wherein the light emission control section further includes:

an R-fire latch that receives the load signal to form a first edge of an R-fire signal and forms and outputs a second edge of the R-fire signal with the R-match signal;

a G-launch latch that receives the load signal to form a first edge of a G-launch signal and forms and outputs a second edge of the G-launch signal with the G-match signal; and

a B-launch latch that receives the load signal to form a first edge of a B-launch signal and forms and outputs a second edge of the B-launch signal with the B-match signal,

wherein a pulse width from a first edge to a second edge of the R emission signal corresponds to the R driving time data, a pulse width from a first edge to a second edge of the G emission signal corresponds to the G driving time data, a pulse width from a first edge to a second edge of the B emission signal corresponds to the B driving time data,

wherein the driving circuit section includes an R driving circuit, a G driving circuit, and a B driving circuit for driving R, G and B LEDs included in a unit pixel, respectively,

wherein, R drive circuit, G drive circuit and B drive circuit include respectively: an LED driving switch connected with one electrode of the LED; an emission control switch supplied with the emission signal to control conduction of the LED driving switch; an operational amplifier supplied with a driving voltage as an input and supplying the driving voltage copied as another input to another electrode of the LED driving switch, and an output terminal connected to a control electrode of the LED driving switch; a transmission control switch which connects the output terminal of the operational amplifier and one electrode, and a ground voltage is connected to the other electrode, the transmission signal being supplied to a control electrode to be turned on according to a transmission signal; and a current limiting resistor connected between the other pole of the LED driving switch and a ground voltage to limit a current supplied to the LED, and the LED driving switch is turned on when the light emission control switch is turned off.

2. The LED pixel package of claim 1,

the data signal is a signal in which the R driving time data, the G driving time data and the B driving time data are connected in series,

the data control unit separates the R-drive time data, the G-drive time data, and the B-drive time data, and then separates them in parallel for each bit to output them.

3. The LED pixel package of claim 2,

the data control unit includes:

a shift register which receives the data signals in series for each bit; and

and a latch unit latching the R, G, and B driving time data output from the shift register.

4. The LED pixel package of claim 3,

the R driving time data, the G driving time data and the B driving time data output by the shift register are output in parallel.

5. The LED pixel package of claim 1,

the LED pixel packages are connected in an active matrix configuration.