JPH09244570A - Light emitting diode(led) display driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display driving device capable of carrying out gradation display in which the luminance of the LED(light emitting diode) display is stepwise varied easily only by supplying signals without requiring the direct work such as the replacement of circuit elements and adjustment. SOLUTION: Display serial data 14 are converted to parallel data by a shift register 5. The parallel data are latched by a latch means 6. The parallel data outputted from the means 6 are given to an LED 21 through a gate 7 and an output amplifier 8. A pulse period controlling circuit 23 outputs the signals in which a duty ratio varies in accordance with the changes in the number of pulses within a prescribed time based on a luminance setting signal 24. Then, the output signals are inputted to the gate 7, the duty ratio of the driving signals given to the LED 21 is changed and the luminance of the LED is stepwise varied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for an LED (light emitting diode) display, and more particularly to a driving device capable of gradation display in which brightness is changed stepwise.

[0002]

2. Description of the Related Art A circuit configuration of a conventional LED display driving device is shown in FIG. In the figure, 1 to 4, 9 are buffers, 5 is n
Bit shift register, 6 is an n-bit latch, 7-
1 to 7-n are AND gates, 8-1 to 8-n are output amplifiers, 10 is a current setting circuit, 11 is a resistor, and 12 is a monostable multivibrator IC (hereinafter referred to as "monomulti").
It is. Further, 13 is a clock signal for data shift,
Reference numeral 14 is an input data signal, 15 is a latch signal, 16 is an input signal to the monomulti 12, 12 is an output signal of the monomulti 12, 18 is a current setting terminal, 19-1 to 19-n are output terminals, and 20 is an output. Data signals 21-1 to 21-n are common anode type LEDs, and 22 is an LED driving power supply circuit.

When n-bit serial data as the input data signal 14 is input to the shift register 5 in synchronization with the clock signal 13, the shift register 5 outputs n-bit parallel data. The output parallel data is latched by the latch 6 at the rising edge of the latch signal 15. The n-bit parallel display data output from the latch 6 corresponds to the corresponding AND gates 7-1 to 7-1.
7-n and output amplifiers 8-1 to 8-n are applied to output terminals 19-1 to 19-n. Output terminals 19-1 to 19-1
The cathodes of the corresponding LEDs 21-1 to 21-n are connected to 19-n, respectively, and the common anode of the LEDs 21-1 to 21-n is connected to the LED driving power supply circuit 22.

A common lighting control signal is applied to the other input terminals of the AND gates 7-1 to 7-n. That is, the output control signal 1 for collectively controlling the turning on / off of each LED
The output of the mono-multi IC having 6 as an input is supplied to the other input terminals of the AND gates 7-1 to 7-n through the buffer 4. Further, a common brightness adjustment signal is given to the output amplifiers 8-1 to 8-n. That is, the common output of the current setting circuit 10 that determines the current that flows when the LED is lit is input to the output amplifiers 8-1 to 8-n, and this current value is between the setting terminal 18 of the current setting circuit 10 and GND. It depends on the resistance value of the connected resistor 11.

By the way, it is usual to change the display brightness of the LED display according to the usage conditions. For example,
When the LED display is used outdoors, the display becomes easier to see by increasing the brightness in a bright daytime environment and decreasing the brightness in a dark nighttime environment. The brightness of the LED display element can be changed by changing the current or by changing the duty ratio of pulse driving.

In the conventional LED display driving device having the above-mentioned structure, the current supplied to the LED is the current setting terminal 18
It can be changed by the resistance value of the resistor 11 connected to the. Further, the duty ratio can be changed by changing the pulse width of the output signal of the mono-multi 12. As is well known, the monomulti IC generates an output signal having a pulse width determined by the values of external resistors and capacitors, triggered by the rising edge of the input pulse signal. Therefore, this resistor or capacitor (not shown)
By changing the value of, the pulse width and eventually the duty ratio can be changed.

[0007]

However, in order to change the display brightness of the LED in the conventional circuit configuration, the resistor connected to the current setting terminal, the resistor connected to the mono-multi IC, or the capacitor is replaced, or It had to be adjusted using a variable resistor (capacitor). That is, direct work such as replacement of circuit elements or adjustment was required. Such work is cumbersome and easily causes a failure.

[0008] Therefore, the present invention enables gradation display by simply giving a signal or automatically changing the brightness of the LED display stepwise without requiring the above-mentioned direct work. It is an object to provide an LED display driving device.

[0009]

A first structure of an LED display driving device according to the present invention is to convert display serial data into parallel data by a shift register, latch the parallel data by latch means, and latch the parallel data. Configured to provide the parallel data output from the
A pulse cycle control circuit that outputs a signal whose duty ratio changes by changing the number of pulses within a predetermined time based on a brightness setting signal is provided. By inputting the output signal to the gate, it is given to the LED. It is characterized in that the duty ratio of the drive signal used is changed.

In the second configuration of the LED display driving device according to the present invention, the display serial data is converted into parallel data by the shift register, the parallel data is latched by the latch means, and the parallel data from the latch means is converted. An apparatus configured to give an output to an LED via a gate and an output amplifier, and comprising current setting means for instructing the output amplifier of a current setting value to be supplied to the LED, wherein a predetermined time is set based on a brightness setting signal. A pulse period control circuit that outputs a signal whose duty ratio changes by changing the number of pulses in the pulse period control circuit, and the current setting means supplies a current set value to the LED based on the output signal of the pulse period control circuit. It is characterized by changing.

The pulse cycle control circuit divides the data shift clock supplied to the shift register by one or more stages of frequency dividers, and one or more outputs of the data shift clock and the frequency divider. It is preferable to include a decoder that selects and outputs one of a plurality of types of output signals having different numbers of pulses within a predetermined time by combining the above based on the brightness setting signal. More preferably, the pulse cycle control circuit halves a data shift clock to be given to the shift register.
One of a plurality of types of output signals having different pulse numbers within a predetermined time is obtained by combining three types of signals, that is, a frequency-divided signal and a 1 / 4-frequency-divided signal using a plurality of AND gates and an OR gate. It is configured to select and output one.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 shows an L according to a first embodiment of the present invention.
It is a circuit diagram which shows the structure for 1 bit of an ED display drive device. In FIG. 1, 1 to 4 are input buffers, 5 is a shift register, 6 is a latch, 7 is an AND gate, 8 is an output amplifier, 10 is a current setting circuit, and 22 is an LED driving power supply circuit. 13 is a clock signal for data shift, 23
Is a pulse cycle control circuit, 24 is a luminance information input signal, 18
Is a current setting terminal, 11 is a resistor, 19 is an output terminal, 21 is an LED, 15 is a latch signal, and 16 is an output control signal.

The pulse cycle control circuit 23 outputs gradation data for gradation display for changing the brightness of the LED 21 from the data shift clock signal 13 and the brightness information input signal 24. An example of the circuit is shown in FIG. In FIG. 2, 7a to 7e are AND gates, 25
Is an OR gate, 26a and 26b are 1/2 frequency dividers, and 27 is an inverter.

The data shift clock signal 13 input to the pulse period control circuit 23 is, as shown in FIG.
The signal 29 is divided by 1/2 by the 1/2 divider 26a, and further divided by 1/2 by the 1/2 divider 26b to be a signal 30 divided by 1/4 in total. Original signal 13, 1 /
3 of the signal 29 divided by 2 and the signal 30 divided by 1/4
The clock signals of various types are combined by a decoder circuit including AND gates 7a to 7e, an OR gate 25, and an inverter 27, and output to 28 as grayscale data.

In this embodiment, different gradation data 28 is output depending on the level of the brightness setting signal 24. FIG.
As can be seen from the above, when the brightness setting signal 24 is at the L level, the original signal 13, the 1 / 2-divided signal 29, and 1
A logical product signal 31 of the signal 30 divided by / 4 is selected and becomes the gradation data 28 (see FIG. 3). On the other hand, when the brightness setting signal 24 is at the H level, the logical product signal 32 of the original signal 13 and the 1 / 2-divided signal 29 is selected and becomes the gradation data 28 (see FIG. 4).

Comparing FIG. 3 and FIG. 4, the brightness setting signal 24
It can be seen that the number of pulses of the grayscale data 28 within a predetermined time period changes depending on whether is the H level or the L level. That is, when the brightness setting signal 24 is at the H level, the number of pulses within a predetermined time is twice as large as when the brightness setting signal 24 is at the L level. Since the pulse widths are the same, the duty ratio is changed by a factor of two, which makes it possible to perform gradation display in which a two-step luminance change is given to the LED 21. The pulse cycle control circuit 23 only needs to be able to change the number of pulses (duty ratio) within the same display data period latched by the latch 6, and is not limited to the circuit configuration illustrated in FIG.

(Embodiment 2) Next, FIG. 5 shows a circuit configuration of the entire n-bit LED display drive device according to the second embodiment. Similarly to the conventional example shown in FIG. 12, when n-bit serial data is input as the input data signal 14 to the shift register 5 in synchronization with the clock signal 13, the shift register 5 outputs n-bit parallel data. It The output parallel data is latched by the latch 6 at the rising edge of the latch signal 15. The n-bit parallel display data output from the latch 6 corresponds to the corresponding AND gates 7-1 to 7-n and the output amplifier 8.
It is given to the output terminals 19-1 to 19-n via -1 to 8-n. L corresponding to the output terminals 19-1 to 19-n
The cathodes of the EDs 21-1 to 21-n are respectively connected, and the common anode of the LEDs 21-1 to 21-n is the LED.
It is connected to the driving power supply circuit 22.

A common lighting control signal is connected to the other input terminals of the AND gates 7-1 to 7-n, and a brightness adjustment signal from the current setting circuit 10 common to the output amplifiers 8-1 to 8-n. The fact that is given is also as described in the conventional example. The device of this embodiment is different from the conventional example,
The LED current setting value by the current setting circuit 10 is not determined only by the resistance value of the resistor 11, but the pulse cycle control circuit 2
This is a point in which the gradation display signal (gradation data) from 3 changes in a plurality of steps. The pulse cycle control circuit 23 generates four types of gradation data based on the data shift clock signal 13 and two control signals (luminance setting signals) 24 and 33. FIG. 6 shows an example of the configuration.

In FIG. 6, the clock signal 13 for data shift input to the pulse cycle control circuit 23 is 1 /
The signal 34 is divided by 1/2 by the 2 frequency divider 26a, and further divided by 1/2 by the 1/2 frequency divider 26b, for a total of 1/4.
The divided signal 35 is obtained. Three types of clock signals, the original signal 13, the 1/2 frequency-divided signal 34, and the 1/4 frequency-divided signal 35 are AND gates 7a to 7g and the OR gate 2.
5a, 25b and inverters 27a, 27b are combined by a decoder circuit and output to 40 as gradation data.

In this embodiment, the brightness setting signals 24 and 3
4 kinds of gradation data 4 depending on the combination of 3 levels
0 is output. First, when both the brightness setting signals 24 and 33 are at the L level, the outputs of the three AND gates 7e to 7g input to the OR gate 25b at the final stage of the decoder circuit are all at the L level, so that the L level is always at the L level. Signal is output as gradation data 40 (see FIG. 7).

When the brightness setting signal 24 is at the H level and the brightness setting signal 33 is at the L level, the AND gate 7f is selected and the original signal 13, the 1/2 divided signal 34, and 1 are selected.
A logical product signal 38 of the signal 35 divided by / 4 becomes gradation data 40 (see FIG. 8). When both the brightness setting signals 24 and 33 are at the H level, the AND gate 7g is selected, and the logical product signal 37 of the original signal 13 and the signal 34 divided by 1/2 becomes the gradation data 40 (Fig. 9). When the brightness setting signal 24 is at the L level and the brightness setting signal 33 is at the H level, the AND gate 7e is selected, and the logical sum signal of the signal 34 divided by 1/2 and the signal 35 divided by 1/4 is selected. 36
And the original signal 13 and the logical product signal 39 are grayscale data 40.
(See FIG. 10).

Comparing FIGS. 7 to 10, the brightness setting signal 2
Grayscale data 40 depending on the combination of 4 and 33 levels
It can be seen that the number of pulses has changed within the predetermined time period.
That is, the number of pulses within the predetermined time shown in FIGS.
When the brightness setting signals 24 and 33 are both at the L level (FIG. 7)
Is zero, one when the signal 24 is at the H level and the signal 33 is at the L level (FIG. 8), two when the signals 24 and 33 are both at the H level (FIG. 9), and the signal 24 is at the L level and the signal 33 Is H
At the level (Fig. 10), the number is changed to three. Based on the gradation data 40 that changes in four ways,
The brightness of the LED can be changed in four steps by changing the current setting value that the current setting circuit 10 supplies to the LED. The current setting circuit 10 determines the current setting value according to the number of pulses within a predetermined time by integrating the signal of the gradation data 40, for example.

The number of pulses of the gradation data 40 within a predetermined time is changed in four ways, so that the duty ratio becomes four.
This means that the gradation data 4
As in the first embodiment, by directly applying 0 to the AND gate to control the display data output period, it is possible to perform gradation display in which the brightness of the LED is changed in four steps. However,
In this case, the extinguished state (when the number of pulses is zero) is included in one of the four stages. (Embodiment 3) Next, L according to a third embodiment of the present invention.
FIG. 11 shows a circuit configuration for 1 bit of the ED display drive device. In FIG. 11, the input data signals 42 and 43, which are serial data, are input to the shift registers 5a and 5b in synchronization with the clock signal 13, and the shift registers 5a and 5b.
The parallel data output from b is latched in the latches 6a and 6b at the rising edge of the latch signal 15. Latch 6
The output data from a and 6b are logically ANDed with the output control signal 16 for turning on / off by the AND gate 7a, and further A
The ND gate 7b performs a logical product with the output signal of the pulse cycle control circuit 23 and supplies the logical product to the output amplifier 8.

The function of the pulse cycle control circuit 23 is similar to that of the second embodiment, and the number of pulses within a predetermined time is changed to 4
Output the same gradation data. The circuit configuration can also be realized as in the second embodiment. In this embodiment, the brightness of the LED is changed by directly applying the gradation data to the AND gate 7b to control the display data output period. In addition, as the two brightness setting signals given to the pulse cycle control circuit 23, the shift registers 5a,
5b input data signals 42 and 43 are used. Therefore, the brightness of the LED changes according to the display data.

In each embodiment, by changing the configurations of the output amplifier and the LED driving power supply circuit,
A common cathode type LED can be displayed in gradation. Further, the number of gradation display stages is not limited to two or four, and an arbitrary number of stages can be selected by changing the specific circuit configuration of the pulse cycle control circuit.

[0026]

As described above, according to the present invention, the pulse period control circuit in which the frequency divider and the decoder are combined allows the gradation display for gradually changing the brightness of the LED to be provided only by giving a signal. Easy to do. Therefore, it is possible to provide an excellent LED display driving device that can easily change the brightness according to the ambient brightness.

[Brief description of drawings]

FIG. 1 is a circuit diagram of 1 bit of an LED display driving device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a pulse cycle control circuit in the LED display driving device of FIG.

FIG. 3 is a timing chart of a first state of the pulse cycle control circuit of FIG.

4 is a timing chart of a second state of the pulse cycle control circuit of FIG.

FIG. 5 is a circuit diagram of an LED display driving device according to a second embodiment of the present invention.

6 is a circuit diagram showing a configuration example of a pulse cycle control circuit in the LED display driving device of FIG.

7 is a timing chart of the first state of the pulse cycle control circuit of FIG.

8 is a timing chart of the second state of the pulse cycle control circuit of FIG.

9 is a timing chart of a third state of the pulse cycle control circuit of FIG.

10 is a timing chart of a fourth state of the pulse cycle control circuit of FIG.

FIG. 11 is a 1-bit circuit diagram of an LED display driving device according to a third embodiment of the present invention.

FIG. 12 is a circuit diagram of a conventional LED display driving device.

[Explanation of symbols]

 1 to 4, 9, 41 buffer 5 shift register 6 latch 7 AND gate 8 output amplifier 10 current setting circuit 11 resistor 12 monostable multivibrator 13 data shift clock signal (terminal) 14, 42, 43 input data signal (terminal) 15 Latch signal (terminal) 16 Output control signal (terminal) 18 Current setting terminal 19 Output signal terminal 21 LED 22 LED driving power circuit 23 Pulse cycle control circuit 24, 33 Luminance setting signal (terminal) 25 OR gate 26 1/2 Frequency divider circuit 27 Inverter 28, 40 Grayscale data output signal (terminal)

Claims (4)

[Claims] 1. Serial data for display is converted into parallel data by a shift register, this parallel data is latched by a latch means, and parallel data output from this latch means is given to an LED via a gate and an output amplifier. A configured LED display drive device, which is provided with a pulse cycle control circuit that outputs a signal whose duty ratio changes by changing the number of pulses within a predetermined time based on a brightness setting signal. The LE is characterized in that the duty ratio of the drive signal given to the LED is changed by inputting to the gate.
D display drive device. 2. The display serial data is converted into parallel data by a shift register, the parallel data is latched by a latch means, and the parallel data output from the latch means is given to an LED via a gate and an output amplifier. A display driving device configured to include a current setting means for instructing the output amplifier of a current setting value to be supplied to the LED, wherein the duty is changed by changing the number of pulses within a predetermined time based on a brightness setting signal. An LED display drive device, comprising: a pulse cycle control circuit for outputting a signal with a changed ratio, wherein the current setting means changes the current set value based on an output signal of the pulse cycle control circuit. 3. The pulse cycle control circuit divides a frequency of a data shift clock applied to the shift register.
A plurality of stages or a plurality of stages of frequency dividers, and a plurality of types of output signals having different numbers of pulses within a predetermined time by combining one or more outputs of the data shift clock and the frequency divider based on the brightness setting signal 3. The L according to claim 1, further comprising a decoder for selecting and outputting one of
ED display driver. 4. The pulse cycle control circuit, and a data shift clock supplied to the shift register,
By combining three types of signals, that is, a signal obtained by dividing by ½ and a signal obtained by dividing by ¼ by using a plurality of AND gates and an OR gate, among a plurality of types of output signals having different pulse numbers within a predetermined time 4. The LED display driving device according to claim 3, which is configured to select and output one of the above.