KR20230156618A - Pixel and display apparatus reducing static power consumption - Google Patents

Abstract

A pixel driving circuit according to the present disclosure includes a first circuit that controls a signal related to driving of one or more light-emitting elements in a data writing mode, and a signal transmitted from the first circuit in a driving mode. and a second circuit that supplies power to the one or more light emitting devices based on.

Description

Pixel and display device with reduced static power consumption {PIXEL AND DISPLAY APPARATUS REDUCING STATIC POWER CONSUMPTION}

The present invention relates to pixels included in a display device, and specifically to pixels with reduced static power consumption.

A typical display device includes a plurality of pixels, and is composed of M*N pixels arranged. Each pixel may include one or more light-emitting devices and is generally composed of three light-emitting devices (R, G, and B). Each light emitting element is called a subpixel.

Among various methods for controlling the operation of subpixels, there is a PWM control method that stores video data to control the emission of subframes during a single frame in built-in memory and controls grayscale through a PWM (Pulse Width Modulation) signal. The pixel driving circuit for driving each pixel for PWM control can be implemented with a transistor, but can be divided into a digital circuit and an analog circuit depending on the operating area of the transistor.

Digital circuits operate in the cutoff area and non-saturation area corresponding to On-Off to express '0' and '1'. On the other hand, analog circuits (excluding analog switches) such as AMP or bias operate in the saturation region and must continue to consume a certain amount of current during the circuit's operating time. Since the same power may not always be required depending on the display driving mode or screen, a method is needed to reduce static power consumption in the pixel driving circuit.

The above-mentioned background technology is technical information that the inventor possessed for deriving the present invention or acquired in the process of deriving the present invention, and cannot necessarily be said to be known art disclosed to the general public before filing the application for the present invention.

The purpose of the present disclosure is to provide a low-power pixel driving circuit. The problem that the present disclosure aims to solve is not limited to the problems mentioned above, and other problems and advantages of the present disclosure that are not mentioned can be understood through the following description and can be understood more clearly by the examples of the present disclosure. It will be. In addition, it will be appreciated that the problems and advantages to be solved by the present disclosure can be realized by the means and combinations thereof indicated in the patent claims.

A pixel driving circuit according to a first aspect of the present disclosure includes a first circuit that controls a signal related to driving one or more light emitting elements in a data writing mode; and a second circuit that supplies power to the one or more light emitting elements based on a signal transmitted from the first circuit in a driving mode.

A display device according to a second aspect of the present disclosure includes a display panel including an arrangement of a plurality of pixel driving circuits forming rows and columns; a scan driving circuit that sequentially outputs row signals to pixel driving circuits arranged in a row direction among the array included in the display panel; and a data driving circuit that outputs a column signal related to driving light-emitting elements corresponding to each of the plurality of pixel driving circuits to pixel driving circuits arranged in a column direction among the array included in the display panel. However, each of the plurality of pixel driving circuits is a pixel driving circuit according to the first aspect.

By reducing the number of times the capacitor is charged, the power consumed to drive the pixel can be reduced.

Additionally, by selectively supplying the bias power needed to charge the capacitor, the power consumed to drive the pixel can be reduced.

1 is a display device including a plurality of pixel driving circuits according to an embodiment of the present disclosure.
Figure 2 is a block diagram schematically showing a pixel driving circuit according to an embodiment of the present disclosure.
Figure 3 is a schematic diagram for explaining the configuration and operation of a driving unit according to an embodiment of the present disclosure.
Figure 4 is a circuit diagram for explaining the configuration of a sub-driver according to an embodiment of the present disclosure.
Figure 5 is an exemplary diagram of the number of charging times of the capacitor unit according to capacitor data according to an embodiment of the present disclosure.
FIG. 6 is an exemplary diagram for explaining control of power supply by a bias unit according to an embodiment of the present disclosure.
FIG. 7 is an exemplary diagram illustrating power supply control by a bias unit when the number of charging times is defined according to an embodiment of the present disclosure.
Figure 8 is a circuit diagram of a power generator according to an embodiment of the present disclosure.
Figure 9 is a timing diagram of the power generator according to the present specification outputting a reference voltage using a row signal and a column signal.
Figure 10 is a block diagram schematically showing the configuration of a general flip-flop.
Figure 11 is a timing diagram of a row signal and a column signal in a video data reset section according to an embodiment of the present disclosure.
FIG. 12 is an exemplary diagram showing a writing and PWM driving section of capacitor data and video data according to the present specification.

The advantages and features of the present disclosure and methods for achieving them will become clear by referring to the embodiments described in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments presented below, but may be implemented in various different forms, and should be understood to include all transformations, equivalents, and substitutes included in the spirit and technical scope of the present disclosure. do. The embodiments presented below are provided to ensure that the present disclosure is complete and to fully inform those skilled in the art of the scope of the invention. In describing the present disclosure, if it is determined that a detailed description of related known technologies may obscure the gist of the present disclosure, the detailed description will be omitted.

The terms used in the embodiments are general terms that are currently widely used as much as possible, but may vary depending on the intention or precedent of a person working in the art, the emergence of new technology, etc. In addition, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the relevant description. Therefore, terms used in the specification should be defined based on the meaning of the term and the overall content of the specification, not just the name of the term.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the disclosure. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that this does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

Additionally, terms including ordinal numbers such as “first” or “second” used in the specification may be used to describe various components, but the components should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another component.

In the following embodiments, “ON” used in connection with the device state may refer to an activated state of the device, and “OFF” may refer to a deactivated state of the device. “On,” as used in connection with a signal received by a device, may refer to a signal that activates the device, and “off” may refer to a signal that deactivates the device. The device can be activated by high or low voltage. For example, a P-type transistor can be activated by low voltage. N-type transistors are activated by high voltage. Accordingly, it should be understood that the “on” voltages for a P-type transistor and an N-type transistor are opposite (low vs. high) voltage levels.

When one element is referred to as being “connected to” another element, it includes both direct connection to the other element or intervening other elements. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a display device including a plurality of pixel driving circuits according to an embodiment of the present disclosure.

Referring to FIG. 1 , a display device 100 according to an embodiment of the present disclosure may include a display panel 110, a scan driving circuit 120, a data driving circuit 130, and a control unit 140.

In the present disclosure, the display panel 110 may include a plurality of pixels (PX). In one embodiment, the plurality of pixels (PX) may be composed of M * N (M and N are natural numbers) pixels arranged in the form of a matrix, but the method in which the plurality of pixels (PX) are arranged is zigzag. It may be arranged in various patterns according to different embodiments.

In the present disclosure, the display panel 110 includes a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, an electrochromic display (ECD), and a digital display (DMD). Mirror Device), AMD (Actuated Mirror Device), GLV (Grating Light Valve), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), VFD (Vacuum Fluorescent Display), and other types of It can be implemented as a flat panel display or a flexible display. In the present disclosure, the display panel 110 will be described as being implemented as an LED display as an example.

In the present disclosure, each of the plurality of pixels PX may include one or more light emitting devices. In one embodiment, the light emitting device may be a light emitting diode (LED). The light emitting diode may be a micro LED with a size of 80um or less. In one embodiment, one pixel PX may output various colors through a plurality of light emitting devices having different colors. As an example, one pixel PX may include light emitting elements composed of red, green, and blue. As another example, one pixel PX may further include a white light emitting device, and the white light emitting device may replace any one of the red, green, and blue light emitting devices. As another example, one pixel (PX) may be composed of one white light emitting device. In an embodiment in which one pixel (PX) includes a plurality of light emitting devices, each light emitting device included in one pixel (PX) may be referred to as a 'sub pixel'.

In the present disclosure, each pixel PX may include a pixel driving circuit that drives a light emitting element included in the pixel, that is, a sub-pixel. In the present disclosure, the pixel driving circuit may drive a turn on or turn off operation of a subpixel by a signal output from the scan driving circuit 120 and/or the data driving circuit 130. there is. In one embodiment, the pixel driving circuit may include at least one transistor, at least one capacitor, etc. In one embodiment, the pixel driving circuit may be implemented by a stacked structure on a semiconductor wafer.

In the present disclosure, the display panel 110 includes one or more scan lines (SL ₁ to SL _m ) arranged in a row direction and one or more data lines (DL ₁ to DL _n ) arranged in a column direction. It can be included. In the present disclosure, a pixel (PX) may be located at an intersection of one or more scan lines (SL ₁ to SL _m ) and one or more data lines (DL ₁ to DL _n ). Each pixel (PX) may be connected to one scan line (SL _k ) and one data line (DL _k ). One or more scan lines (SL ₁ to SL _m ) may be connected to the scan driving circuit 120, and one or more data lines (DL ₁ to DL _n ) may be connected to the data driving circuit 130.

In the present disclosure, the scan driving circuit 120 may output a signal (hereinafter referred to as a low signal) that causes one or more pixels connected to one of one or more scan lines (SL ₁ to SL _m ) to be driven. Preferably, the scan driving circuit 120 can sequentially select one or more scan lines (SL ₁ to SL _m ). For example, a pixel connected to the first scan line SL ₁ may be driven during the first scan driving period, and a pixel connected to the second scan line SL ₂ may be driven during the second scan driving period. The operation of the scan driving circuit 120 of the present disclosure will be described in detail later.

In the present disclosure, the data driving circuit 130 may output a signal related to gradation (hereinafter, a column signal) to each pixel through one or more data lines DL ₁ to DL _n . One data line is connected to one or more pixels in the longitudinal direction, but signals related to gray level can be input only to pixels connected to the scan line selected by the scan driving circuit 120. The operation of the data driving circuit 130 of the present disclosure will be described in detail later.

In the present disclosure, the control unit 140 may output a control signal to execute the operations of the scan driving circuit 120 and the data driving circuit 130. The control unit 140 may output a control signal corresponding to image data corresponding to one image frame to the scan driving circuit 120 or the data driving circuit 130.

Figure 2 is a block diagram schematically showing a pixel driving circuit according to an embodiment of the present disclosure.

Referring to FIG. 2 , the pixel driving circuit 200 of the present disclosure may include a first circuit 210 and a second circuit 220 . In the present disclosure, the first circuit 210 may also be referred to as a digital circuit and may operate in a data writing mode. In the present disclosure, the second circuit 220 may also be referred to as an analog circuit and may operate in a driving mode.

Although not shown in FIG. 2, the pixel driving circuit 200 of the present disclosure includes terminals (VCC, GND) for receiving power, and terminals (R, G, B) for outputting a light emission control signal to one or more light emitting devices. , may include a terminal (ROW) for receiving the row signal output from the scan driving circuit 120 and a terminal (COL) for receiving the column signal output from the data driving circuit 130, and the above-mentioned terminals A person skilled in the art will be able to easily understand that an electrical connection can be configured so that power and signals can be input and output through the device.

In one embodiment, the first circuit 210 may include a control unit 211 and a memory 212. As described above, the first circuit 210 may operate in data writing mode.

In one embodiment, memory 212 may be configured to store data related to control of pixels or light emitting devices of the present disclosure. In one embodiment, memory 212 may include video memory (not shown) and charging control memory (not shown). The video memory may store data related to the operation of one or more light-emitting devices, that is, video data. Video data stored in video memory may refer to data about the gray level at which a light emitting device emits light during one frame or one PWM cycle. The charging control memory may store capacitor data related to charging of the capacitor included in the driver 222, which will be described later. The operation of the memory of the present disclosure will be described in detail later.

In one embodiment, the control unit 211 may control the operation of the capacitor included in the driving unit 222. In one embodiment, the control unit 211 may control whether to charge the capacitor based on capacitor data stored in the charging control memory. The operation of the capacitor of the present disclosure will be described in detail later.

In one embodiment, the second circuit 220 may include a bias unit 221 and a driver 222. As described above, the second circuit 220 may operate in a drive mode.

In one embodiment, the driver 222 may control power supply to one or more light emitting devices based on data stored in the memory 212. Specifically, the driver 222 may supply power to one or more light-emitting devices based on video data stored in the video memory. In one embodiment, the driver 222 may be configured to control power supply to the light emitting device according to a PWM driving method. Since the PWM driving method is a technology known to those skilled in the art, detailed description will be omitted.

In one embodiment, the bias unit 221 may supply bias power to the driver 222. To supply bias power, the bias unit 221 may be connected to a terminal (VCC) for receiving power. The operation of the bias unit of the present disclosure will be described in detail later.

The pixel driving circuit 200 of the present disclosure may further include a power generator (not shown). The power generator may output a reference voltage (VDD) to the memory 212 based on the row signal output from the scan driving circuit 120 and the column signal output from the data driving circuit 130. The configuration and operation of the power generation unit of the present disclosure will be described later.

The pixel driving circuit 200 of the present disclosure may further include a reset unit (not shown) that outputs a reset signal (RSTB) to the memory 212 to initialize data stored in the memory 212. The configuration and operation of the reset unit of the present disclosure will be described later.

Figure 3 is a schematic diagram for explaining the configuration and operation of a driving unit according to an embodiment of the present disclosure.

Referring to FIG. 3, a driving unit 330 including a control unit 310, a bias unit 320, and one or more sub-driving units 331 is shown. In FIG. 3, the control unit 310 may have a configuration corresponding to the control unit 211 of FIG. 2, the bias unit 320 may have a configuration corresponding to the bias unit 221 of FIG. 2, and the driver 330 may be a configuration corresponding to the driving unit 222 of FIG. 2.

In the present disclosure, the driver 330 may control power supply to one or more light emitting devices. In one embodiment, the driver 330 may include one or more sub-drivers 331 each corresponding to one or more light-emitting devices. That is, the pixel of the present disclosure may include one or more light-emitting devices, and one sub-driver 331 may be configured to correspond to one light-emitting device.

As described above, the driver 330 may control power supply to one or more light emitting devices based on data stored in the memory. Specifically, the sub-driver 331 may control power supply to the light-emitting device based on data stored in the memory. The sub-driver 331 may supply power to the light-emitting device based on video data stored in the video memory. In one embodiment, the sub-driver 331 may include a capacitor unit that charges power necessary for driving the light-emitting device, and the capacitor unit of the present disclosure will be described in detail later.

In the present disclosure, the bias unit 320 may supply bias power to the driver 330, and specifically, the bias unit 320 may supply bias power to the sub-driver 331. The bias unit 320 may be connected to a terminal (VCC) through which the pixel driving circuit receives power in order to supply bias power to the sub-driver 331.

In one embodiment, whether power is supplied to the sub-driver 331 by the bias unit 320 may be controlled by the control signal CTRL output from the control unit 310. In one embodiment, the control signal CTRL that controls whether or not to supply power to the sub-driver 331 of the bias unit 320 may be output from the control unit 310. In one embodiment, the function of controlling the operation of the capacitor of the control unit 310 may be performed in a separate configuration from the control unit 310, but is not limited thereto.

In one embodiment, the power supplied by the bias unit 320 may be stored in a capacitor included in the sub-drive unit 331.

In one embodiment, the control unit 310 may control whether to charge the capacitor based on capacitor data stored in the memory. In other words, the control unit 310 can control whether to supply power to the bias unit 320 and whether to charge the capacitor by outputting the control signal CTRL based on the capacitor data stored in the memory.

Figure 4 is a circuit diagram for explaining the configuration of a sub-driver according to an embodiment of the present disclosure.

Referring to FIG. 4, the sub-driver 400 according to one embodiment may include a capacitor unit 401, a charging unit 402, a discharging unit 403, and a switch unit (SW). In FIG. 4 , the sub-driver 400 may have a configuration corresponding to the sub-driver 331 of FIG. 3 .

Referring to FIG. 4, the charging unit 402 may be connected between the pixel positive power and the pixel negative power. The discharge unit 403 may be connected between the pixel positive power and the pixel negative power. The capacitor unit 401 may be connected between the charging unit 402 and the discharging unit 403. The switch unit (SW) may be connected between the charging unit 402 and the capacitor unit 401. The switch unit (SW) can be turned on or off by the control signal (CTRL) output from the control unit.

The example shown in FIG. 4 is an example in which the capacitor unit 401 is composed of two capacitors C ₁ and C ₂ . The first capacitor C ₁ may be connected between the first connection line connecting the charging unit 402 and the discharging unit 403 and the pixel negative power source (GND). The second capacitor C ₂ may be connected between a second connection line connecting the charging unit 402 and the discharging unit 403 and the pixel negative power source. In this case, _the charging unit 402 includes a first charging transistor (T C1 ) and a second charging transistor (T _C2 ) connected to the first capacitor (C ₁ ) and the second capacitor (C ₂ ), respectively, between the pixel positive power and the pixel negative power. ) may include. The discharge unit 403 includes a first discharge transistor (T D1 ) and a second discharge transistor (T _D2 ) connected to the first capacitor ₍ C ₁ ) and the second capacitor (C ₂ ), respectively, between the pixel positive power and the pixel negative power. It can be included. The switch unit (SW) includes a first switching element (SW ₁ ) connected between the first charging transistor (T _C1 ) and the first capacitor (C ₁ ), the second charging transistor (T _C2 ), and the second capacitor (C ₂ ). It may include a second switching element (SW ₂ ) connected therebetween. The switch unit (SW) may further include a third switching element (SW ₃ ) connected between the first charging transistor (T _C1 ) and the second charging transistor (T _C2 ). The sub-driver 400 may further include a PWM switching element (SW _PWM ) connected in series with the discharge unit 403 between the pixel positive power and the pixel negative power. The PWM switching element (SW _PWM ) may be turned on or off depending on the video data stored in the memory.

The sub-driver 400 of FIG. 4 is provided as an example, and the circuit configuration according to the elements included in the sub-driver 400 and their connections may be configured differently from the embodiment shown in FIG. 4. For example, in FIG. 4, the sub-driver 400 is shown as including a transistor that is an NMOSFET, but in another embodiment, the sub-driver 400 may include a transistor that is a PMOSFET, and in this embodiment, the first The capacitor (C ₁ ) and the second capacitor (C ₂ ) may be connected to a terminal (VCC) for receiving power rather than the pixel negative power (GND).

Figure 5 is an exemplary diagram of the number of charging times of the capacitor unit according to capacitor data according to an embodiment of the present disclosure.

Referring to FIG. 5, an example is shown where the capacitor data (Cap data) stored in the memory is 3-bits and the video data is 12-bits.

In the present disclosure, the capacitor data may correspond to the number of times the capacitor portion can be charged to the maximum in one cycle (i.e., a single frame). That is, the number of charging times within a single frame of the capacitor unit can be defined through capacitor data.

Referring to FIG. 5, for example, when the capacitor data is <000>, the control unit may output a control signal so that the capacitor unit is charged all 12 times within one cycle. When the capacitor data is <001>, the control unit may output a control signal so that the capacitor unit is charged only once in one cycle. When the capacitor data is <010>, the control unit may output a control signal to charge the second capacitor unit within one cycle. When the capacitor data is <011>, the control unit can output a control signal to charge the capacitor part 3 within one cycle. That is, the value of the capacitor data stored in the memory is a value related to the number of times the capacitor is charged during one cycle, and the control unit can output a control signal to the capacitor unit to control charging of the capacitor unit according to the capacitor data stored in the memory. However, the example shown in FIG. 5 is for ease of understanding, and the number of bits of capacitor data and the number of charging times according to the capacitor data may be appropriately set in any manner.

FIG. 6 is an exemplary diagram for explaining control of power supply by a bias unit according to an embodiment of the present disclosure.

In the present disclosure, as described above, the control unit may control whether or not power is supplied by the bias unit through a control signal.

In one embodiment, the controller may control the bias unit so that power is supplied by the bias unit only in the driving mode. As described above, the pixel driving circuit of the present disclosure may correspond to two modes, a data writing mode or a driving mode. Power consumption can be reduced by the control unit operating (turning on) the bias unit only when the pixel driving circuit is in a driving mode.

In one embodiment, the control unit may control the bias unit so that the bias unit stops supplying power when the capacitor unit is charged by bias power supplied by the bias unit. When the capacitor portion is charged, power consumption can be reduced by limiting the operation of the bias portion.

In one embodiment, the control unit controls the bias unit to stop supplying power when the capacitor unit is charged by the bias power supplied by the bias unit, but the bias unit supplies bias power only when the bit value of the video data is 1. You can control it to do so. In other words, in this embodiment, the control unit reads the video data stored in the memory, operates the bias unit only in response to the bit value of the video data being 1, and limits the operation of the bias unit when the capacitor unit is charged by the bias power. can do. In this embodiment, the control unit may not operate the bias unit in response to the bit value of the video data being 0. When the value of the video data is 0, there is no need to drive the light emitting element, and accordingly, there is no need to charge the capacitor unit. In this embodiment, power consumption can be reduced by controlling the operation of the bias unit and blocking the bias power supply when there is no need to charge the capacitor unit.

Referring to FIG. 6, a timing diagram is shown to explain an embodiment in which the control unit supplies bias power only when the value of video data is 1.

For example, referring to FIG. 6, when the video data is (11111111111), the value of all video data is 1, so the control unit can operate the bias unit in response to all bits of the video data.

Meanwhile, referring to FIG. 6, when the capacitor video data is (10101010101), the control unit can operate the bias unit only in response to the bit value of the video data being 1. On the other hand, in response to the bit value of the video data being 0, as described above, there is no need to drive the light emitting element, so the capacitor portion is not charged. This embodiment implements this by blocking the supply of bias power necessary for charging the capacitor portion.

Referring to FIG. 6, it is shown that even when the capacitor video data is (00000000111), the capacitor portion is not charged, corresponding to the bit value of the video data being 0.

Meanwhile, referring to FIG. 6, when the capacitor video data is (00000000000), the value of all video data is 0, so the control unit may not operate the bias unit in response to all bits of the video data, and accordingly, the capacitor unit may not operate all bits. It does not charge in response to the beat.

FIG. 7 is an exemplary diagram illustrating power supply control by a bias unit when the number of charging times is defined according to an embodiment of the present disclosure.

As described above with reference to FIG. 5, the number of charges within a single frame of the capacitor unit can be defined through capacitor data, and as described above with reference to FIG. 6, the control unit only responds to the bit value of the video data being 1. Thus, the bias section can be operated.

In one embodiment, when the number of charges is defined, the control unit controls the bias unit so that the bias supplies power only when the bit value of the video data is 1, and when the capacitor is charged by the bias power, the bias stops supplying power. However, the bias unit can be controlled so that the bias power supply is limited to the number of charging times within a single frame. Specifically, the control unit operates the bias unit only in response to the bit value of the video data being 1, but the number of times the bias unit is operated within a single frame may be limited. That is, when the number of bits with a value of 1 included in the video data within a single frame exceeds the charging number, the control unit charges the capacitor unit corresponding to a portion of the bits with a bit value of 1 in the video data equal to the charging number, In response to the remainder, the operation of the bias unit can be controlled so that the capacitor unit is not charged. Preferably, the bias unit may be operated in response to the bit value being 1 for the upper bit, and when the number of operations of the bias unit reaches the defined number of charging within a single frame, the bias unit may not be activated in the lower bits thereafter. In this embodiment, power consumption can be reduced by the control unit blocking bias power supply to bits that exceed the number of charging times.

Referring to FIG. 7, when the video data is (10101010101), a timing diagram is shown to explain an embodiment of charging the capacitor unit according to various charging times.

Referring to FIG. 7, an example is shown in which the number of charging times is not defined or the capacitor unit is defined to be charged for all bits in which the bit value of video data is 1 within a single frame (All times). As shown, if the number of charging times is not defined or the capacitor unit is defined to be charged for all bits of the video data within a single frame, the capacitor unit charges in response to all bits of the video data with a value of 1. It can be done as much as possible. In other words, the control unit can control the bias unit so that the bias power is supplied in response to all bits of video data having a 1 value within a single frame.

Referring to FIG. 7, when the number of charges is defined as 1, an example is shown in which the capacitor unit is charged for only one of the bits whose bit value of video data is 1 within a single frame. As shown, when the number of charging times is defined as 1, the control unit can cause the capacitor unit to be charged in response to only one of the bits of the video data whose bit value is 1. In other words, the control unit can control the bias unit so that bias power is supplied only once within a single frame.

Likewise, referring to FIG. 7, when the number of charging times is defined as K, an example is shown in which the capacitor unit is charged for only K bits among the bits whose bit value of video data is 1 within a single frame. As shown, when the number of charging times is defined as K, the control unit can cause the capacitor unit to be charged in response to only K bits among the bits that are 1, which is the bit value of the video data. That is, in the example shown in FIG. 7, there are 6 bits with a bit value of 1 in the video data within a single frame, but since the number of charging times is defined as K, the capacitor unit is charged in response to only K bits out of the 6 bits. It may be possible, and it may not be charged in response to the remaining bits except for K. In other words, the control unit can control the bias unit so that bias power is supplied up to K times within a single frame.

Referring to FIG. 7, in the example shown in FIG. 7, there are 6 bits of video data with a bit value of 1 within a single frame, so when the charging number is defined as a value of 6 or more, all bits with a bit value of 1 In response, the capacitor portion may be charged.

In the example shown in FIG. 7, when the number of charging times is defined, the capacitor portion is charged preferentially corresponding to the upper bit among the bits with a bit value of 1 in the video data. However, this is provided as an example, and any suitable method may be applied. there is.

The video data shown in FIG. 7 is provided as an example, and it will be understood by those skilled in the art that the method of the present disclosure can be applied to video data including the number of bits, bit values, and number of bits with a bit value of 1 in any single frame. will be understandable.

In one embodiment, the number of times the capacitor unit is charged within a single frame may be user-definable.

Below, a method of outputting a reference voltage and writing data to the memory of the present disclosure will be described.

Figure 8 is a circuit diagram of a power generator according to an embodiment of the present disclosure.

As described above, the pixel driving circuit according to an embodiment of the present disclosure may include a power generator. The power generator may output a reference voltage to the memory using the low signal output from the scan driving circuit and the column signal output from the data driving circuit.

Referring to FIG. 8, the power generator 800 according to an embodiment of the present specification may include a transistor 810, a NAND gate 820, and a time delay element 830. The power generator 800 is connected to a row signal input terminal (ROW) and a column signal input terminal (COL) to receive the row signal and the column signal. Additionally, the power generator 800 may include a reference voltage output terminal that outputs the reference voltage (VDD_INT) to a memory.

The transistor 810 may be disposed between the input terminal of the low signal and the output terminal of the reference voltage. According to one embodiment, transistor 810 may be a PMOSFET. The drain terminal and source terminal of the PMOSFET may be connected to the input terminal of the low signal and the output terminal of the reference voltage, and the gate terminal of the PMOSFET may be connected to the signal output terminal of the NAND gate. For reference, PMOSFET turns off when the signal input to the gate terminal is logic high (Logic High, '1'), and turns on when the signal input to the gate terminal is logic low (Logic Low, '0'). .

The NAND gate 820 may be placed between the middle terminal (gate terminal) of the transistor 810 and the input terminal of the column signal. The NAND gate 820 is a logic circuit element and may have two input terminals and one output terminal. A column signal may be input to one of the two input terminals of the NAND gate 820, and a delayed row signal may be input to the other. For reference, the NAND gate 820 outputs logic low only when all inputs are logic high ([1,1]), and in other cases ([0,0], [1,0], [0,1 ]) All output logic high.

The time delay element 830 may be placed between the input terminal of the low signal and the NAND gate. The time delay element 830 can receive a low signal, delay it by a preset time, and output the delayed low signal to one of the input terminals of the NAND gate 820. As an example, the delay time may be 0.5ns to 1ns.

Figure 9 is a timing diagram of the power generator according to the present specification outputting a reference voltage using a row signal and a column signal.

Referring to FIG. 9, 'ROW' refers to a row signal input through the input terminal of the row signal, and 'ROW_D' refers to a row signal delayed after passing a time delay element (e.g., the time delay element 830 in FIG. 8). Refers to a low signal, 'COL' refers to a column signal input through the input terminal of the column signal, and 'CTRL' refers to a signal output from a NAND gate (e.g., NAND gate 820 in FIG. 8).

First, the low signal may have the characteristic of changing from a logic high state to a logic low state, maintaining the logic low state for a preset time, and then changing back to a logic high state. The column signal may also have the characteristic of changing from a logic high state to a logic low state, maintaining the logic low state for a preset time, and then changing back to a logic high state. At this time, the column signal may change from logic high to logic low slightly before the low signal enters the logic low state. Additionally, the column signal may have a time difference for maintaining logic low when the data to be input to the memory is logic low ('0') and logic high ('1'). If it corresponds to logic low ('0') data, the column signal may change from logic low to logic high after the low signal changes to logic high (see (a) of FIG. 9). If it corresponds to logic high ('1') data, the column signal may change from logic low to logic high before the low signal changes to logic high (see (b) of FIG. 9).

Depending on the timing of the delayed row signal and the column signal, the NAND gate may change from logic low to logic high and back to logic low. As described above, the transistor (e.g., transistor 810 in FIG. 8, PMOSFET) is turned on by a logic low signal, turned off by a logic high signal, and then turned on again by a logic low signal. It can be (On).

Referring to (c) of FIG. 9, when the row signal ROW is logic high, the transistor is in the On state, so the reference voltage VDD_INT can be output to the output terminal of the reference voltage. On the other hand, when the row signal ROW is logic low, the transistor is in an off state, so the reference voltage VDD_INT of the output terminal of the reference voltage can be maintained. To this end, the power generator (e.g., the power generator 800 of FIG. 8) may further include a capacitor (e.g., the capacitor 840 of FIG. 8) disposed between the output terminal of the reference voltage and the circuit ground. The capacitor can play a role in maintaining the reference voltage (VDD_INT) of the output terminal of the reference voltage because the transistor is in the off state.

Figure 10 is a block diagram schematically showing the configuration of a general flip-flop.

Referring to FIG. 10, the column signal may be input to the data signal input terminal (D) of the flip-flop (FF), and the row signal may be input to the clock signal input terminal (CLK). Referring to (a) of FIG. 9, if the column signal is in a logic low state at the moment (rising edge) when the row signal changes from logic low to logic high, logic low data ('0') is sent to the flip-flop (FF). can be entered. In addition, referring to (b) of FIG. 9, if the column signal is in a logic high state at the moment (rising edge) when the row signal changes from logic low to logic high, logic high data ('1') is transmitted to the flip-flop (FF). ) can be entered. That is, in the present disclosure, the power generator can output reference power through the timing of the row signal and the column signal, while simultaneously inputting capacitor data or video data using the same signal. In the present disclosure, the memory of the present disclosure is described as an example consisting of a plurality of flip-flops, but is not limited thereto.

Meanwhile, as described above, the pixel driving circuit of the present disclosure may further include a reset unit that outputs a reset signal (RSTB) to the memory to initialize data stored in the memory.

Figure 11 is a timing diagram of a row signal and a column signal in a video data reset section according to an embodiment of the present disclosure.

Referring to FIG. 11, the reset unit 1100 has a data signal input terminal (D) where a row signal is input, a clock signal input terminal (CLK) where a column signal is input, and a signal output terminal (Q) where a reset signal (RSTB) is output. You can have it. At this time, the column signal input to the clock signal input terminal CLK may be input in an inverted state of the column signal output from the data driving circuit. Accordingly, the reset unit 1100 may further include a signal inverter (not shown) input to the clock signal input terminal (CLK) to invert the column signal.

In the video data reset section (RESET), the scan driving circuit may output a low signal that maintains a logic low state for a longer period of time than the reference interval. In the video data reset section (RESET), the data driving circuit may output a column signal that changes from logic high to logic low while the low signal maintains a logic low state. In the present disclosure, the reset signal (RSTB) may initialize data stored in the memory at logic low ('0'). Therefore, it should be understood that the reset signal RSTB shown in FIG. 11 is a signal in which the column signal is not inverted.

FIG. 12 is an exemplary diagram showing a writing and PWM driving section of capacitor data and video data according to the present specification.

Referring to (a) of FIG. 12, in one embodiment, the row signal and the column signal are a capacitor data write section, a video data write section, and PWM driving every one cycle (1H). It may be a signal including a section. That is, capacitor data can be newly input every cycle.

Referring to (b) of FIG. 12, in another embodiment, the row signal and the column signal may be signals including one capacitor data writing section, a video data writing section and a PWM driving section every one cycle (1H). That is, this embodiment relates to a case where capacitor data is input only once and is not changed without additional control.

Referring to (c) of FIG. 12, in another embodiment, the row signal and the column signal repeat a capacitor data writing section every preset cycle, a video data writing section and a PWM driving section every one cycle (1H). It may be a signal containing That is, capacitor data can be newly input at regular intervals.

In the above-described embodiments, the period H may correspond to 1 frame, or may be a pre-divided interval within 1 frame.

The above-described scan driving circuit and data driving circuit include processors, ASICs (application-specific integrated circuits), other chipsets, logic circuits, registers, communication modems, and It may include a data processing device, etc. Additionally, when the above-described control logic is implemented in software, the scan driving circuit and data driving circuit may be implemented as a set of program modules. At this time, the program module may be stored in the memory device and executed by the processor.

A program is written in a computer language such as C/C++, C#, JAVA, Python, or machine language that the computer's processor (CPU) can read through the computer's device interface in order for the computer to read the program and execute the methods implemented in the program. May contain encoded code. These codes may include functional codes related to functions that define the necessary functions for executing the methods, and may include control codes related to execution procedures necessary for the computer's processor to execute the functions according to predetermined procedures. there is. In addition, these codes may further include memory reference-related codes that indicate from which location (address address) in the computer's internal or external memory additional information or media required for the computer's processor to execute functions should be referenced. Additionally, if the computer's processor needs to communicate with any other remote computer or server to execute functions, how should the code communicate with any other remote computer or server using the computer's communication module? , It may further include communication-related codes regarding what information or media should be transmitted and received during communication.

A storage medium in which a program is stored is not a medium that stores data for a short period of time, such as a register or cache memory, but a medium that stores data semi-permanently and can be read by a device. Specifically, examples of storage media include, but are not limited to, ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage devices. That is, the program can be stored in various recording media on various servers that the computer can access or in various recording media on the user's computer. Additionally, the storage medium may be distributed across networked computer systems to store computer-readable code in a distributed manner.

Those skilled in the art related to the present embodiment will understand that the above-described substrate can be implemented in a modified form without departing from the essential characteristics. Therefore, the spirit of the present invention should not be limited to the above-described embodiments, and the scope of the patent claims described below as well as all scopes equivalent to or equivalently changed from the scope of the claims are within the scope of the spirit of the present invention. It will be said to belong to

Claims (11)

In a data writing mode, a first circuit that controls signals related to driving one or more light emitting elements; and
a second circuit that supplies power to the one or more light emitting elements based on a signal transmitted from the first circuit in a driving mode;
Including,
Pixel driving circuit.
According to claim 1,
The first circuit is,
Storing video data related to driving of the one or more light emitting elements and capacitor data related to charging of the capacitor, and outputting a control signal corresponding to the video data and the capacitor data,
Pixel driving circuit.
According to clause 2,
The second circuit is,
A driving unit that supplies power to the one or more light emitting devices; and
a bias unit that supplies bias power to the driving unit;
Including,
Pixel driving circuit.
According to clause 3,
The driving unit,
Each includes one or more sub-drivers corresponding to the one or more light-emitting elements,
Each of the one or more sub-drive units includes a capacitor,
The first circuit is,
a control unit that controls whether to charge capacitors included in the one or more sub-drive units based on the capacitor data;
Including,
Pixel driving circuit.
According to clause 3,
The first circuit is,
a control unit that controls whether to supply bias power by the bias unit by controlling the bias unit based on the video data;
Including,
Pixel driving circuit.
According to clause 5,
The control unit,
Controlling the bias unit so that the bias unit supplies the bias power only in the driving mode,
Pixel driving circuit.
According to clause 5,
The control unit,
When the capacitor is charged by the bias power, controlling the bias unit so that the bias unit stops supplying power.
Pixel driving circuit.
According to clause 5,
The control unit,
Controlling the bias unit so that the bias unit supplies power only when the bit value of the video data is 1, and when the capacitor is charged by the bias power, the bias unit stops supplying power.
Pixel driving circuit.
According to clause 8,
If the number of charges is defined as K,
The control unit,
Controlling the bias unit so that the bias power is supplied up to K times within a single frame,
Pixel driving circuit.
According to clause 9,
The number of charging times can be defined by the user,
Pixel driving circuit.
A display panel comprising an arrangement of a plurality of pixel drive circuits forming rows and columns;
a scan driving circuit that sequentially outputs row signals to pixel driving circuits arranged in a row direction among the array included in the display panel; and
a data driving circuit that outputs column signals related to driving light-emitting elements corresponding to each of the plurality of pixel driving circuits to pixel driving circuits arranged in a column direction among the array included in the display panel;
Including,
Each of the plurality of pixel driving circuits is a pixel driving circuit according to any one of claims 1 to 9,
Display device.

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