KR102620243B1 - Solar cell module - Google Patents

Abstract

One embodiment of the present invention includes at least one first solar cell including a first upper grid electrode portion and a first lower electrode portion, at least one second solar cell including a second upper grid electrode portion and a second lower electrode portion, It includes an upper connection electrode connecting the first upper grid electrode portion and the second upper grid electrode portion, and a lower connection electrode connecting the first lower electrode portion and the second lower electrode portion, and the first solar cell and the second solar cell are They are arranged alternately, and the upper connection electrodes simultaneously connect the plurality of first microelectrodes included in the first solar cell with the plurality of second microelectrodes included in the adjacent second solar cell, thereby improving aesthetics and permeability. begins.

Description

Solar cell module {SOLAR CELL MODULE}

The present invention relates to solar cell modules. More specifically, the present invention relates to solar cell modules with improved photovoltaic efficiency.

Recently, as the depletion of existing energy resources such as oil and coal is expected, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as next-generation batteries that directly convert solar energy into electrical energy using semiconductor devices.

Meanwhile, a solar cell module is formed by arranging a plurality of solar cells and then electrically connecting them to each other. Since the power generation efficiency can vary depending on the arrangement of the plurality of solar cells, much research has been done to improve the power generation efficiency. is being done. Solar cell modules developed to date have solar cells with the same conductivity arranged sequentially.

However, in a solar cell module in which solar cells with the same conductivity are arranged in series, the lower electrode of the solar cell and the upper electrode of the adjacent solar cell must be electrically connected to each other by a connecting electrode in order to electrically connect adjacent solar cell units. Therefore, there is a problem in that a plurality of solar cells must be spaced apart by a certain width or more.

In addition, when the solar cell includes a grid-shaped grid electrode formed by a plurality of microelectrodes, a plurality of microelectrodes included in each randomly selected solar cell and a solar cell adjacent to the randomly selected solar cell are electrically connected simultaneously. To achieve this, the area of the connection electrode had to be expanded. However, when the surface area of the connection electrode is widened, there is a problem that the power generation efficiency of the solar cell module is reduced due to light reflection by the connection electrode.

Embodiments of the present invention provide solar cell modules with excellent photoelectric conversion efficiency.

One embodiment of the present invention includes an N-type crystalline silicon semiconductor substrate having an N-type conduction type; a P-type layer located on the upper surface of the N-type crystalline silicon semiconductor substrate, forming a P-N junction with the N-type crystalline silicon semiconductor substrate and having a P-type conduction type; a first upper grid electrode portion located on the P-type layer, electrically connected to the P-type layer, and including a plurality of first microelectrodes; a first lower electrode portion located on the lower surface of the N-type crystalline silicon semiconductor substrate, which is the opposite side of the upper surface, and connected to the N-type crystalline silicon semiconductor substrate; at least one first solar cell, P-type conduction type, including: a P-type crystalline silicon semiconductor substrate; an N-type layer located on the upper surface of the P-type crystalline silicon semiconductor substrate and having an N-type conductivity forming a P-N junction with the P-type crystalline silicon semiconductor substrate; a second upper grid electrode portion located on the N-type layer and connected to the N-type layer and including a plurality of second microelectrodes; At least one second solar cell including a second lower electrode portion located on the lower surface of the P-type crystalline silicon semiconductor substrate opposite to the upper surface and connected to the P-type crystalline silicon semiconductor substrate, the first upper grid electrode portion, and An upper connection electrode connecting the second upper grid electrode unit, and a lower connection electrode connecting the first lower electrode unit and the second lower electrode unit, wherein the first solar cell and the second solar cell alternate with each other. is disposed, and the upper connection electrode is included in a plurality of first microelectrodes included in a first solar cell randomly selected from among the plurality of first solar cells and in the second solar cell adjacent to the randomly selected first solar cell. Disclosed is a solar cell module that simultaneously electrically connects a plurality of second microelectrodes.

In this embodiment, the first microelectrodes include two or more X1 upper microelectrodes extending in a first direction and two or more Y1 upper microelectrodes extending in a second direction forming a predetermined angle with the first direction; , the second microelectrodes may include two or more X2 upper microelectrodes extending in a first direction and two or more Y2 upper microelectrodes extending in a second direction forming a predetermined angle with the first direction.

In this embodiment, the connection electrode includes two or more X1 upper microelectrodes included in a first solar cell randomly selected among the first solar cells, and the second solar cell adjacent to the randomly selected first solar cell in the first direction. 2 or more X2 upper microelectrodes included in the cell; or at least two Y1 upper microelectrodes included in a first solar cell randomly selected among the first solar cells and at least two Y2 upper microelectrodes included in the second solar cell adjacent to the randomly selected first solar cell in the first direction. Electrodes can be electrically connected simultaneously.

In this embodiment, the upper connection electrode includes all of the X1 upper microelectrodes included in the randomly selected first solar cell and the X2 upper microelectrode included in the second solar cell adjacent to the randomly selected first solar cell in the first direction. entire; Or all of the Y1 upper microelectrodes included in the arbitrarily selected first solar cell and all of the two or more Y2 upper microelectrodes included in the second solar cell adjacent to the arbitrarily selected first solar cell in the second direction; can be electrically connected at the same time. there is.

In this embodiment, the first direction may be the X direction, and the second direction may be the Y direction.

In this embodiment, the predetermined angle formed by the first direction and the second direction may be greater than 0° and less than 180°.

In this embodiment, the first upper grid electrode unit includes a square pattern, a pentagonal pattern, a hexagonal pattern, a heptagonal pattern, or an octagonal pattern formed by a plurality of microelectrodes including the X1 upper microelectrode and the Y1 upper microelectrode. And, the second upper grid electrode unit may include a square pattern, a pentagonal pattern, a hexagonal pattern, a heptagonal pattern, or an octagonal pattern formed by a plurality of microelectrodes including the X2 upper microelectrode and the Y2 upper microelectrode.

In this embodiment, the first upper grid electrode portion includes a square pattern formed by a plurality of microelectrodes including the X1 upper microelectrode and the Y1 upper microelectrode, and the second upper grid electrode portion includes the X2 upper microelectrode. It may include a square pattern formed by a plurality of microelectrodes including a microelectrode and the Y2 upper microelectrode.

In this embodiment, the first upper grid electrode portion and the second upper grid electrode portion include an upper microelectrode W1 and W2 extending in a third direction forming a predetermined angle with the first direction and the second direction, respectively. Each may further include an upper microelectrode.

In this embodiment, the first upper grid electrode unit includes a hexagonal pattern formed by a plurality of microelectrodes including the X1 upper microelectrode, the Y1 upper microelectrode, and the W1 upper microelectrode, and the second upper grid electrode. The grid electrode unit may include a hexagonal pattern formed by a plurality of microelectrodes including the X2 upper microelectrode, the Y2 upper microelectrode, and the W2 upper microelectrode.

In this embodiment, the area on which the first upper grid electrode portion is formed of the upper surface of the N-type crystalline silicon semiconductor substrate is 0.1 to 10% of the total area of the upper surface of the N-type crystalline silicon semiconductor substrate, and The area of the upper surface of the P-type crystalline silicon semiconductor substrate where the second upper grid electrode portion is formed may be 0.1 to 10% of the total area of the upper surface of the P-type crystalline silicon semiconductor substrate.

In this embodiment, the first lower electrode unit includes two or more X1 lower microelectrodes extending in a first direction and two or more Y1 lower microelectrodes extending in a second direction, and the second lower electrode unit extends in the first direction. It may include two or more X2 lower microelectrodes extending in the second direction and two or more Y2 lower microelectrodes extending in the second direction.

In this embodiment, the lower connection electrode includes two or more X1 lower microelectrodes included in the randomly selected first solar cell and two or more X2 included in the second solar cell adjacent to the randomly selected first solar cell in the first direction. lower microelectrode; Alternatively, two or more Y1 lower microelectrodes included in a randomly selected first solar cell and two or more Y2 lower microelectrodes included in a second solar cell adjacent to the randomly selected first solar cell in a second direction may be electrically connected at the same time. there is.

In this embodiment, the upper connection electrode and the lower connection electrode are each formed side by side in one direction, and the direction in which the upper connection electrode is formed and the direction in which the lower connection electrode is formed may be in a twisted position.

In this embodiment, the first solar cell and the second solar cell may be spaced apart at a predetermined interval to form a gap area, and the upper connection electrode and the lower connection electrode may be disposed on the gap area.

In this embodiment, the width of the gap region may be 1 to 1,000 μm.

In this embodiment, the widths of the upper connection electrode and the lower connection electrode may each be 10 to 1,500 μm.

In this embodiment, the gap area can be completely covered by the upper connection electrode and the lower connection electrode.

In this embodiment, the first solar cell further includes an N-type back surface electric field layer disposed between the N-type crystalline silicon semiconductor substrate and the first lower electrode portion and having an N-type conduction type, and the first lower electrode portion. The electrode portion is connected to the N-type back electric layer, and the second solar cell further includes a P-type back electric layer disposed between the P-type crystalline silicon semiconductor substrate and the second lower electrode portion and having a P-type conduction type. And, the second lower electrode part can be connected to the P-type rear surface layer.

In this embodiment, the first solar cell further includes a first anti-reflection layer disposed on the P-type layer, and the first upper grid electrode portion penetrates the first anti-reflection layer and is connected to the P-type layer. And, the second solar cell further includes a second anti-reflection layer disposed on the N-type layer, and the second upper grid electrode portion may penetrate the second anti-reflection layer and connect to the N-type layer.

The solar cell module according to the present embodiments minimizes light loss by using solar cells including grid electrodes and can have excellent photoelectric conversion efficiency by alternately arranging solar cells with different conductivity types. Of course, the scope of the present invention is not limited by this effect.

1 is a plan view schematically showing a solar cell module according to an embodiment of the present invention.
Figure 2 is a cross-sectional view schematically showing the line II' of Figure 1.
FIG. 3 is a plan view schematically showing a modified example of the solar cell module of FIG. 1.

Since the present invention can be modified in various ways and can have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all transformations, equivalents, and substitutes included in the spirit and technical scope of the present invention. In describing the present invention, if it is determined that a detailed description of related known technologies may obscure the gist of the present invention, the detailed description will be omitted.

Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. Terms are used only to distinguish one component from another.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. Additionally, in each drawing, components are exaggerated, omitted, or schematically depicted for convenience and clarity of explanation, and the size of each component does not entirely reflect the actual size.

In the description of each component, when it is described as being formed on or under, both on and under are formed directly or through other components. Included, and the standards for on and under are explained based on the drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, identical or corresponding components will be assigned the same drawing numbers and overlapping descriptions thereof will be omitted. do.

FIG. 1 is a plan view schematically showing a solar cell module according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view schematically showing a cross section taken along line II′ of FIG. 1 .

Referring to Figures 1 and 2, the solar cell module 10 according to an embodiment of the present invention includes one or more first solar cells 100, one or more second solar cells 200, and an upper connection electrode 300. and a lower connection electrode 400, and one or more first solar cells 100 and one or more second solar cells 200 may be alternately arranged. For example, 1 or more may mean that there is at least one first solar cell 100 or one second solar cell 100.

The first solar cell 100 includes an N-type crystalline silicon semiconductor substrate 110 having an N-type conduction type; A P-type layer 120 located on the upper surface A1 of the N-type crystalline silicon semiconductor substrate 110, forming a P-N junction with the N-type crystalline silicon semiconductor substrate 110 and having a P-type conduction type; A first upper grid electrode portion 130 located on the P-type layer 120, electrically connected to the P-type layer 120, and including a plurality of first microelectrodes; A first lower electrode portion 140 located on the lower surface B1 of the N-type crystalline silicon semiconductor substrate 110, which is the opposite surface of the upper surface A1, and connected to the N-type crystalline silicon semiconductor substrate 110. You can.

The second solar cell 200 includes a P-type crystalline silicon semiconductor substrate 210 having a P-type conduction type; An N-type layer 220 located on the upper surface A2 of the P-type crystalline silicon semiconductor substrate 210, forming a P-N junction with the P-type crystalline silicon semiconductor substrate 210 and having an N-type conduction type; a second upper grid electrode portion 230 located on the N-type layer 220, electrically connected to the N-type layer 220, and including a plurality of second microelectrodes; A first lower electrode portion 240 located on the lower surface B2 of the P-type crystalline silicon semiconductor substrate 210, which is the opposite side of the upper surface A2, and connected to the P-type crystalline silicon semiconductor substrate 210. You can.

The upper connection electrode 300 includes the plurality of first microelectrodes included in the first solar cell 100 randomly selected from among the first solar cells 100 and a second solar cell adjacent to the randomly selected first solar cell 100. A plurality of the second microelectrodes included in 200 may be electrically connected simultaneously.

According to one implementation, the N-type crystalline silicon semiconductor substrate 110 and the P-type crystalline silicon semiconductor substrate 210 may be formed of single crystalline silicon or polycrystalline silicon. For example, the N-type crystalline silicon semiconductor substrate 110 may be doped with Group 5 elements such as P, As, and Sb as N-type impurities. For example, the P-type crystalline silicon semiconductor substrate 210 may be implemented as a P-type by doping with Group 3 elements B, Ga, In, etc. as P-type impurities.

Meanwhile, although not shown in the drawing, each light-receiving surface of the N-type crystalline silicon semiconductor substrate 110 and the P-type crystalline silicon semiconductor substrate 210 may include uneven structures (not shown) of various shapes such as pyramids, squares, and triangles. You can. The uneven structure (not shown) reduces the reflectance of light incident on the N-type crystalline silicon semiconductor substrate 110 and the P-type crystalline silicon semiconductor substrate 210, thereby improving the photoelectric conversion efficiency of the solar cell module 10. .

The P-type layer 120 may form a P-N junction with the N-type crystalline silicon semiconductor substrate 110. The N-type layer 220 may form a P-N junction with the P-type crystalline silicon semiconductor substrate 210.

For example, the P-type layer 120 may be an emitter layer formed by doping an N-type crystalline silicon semiconductor substrate 110 with an impurity having a P-type conductivity type. Accordingly, the upper surface A1 of the N-type crystalline silicon semiconductor substrate 110 is not a clearly defined area and can be understood as an area where a P-N junction is formed.

For example, the N-type layer 220 may be an emitter layer formed by doping the P-type crystalline silicon semiconductor substrate 210 with an impurity having an N-type conductivity. Accordingly, the upper surface A2 of the P-type crystalline silicon semiconductor substrate 210 is not a clearly defined area and can be understood as an area where a P-N junction is formed.

In this way, when the P-type layer 120, which is an emitter layer, and the N-type crystalline silicon semiconductor substrate 110 have opposite conductivity types, a P-N junction is formed at the interface between the N-type crystalline silicon semiconductor substrate 110 and the P-type layer 120. (junction) may be formed. In addition, if the N-type layer 220, which is an emitter layer, and the P-type crystalline silicon semiconductor substrate 210 have opposite conductivity types, a P-N junction is formed at the interface between the P-type crystalline silicon semiconductor substrate 210 and the N-type layer 220. ) can be formed. In this case, when light is irradiated to the P-N junction, photovoltaic power may be generated due to the photoelectric effect.

The first upper grid electrode unit 130, the second upper grid electrode unit 230, the first lower electrode unit 140, and the second lower electrode unit 240 collect carriers generated by irradiation of light, and It may be a movement path along which a carrier moves to an external electronic device electrically connected to the battery module 10.

The first upper grid electrode unit 130 may refer to an electrode including a grid pattern formed by a plurality of the first microelectrodes. The second upper grid electrode unit 230 may refer to an electrode including a grid pattern formed by a plurality of the second microelectrodes.

The first upper grid electrode unit 130 may be located on the light-receiving surface of the first solar cell 100. The second upper grid electrode unit 230 may be located on the light-receiving surface of the second solar cell.

The first upper grid electrode unit 130 and the second upper grid electrode unit 230 may each have a microgrid pattern. For example, the line width of the microgrid pattern may be several ㎛ to 1 mm, whereby the opening ratio of the first upper grid electrode portion 130 and the second upper grid electrode portion 230 may be formed to be 90% or more. . Accordingly, it is possible to minimize the phenomenon in which incident light is obscured by the first upper grid electrode unit 130 and the second upper grid electrode unit 230.

According to one embodiment, the first microelectrodes include two or more X1 upper microelectrodes 132 extending in a first direction and two or more Y1 extending in a second direction forming a predetermined angle θ with the first direction. It may include an upper microelectrode 134.

According to one embodiment, the second microelectrodes include two or more X2 upper microelectrodes 232 extending in a first direction and two or more Y2 extending in a second direction forming a predetermined angle θ with the first direction. It may include an upper microelectrode 234.

According to one embodiment, the upper connection electrode 300 includes two or more X1 upper microelectrodes 132 included in a first solar cell 100 randomly selected among the first solar cells 100 and Two or more X2 upper microelectrodes 232 included in the second solar cell 200 adjacent to the cell 110 in the first direction; or two or more Y1 upper microelectrodes 134 included in a first solar cell 100 randomly selected among the first solar cells 100 and a second electrode adjacent to the randomly selected first solar cell 110 in the second direction. Two or more Y2 upper microelectrodes 232 included in two solar cells 200 may be electrically connected simultaneously.

According to one implementation, the first direction may be the X direction, and the second direction may be the Y direction. According to another implementation, the first direction may be the Y direction, and the second direction may be the X direction.

According to one embodiment, the predetermined angle θ formed by the first direction and the second direction may be greater than 0° and less than 180°. More preferably, the predetermined angle θ may be about 30° to 150°, about 60° to 120°, about 50° to 150°, or about 30° to 120°.

According to one embodiment, the first upper grid electrode unit 130 may include a square pattern, a pentagonal pattern, a hexagonal pattern, a heptagonal pattern, or an octagonal pattern formed by the first microelectrodes. For example, the first upper grid electrode unit 130 is formed by a square pattern, a pentagonal pattern, a hexagonal pattern, or a heptagonal pattern formed by a plurality of microelectrodes including the X1 upper microelectrode 132 and the Y1 upper microelectrode 134. Alternatively, it may include an octagonal pattern.

According to one embodiment, the second upper grid electrode unit 230 may include a square pattern, a pentagonal pattern, a hexagonal pattern, a heptagonal pattern, or an octagonal pattern formed by the second microelectrodes. For example, the second upper grid electrode unit 230 is formed by a square pattern, a pentagonal pattern, a hexagonal pattern, or a heptagonal pattern formed by a plurality of microelectrodes including the X2 upper microelectrode 232 and the Y2 upper microelectrode 234. Alternatively, it may include an octagonal pattern.

According to another implementation, the first upper grid electrode unit 130 may include a square pattern formed by a plurality of microelectrodes including the X1 upper microelectrode 132 and the Y1 upper microelectrode 134. Additionally, the second upper grid electrode unit 230 may include a square pattern formed by a plurality of microelectrodes including the X2 upper microelectrode 232 and the Y2 upper microelectrode 234. In this case, the predetermined angle θ formed by the first direction and the second direction may be greater than about 0° and less than 180°. Preferably, the predetermined angle θ formed between the first direction and the second direction may be about 30° to 150°, about 60° to 120°, or about 90°.

According to one implementation, the widths of the X1 upper microelectrode 132 and the Y1 upper microelectrode 134 included in the first upper grid electrode 130 may be the same. Additionally, the widths of the X2 upper microelectrode 232 and the Y2 upper microelectrode 234 included in the second upper grid electrode 230 may be the same. For example, the X1 upper microelectrode 132 and the Y1 upper microelectrode 134 included in the first upper grid electrode 130; and the X2 upper microelectrode 232 and the Y2 upper microelectrode 234 included in the second upper grid electrode 230 may all have the same width.

According to another implementation, the widths of the first upper grid electrode 130 and the second upper grid electrode 230 may be different from each other.

According to another embodiment, the width of the X1 upper microelectrode 132 and the Y1 upper microelectrode 134 included in the first upper grid electrode 130 may be about 0.01㎛ to about 100㎛. For example, the width of the X2 upper microelectrode 232 and the Y2 upper microelectrode 234 included in the second upper grid electrode 230 may be about 0.01 μm to about 100 μm.

According to one embodiment, the X1 upper microelectrode 132 and the Y1 upper microelectrode 134 included in the first upper grid electrode 130 may be formed of the same conductive material. Additionally, the X2 upper microelectrode 232 and the Y2 upper microelectrode 234 included in the second upper grid electrode 230 may be formed of the same conductive material.

For example, the X1 upper microelectrode 132 and the Y1 upper microelectrode 134 included in the first upper grid electrode 130; and the X2 upper microelectrode 232 and Y2 upper microelectrode 234 included in the second upper grid electrode 230 may all be formed of the same conductive material.

According to another implementation, a first upper grid electrode 130; and the second upper grid electrode 230 may be formed of different conductive materials.

For example, the conductive material may refer to a material in which carriers generated by irradiation of light can move. For example, the conductive material may include metal or metal oxide. For example, the conductive material may include copper (Cu), silver (Ag), aluminum (Al), nickel (Ni), cobalt (Co), or gold (Au).

According to one embodiment, the area where the first upper grid electrode portion 130 is formed on the upper surface A1 of the N-type crystalline silicon semiconductor substrate 110 is the upper surface A1 of the N-type crystalline silicon semiconductor substrate 110. ) may be about 0.1 to about 10% of the total area. In addition, the area where the second upper grid electrode portion 230 is formed on the upper surface A2 of the P-type crystalline silicon semiconductor substrate 210 is the entire area of the upper surface A2 of the P-type crystalline silicon semiconductor substrate 210. It may be about 0.1 to about 10%.

For example, when the area of the first upper grid electrode part 130 and the area of the second upper grid electrode part 230 satisfy the above range, the area of the first upper grid electrode part 130 and the area of the second upper grid electrode part 130 Since the grid electrode portion 230 is not visible, the aesthetics of the solar cell module 10 may be improved. Additionally, the area of the first upper grid electrode portion 130 and the carrier collection efficiency of the second upper grid electrode portion 230 may be increased, thereby improving the photovoltaic efficiency of the solar cell module.

According to one embodiment, the first lower electrode portion 140 and the second lower electrode portion 240 are respectively formed on the lower surface B1 of the N-type crystalline silicon semiconductor substrate 110 and the P-type crystalline silicon semiconductor substrate 210. It has the same shape as the lower surface B2 and can be formed on the entire bottom of the solar cell 100.

According to another embodiment, the first lower electrode unit 140 and the second lower electrode unit 240 include a plurality of micro electrodes in the same manner as the first upper grid electrode unit 130 and the second upper grid electrode unit 230. It may include a microgrid pattern formed by . For example, the microgrid pattern may include a square pattern, a pentagonal pattern, a hexagonal pattern, a heptagonal pattern, or an octagonal pattern.

According to one embodiment, the first lower electrode unit 140 includes two or more X1 lower microelectrodes (not shown) extending in the first direction and two or more Y1 lower microelectrodes (not shown) extending in the second direction. It includes, and the second lower electrode 240 may include two or more X2 lower microelectrodes (not shown) extending in the first direction and two or more Y2 lower microelectrodes (not shown) extending in the second direction. You can.

According to one embodiment, the first lower electrode portion 140 and the second lower electrode portion 240 may include the same grid electrode pattern as the first upper grid electrode portion 130 and the second upper grid electrode 140. You can. For example, the first lower electrode portion 140 and the second lower electrode portion 240 are each formed by a plurality of microelectrodes in the same manner as the first upper grid electrode 130 and the second upper grid electrode 230. It may include a square pattern, a pentagonal pattern, a hexagonal pattern, a heptagonal pattern, or an octagonal pattern.

According to another implementation, the first lower electrode portion 140 and the second lower electrode portion 240 may include the same grid pattern as the first upper grid electrode 130 and the second upper grid electrode 230, respectively. there is.

According to one embodiment, the lower connection electrode 400, like the upper connection electrode 300, connects two or more lower microelectrodes included in the first solar cell 100 to two lower microelectrodes included in the adjacent second solar cell 200. It can be electrically connected to the above lower microelectrodes at the same time.

For example, the lower connection electrode 400 includes two or more 2 Two or more X2 lower microelectrodes (not shown) included in the solar cell 200; or two or more Y1 lower microelectrodes (not shown) included in the randomly selected first solar cell 100 and two or more Y2 included in the second solar cell 200 adjacent to the first solar cell 100 in the second direction. The lower microelectrodes (not shown) can be electrically connected simultaneously.

According to one embodiment, the upper connection electrode 300 and the lower connection electrode are each formed side by side in one direction, and the direction in which the upper connection electrode 300 and the direction in which the lower connection electrode are formed may be in a twisted position.

For example, when the upper connection electrode 300 extends in the second direction, the lower connection electrode extends in the first direction and may be in a twisted position. For example, when the upper connection electrode 300 extends in the first direction, the lower connection electrode extends in the second direction and may be in a twisted position. The twisted position may mean a state in which two straight lines located on different planes in space do not meet each other, but are not parallel to each other.

According to one embodiment, the first solar cell 100 and the second solar cell 200 are spaced apart at a predetermined interval to form a gap region 50, and the upper connection electrode 300 and the lower connection electrode 400 may be placed on the gap area 50.

For example, the gap region 50 allows carriers generated by the photoelectric effect to move between the first solar cell 100 and the second solar cell 200 having different conductivity types, thereby causing the solar cell module 10 to move. Problems with reduced power generation efficiency can be prevented.

Additionally, as the upper connection electrode 300 and the lower connection electrode 400 are disposed on the gap area 50, the problem of the grid pattern formed by the gap area 50 being visible can be effectively prevented. Accordingly, the aesthetics of the solar cell module 10 may be improved.

According to one implementation, the width of the gap region 50 may be about 1 to 1,000 μm. For example, the width of the gap region 50 is about 1 to 500 μm, about 1 to 300 μm, about 1 to 100 μm, about 1 to 50 μm, about 5 to 1,000 μm, about 10 to 1,000 μm, or about 20 μm. It may be from 1,000 ㎛.

For example, when the gap area 50 satisfies the above width range, the number of solar cells arranged per unit area may increase, thereby improving the photovoltaic efficiency of the solar cell module 10. Additionally, the spacing between solar cells is narrow, so aesthetics can be further improved.

According to one implementation, the width of the upper connection electrode 300 and the lower connection electrode 400 may be larger than the width of the gap region 50. For example, the widths of the upper connection electrode 300 and the lower connection electrode 400 may each be about 10 to 1,500 μm. Preferably, the width of the connection electrode 300 and the lower connection electrode 400 is about 10 to 1,400 μm, about 10 to 1,300 μm, about 10 to 1,200 μm, about 10 to 1,100 μm, and about 10 to 1,000 μm, respectively. It may be about 20 to 1,500 μm, about 30 to 1,500 μm, about 40 to 1,500 μm, or about 50 to 1,500 μm.

For example, when the widths of the upper connection electrode 300 and the lower connection electrode 400 satisfy the above range, the upper connection electrode 300 and the lower connection electrode 400 not only effectively cover the gap area 50, but also , the problem of the upper connection electrode 300 and the lower connection electrode 400 being visible can be effectively prevented. Additionally, the amount of light reflected by the upper connection electrode 300 and the lower connection electrode 400 is reduced, so that the power generation efficiency of the solar cell module 10 can be further improved.

According to one embodiment, the gap area 50 may be completely covered by the upper connection electrode 300 and the lower connection electrode 400. In this case, the aesthetics of the solar cell module 10 can be further improved.

According to one embodiment, the upper connection electrode 300 includes all of the upper microelectrodes X1 included in the randomly selected first solar cell and the upper X2 included in the second solar cell adjacent to the randomly selected first solar cell in the first direction. All microelectrodes; Or all of the Y1 upper microelectrodes included in the arbitrarily selected first solar cell and all of the two or more Y2 upper microelectrodes included in the second solar cell adjacent to the arbitrarily selected first solar cell in the second direction; can be electrically connected at the same time. there is.

According to one embodiment, the first solar cell 100 is disposed between an N-type crystalline silicon semiconductor substrate 110 and the first lower electrode portion 140 and has an N-type back electric field layer (not shown) having an N-type conduction type. ), and the first lower electrode unit 140 may be connected to the N-type rear surface layer (not shown).

For example, the N-type backside electric field layer (not shown) may be a backside electric field layer (BSF) formed by doping the N-type crystalline silicon semiconductor substrate 110 with an impurity having an N conductivity type. Therefore, the lower surface (B1) of the N-type crystalline silicon semiconductor substrate 110 is not a clearly defined area, and can be understood as an area that partitions the N-type back surface layer (BSF) in the N-type crystalline silicon semiconductor substrate 110. You can.

According to one embodiment, the second solar cell 200 is disposed between the P-type crystalline silicon semiconductor substrate 210 and the second lower electrode portion 240 and has a P-type back electric layer (not shown) having a P-type conduction type. ), and the second lower electrode unit 240 may be connected to the P-type rear surface layer (not shown).

For example, the P-type backside electric field layer (not shown) may be a backside electric field layer (BSF) formed by doping the P-type crystalline silicon semiconductor substrate 210 with an impurity having a P-type conductivity type. Therefore, the lower surface (B2) of the P-type crystalline silicon semiconductor substrate 210 is not a clearly defined area, and can be understood as an area that partitions the P-type backside electric field layer (BSF) in the P-type crystalline silicon semiconductor substrate 210. You can.

The N-type back electric field layer (not shown) and the P-type back electric field layer (not shown) prevent carriers from moving to the back of the N-type crystalline silicon semiconductor substrate 110 and the P-type crystalline silicon semiconductor substrate 210, respectively, to recombine. This can be prevented, and as a result, the open-circuit voltage (Voc) of the solar cell module 10 increases, thereby improving the efficiency of the solar cell module 10.

According to one embodiment, the first solar cell 100 and the second solar cell 200 include a first anti-reflection film (not shown) and a second anti-reflection film located on the P-type layer 120 and the N-type layer 220. (not shown) may further be included. At this time, the first upper grid electrode portion 140 and the second upper grid electrode portion 240 may penetrate the first anti-reflection layer and the second anti-radiation layer and connect to the P-type layer 120 and the N-type layer 220, respectively. there is.

According to another embodiment, the first solar cell 100 and the second solar cell 200 include a first protective film (not shown) and a first protective film (not shown) below the first anti-reflective film (not shown) and the second anti-reflective film (not shown), respectively. It may further include a second protective film (not shown). At this time, the first upper grid electrode unit 140 and the second upper grid electrode unit 240 penetrate the first anti-reflection film, the first protective film, the second anti-radiation film, and the second protective film to form the P-type layer 120. and N-type layer 220, respectively.

The first anti-reflection film and the second anti-reflection film can passivate defects existing in the surface or bulk of the P-type layer 120 and the N-type layer 220, that is, the emitter layer, and reduce the reflectance of incident sunlight. When defects present in the emitter layer are passivated, recombination sites of minority carriers are removed, thereby increasing the open-circuit voltage (Voc) of the solar cell module 10. Additionally, when the reflectance of sunlight is reduced, the amount of light reaching the P-N junction increases, thereby increasing the short-circuit current (Isc) of the solar cell module 10. Accordingly, the photoelectric conversion efficiency of the solar cell module 10 can be improved.

For example, the first anti-reflection film and the second anti-reflection film are any one selected from the group consisting of a silicon nitride film, a hydrogen-containing silicon nitride film, a silicon oxide film, a silicon oxynitride film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ It may have a single layer structure or a multilayer structure combining two or more layers. The first anti-reflection film and the second anti-reflection film can reduce reflection of light and induce absorption into the solar cell module 10.

The first anti-reflection film and the second anti-reflection film may include surface structures in various uneven shapes such as pyramids, squares, and triangles. The surface structure can be formed by increasing the surface roughness of the first anti-reflection film and the second anti-reflection film by various methods such as dry etching, and the surface structure of the first anti-reflection film and the second anti-reflection film. Can reduce reflection of incident light and improve photoelectric conversion efficiency of the solar cell module 10.

The first protective film and the second protective film are formed on the light-receiving surfaces of the N-type crystalline silicon semiconductor substrate 110 and the P-type crystalline silicon semiconductor substrate 210, respectively, to prevent recombination of photo charges generated by incident sunlight. Prevents defects due to lattice mismatch as the first anti-reflection film and the second anti-reflection film are formed directly on the N-type crystalline silicon semiconductor substrate 110 and the P-type crystalline silicon semiconductor substrate 210, respectively. can be reduced. This protective film 170 may be formed including a-Si, a-SiOx, or a-SiC. In particular, a-SiOx and a-SiC have a bandgap energy of 1.8 eV or more, so the absorption coefficient of light is small, so the amount of light incident on the N-type crystalline silicon semiconductor substrate 110 and the P-type crystalline silicon semiconductor substrate 210 This decrease can be prevented.

For example, the first protective film and the second protective film may be formed of an inorganic film such as Al ₂ O ₃ .

Figure 3 is a plan view schematically showing a modified example of the solar cell of Figure 1.

Referring to FIG. 3, the first upper grid electrode portion 110 and the second upper grid electrode portion 210 are W1 extending in a third direction forming a predetermined angle with the first direction and the second direction, respectively. It may further include an upper microelectrode 136 and a W2 upper microelectrode 236, respectively. For example, the third direction may be the W direction. For example, the third direction may be the X direction or the Y direction.

N-type described in FIG. 3 may mean a case where the crystalline silicon semiconductor substrate has an N-type conduction type. P-type may refer to a case where the crystalline silicon semiconductor substrate has a P-type conduction type.

According to one implementation, the first upper grid electrode unit 110 and the second upper grid electrode unit 210 may have a microgrid pattern patterned to have a honeycomb shape. For example, the first upper grid electrode unit 110 has a hexagonal pattern formed by a plurality of microelectrodes including the X1 upper microelectrode 132, the Y1 upper microelectrode 134, and the W1 upper microelectrode 136. It can be included. For example, the second upper grid electrode unit 210 has a hexagonal pattern formed by a plurality of microelectrodes including the X2 upper microelectrode 232, the Y1 upper microelectrode 234, and the W1 upper microelectrode 236. It can be included.

Accordingly, the microgrid pattern of the first upper grid electrode portion 110 and the second upper grid electrode portion 210 can have a more dense structure, whereby the charges generated by the photoelectric effect can disperse and flow. As the path increases, the efficiency of the solar cell 20 can be improved.

The above has been described with reference to the embodiments shown in the drawings, but these are merely examples, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached patent claims.

10, 20: solar cell module 50: gap area,
100: first solar cell 200: second solar cell
300: upper connection electrode 400: lower connection electrode
110: N-type crystalline silicon semiconductor substrate
210: P-type crystalline silicon semiconductor substrate
120: P-type layer 220: N-type layer
132: X1 microelectrode 134: Y1 microelectrode
136: W1 microelectrode 232: X2 microelectrode
234: Y2 microelectrode 236: W2 microelectrode
130: first upper grid electrode portion 230: second upper grid electrode portion
140: first lower electrode portion 240: second lower electrode portion
A: Top B: Bottom

Claims (20)

An N-type crystalline silicon semiconductor substrate having an N-type conductivity; a P-type layer located on the upper surface of the N-type crystalline silicon semiconductor substrate, forming a PN junction with the N-type crystalline silicon semiconductor substrate and having a P-type conduction type; a first upper grid electrode portion located on the P-type layer, electrically connected to the P-type layer, and including a plurality of first microelectrodes; At least one first solar cell including a first lower electrode portion located on the lower surface of the N-type crystalline silicon semiconductor substrate, which is the opposite side of the upper surface, and connected to the N-type crystalline silicon semiconductor substrate,
A P-type crystalline silicon semiconductor substrate having a P-type conductivity; an N-type layer located on the upper surface of the P-type crystalline silicon semiconductor substrate and having an N-type conductivity forming a PN junction with the P-type crystalline silicon semiconductor substrate; a second upper grid electrode portion located on the N-type layer and connected to the N-type layer and including a plurality of second microelectrodes; At least one second solar cell located on the lower surface of the P-type crystalline silicon semiconductor substrate, which is opposite to the upper surface, and including a second lower electrode portion connected to the P-type crystalline silicon semiconductor substrate,
an upper connection electrode connecting the first upper grid electrode portion and the second upper grid electrode portion, and
It includes a lower connection electrode connecting the first lower electrode portion and the second lower electrode portion,
The first solar cell and the second solar cell are arranged alternately with each other,
The first upper grid electrode portion includes a grid pattern formed by the first microelectrodes,
The second upper grid electrode unit includes a grid pattern formed by the second microelectrodes,
The upper connection electrode includes a plurality of first microelectrodes included in a first solar cell arbitrarily selected from among the first solar cells and a plurality of second microelectrodes included in the second solar cell adjacent to the arbitrarily selected first solar cell. Connect the microelectrodes electrically at the same time,
The width of the first microelectrode and the width of the second microelectrode are constant,
The first solar cell and the second solar cell are spaced apart at a predetermined interval to form a gap area, and the gap area is completely covered by the upper connection electrode and the lower connection electrode. According to paragraph 1,
The first microelectrodes include two or more X1 upper microelectrodes extending in a first direction and two or more Y1 upper microelectrodes extending in a second direction forming a predetermined angle with the first direction,
The second microelectrodes include two or more X2 upper microelectrodes extending in a first direction and two or more Y2 upper microelectrodes extending in a second direction forming a predetermined angle with the first direction. According to paragraph 2,
The connection electrode includes two or more X1 upper microelectrodes included in a first solar cell randomly selected among the first solar cells and two or more X1 included in the second solar cell adjacent to the randomly selected first solar cell in the first direction. X2 upper microelectrode; or
Two or more Y1 upper microelectrodes included in a first solar cell randomly selected among the first solar cells and two or more Y2 upper microelectrodes included in the second solar cell adjacent to the randomly selected first solar cell in the first direction A solar cell module that electrically connects simultaneously. According to paragraph 3,
The upper connection electrode includes all of the X1 upper microelectrodes included in the randomly selected first solar cell and all of the X2 upper microelectrodes included in the second solar cell adjacent to the randomly selected first solar cell in a first direction; or
Electrically simultaneously connecting all of the Y1 upper microelectrodes included in the arbitrarily selected first solar cell and all of the two or more Y2 upper microelectrodes included in the second solar cell adjacent to the arbitrarily selected first solar cell in a second direction, solar module. According to paragraph 2,
The first direction is the X direction, and the second direction is the Y direction. According to paragraph 2,
A solar cell module wherein a predetermined angle formed by the first direction and the second direction is greater than 0° and less than 180°. According to paragraph 2,
The grid pattern included in the first upper grid electrode unit includes a square pattern, a pentagonal pattern, a hexagonal pattern, a heptagonal pattern, or an octagonal pattern formed by a plurality of microelectrodes including the X1 upper microelectrode and the Y1 upper microelectrode. do,
The grid pattern included in the second upper grid electrode unit includes a square pattern, a pentagonal pattern, a hexagonal pattern, a heptagonal pattern, or an octagonal pattern formed by a plurality of microelectrodes including the X2 upper microelectrode and the Y2 upper microelectrode. solar cell module. According to paragraph 2,
The grid pattern included in the first upper grid electrode unit includes a square pattern formed by a plurality of microelectrodes including the X1 upper microelectrode and the Y1 upper microelectrode,
The grid pattern included in the second upper grid electrode portion includes a square pattern formed by a plurality of microelectrodes including the X2 upper microelectrode and the Y2 upper microelectrode. According to paragraph 2,
The first upper grid electrode unit and the second upper grid electrode unit further include a W1 upper microelectrode and a W2 upper microelectrode extending in a third direction forming a predetermined angle with the first direction and the second direction, respectively. Including solar cell modules. According to clause 9,
The grid pattern included in the first upper grid electrode unit includes a hexagonal pattern formed by a plurality of microelectrodes including the X1 upper microelectrode, the Y1 upper microelectrode, and the W1 upper microelectrode,
The grid pattern included in the second upper grid electrode portion includes a hexagonal pattern formed by a plurality of microelectrodes including the X2 upper microelectrode, the Y2 upper microelectrode, and the W2 upper microelectrode. According to paragraph 1,
The area of the upper surface of the N-type crystalline silicon semiconductor substrate where the first upper grid electrode portion is formed is 0.1 to 10% of the total area of the upper surface of the N-type crystalline silicon semiconductor substrate,
An area of the upper surface of the P-type crystalline silicon semiconductor substrate where the second upper grid electrode portion is formed is 0.1 to 10% of the total area of the upper surface of the P-type crystalline silicon semiconductor substrate. According to paragraph 1,
The first lower electrode unit includes two or more X1 lower microelectrodes extending in a first direction and two or more Y1 lower microelectrodes extending in a second direction,
The second lower electrode portion includes two or more X2 lower microelectrodes extending in a first direction and two or more Y2 lower microelectrodes extending in a second direction. According to clause 12,
The lower connection electrode includes: two or more X1 lower microelectrodes included in a randomly selected first solar cell and two or more X2 lower microelectrodes included in a second solar cell adjacent to the randomly selected first solar cell in a first direction; or
electrically simultaneously connecting two or more Y1 lower microelectrodes included in a randomly selected first solar cell and two or more Y2 lower microelectrodes included in a second solar cell adjacent to the randomly selected first solar cell in a second direction, solar module. According to paragraph 1,
The upper connection electrode and the lower connection electrode are each formed side by side in one direction,
A solar cell module, wherein the direction in which the upper connection electrode is formed and the direction in which the lower connection electrode is formed are in a twisted position. delete According to paragraph 1,
A solar cell module wherein the gap region has a width of 1 to 1,000 ㎛. According to paragraph 1,
A solar cell module wherein the widths of the upper connection electrode and the lower connection electrode are each 10 to 1,500 ㎛. delete According to paragraph 1,
The first solar cell further includes an N-type back surface electric layer disposed between the N-type crystalline silicon semiconductor substrate and the first lower electrode portion and having an N-type conduction type, wherein the first lower electrode portion is the N-type back electrode portion. Connect with all walks of life,
The second solar cell further includes a P-type back surface electric layer disposed between the P-type crystalline silicon semiconductor substrate and the second lower electrode portion and having a P-type conduction type, wherein the second lower electrode portion is the P-type rear surface layer. A solar cell module that connects to all classes. According to paragraph 1,
The first solar cell further includes a first anti-reflection layer disposed on the P-type layer, and the first upper grid electrode portion penetrates the first anti-reflection layer and connects to the P-type layer,
The second solar cell further includes a second anti-reflection layer disposed on the N-type layer, and the second upper grid electrode portion penetrates the second anti-reflection layer and connects to the N-type layer.