KR102600184B1 - Display device - Google Patents

Abstract

A display device according to the present invention includes a substrate, a touch electrode, a touch pad, a touch routing line, and a link line. A display area in which pixels are arranged and a non-display area outside the display area are defined on the substrate. The touch electrode is disposed on the display area. The touch pad is disposed on the non-display area. The touch routing line is disposed on the non-display area and electrically connects the touch electrode and the touch pad. The link line is disposed on the non-display area and is connected to the touch pad and extends from the touch pad to one end of the substrate, or is connected to a routing line and extends from the routing line to one end of the substrate.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

Recently, in line with the development of multimedia and the need for a display device that can properly display it, a display device with low price and high display quality (video expression, resolution, brightness, contrast ratio, and color reproduction, etc.) has been developed. It is being actively developed. These display devices form an interface between the user and the display device through various input devices such as a keyboard, mouse, trackball, joystick, and digitizer.

However, using the above-mentioned input device requires learning how to use it and causes inconveniences such as taking up space for installation and operation, making it difficult to improve the completeness of the product. Accordingly, the demand for display device input devices that are convenient, simple, and capable of reducing malfunctions is increasing day by day. In response to such demands, a touch device has been proposed that allows a user to input information by directly touching or approaching the screen with a hand or a pen while looking at the display device. When a touch element is adopted, it is applied to various display devices because of the convenience of not only enabling input without using a separate input device, but also allowing the user to quickly and easily manipulate information displayed on the screen.

Depending on its structure, touch devices can be divided into add-on type, on-cell type, and integrated type. The add-on type is a method of manufacturing the display device and the touch panel separately and then attaching the touch panel to the top panel of the display device. The on-cell type is a method of forming a touch element directly on the top surface of a display device. The integrated type is a method of constructing a touch element inside the top panel of the display device.

These touch elements can be applied to various display devices, and especially when applied to electroluminescent display devices, the elements that make up the touch elements are covered with the upper or lower part of the encapsulation film to protect the light emitting part of the electroluminescent display device. can be formed in That is, the touch driving electrodes constituting the touch driving signal transmission channel and the touch sensing electrodes constituting the touch recognition signal receiving channel are disposed on the upper and/or lower surfaces of the encapsulation film covering the display elements of the electroluminescent display device. is formed

After the manufacturing of the display device including the touch element is completed, in addition to the pixel array inspection, an additional inspection process is performed to check for defects in the touch element.

When performing an inspection process to check touch defects of a touch element, inspection pads for this need to be formed. However, when the touch inspection pads are formed on the non-display area of the display panel, there is a problem in that a narrow bezel cannot be implemented as the bezel area increases. The purpose of the present invention is to provide a display device implementing a narrow bezel.

A display device according to an embodiment of the present invention includes a substrate, a touch electrode, a touch pad, a touch routing line, and a link line. A display area in which pixels are arranged and a non-display area outside the display area are defined on the substrate. The touch electrode is disposed on the display area. The touch pad is disposed on the non-display area. The touch routing line is disposed on the non-display area and electrically connects the touch electrode and the touch pad. The link line is disposed on the non-display area and is connected to the touch pad and extends from the touch pad to one end of the substrate, or is connected to the touch routing line and extends from the touch routing line to one end of the substrate.

The link line and the touch pad are disposed on different layers with at least one insulating film interposed therebetween, and may be connected to each other through a contact hole penetrating the insulating film.

The link line and the touch routing line are disposed on different layers with at least one insulating film interposed therebetween, and may be connected to each other through an auxiliary contact hole penetrating the insulating film.

The link line may be a branched portion from the touch routing line.

The link line and the touch routing line may be arranged on the same layer. The link line and the touch routing line may be electrically connected through a jumping line disposed on a different layer with at least one insulating film interposed between the link line and the touch routing line.

One end of the link line may correspond to one end of the substrate.

At least a portion of the link line may be in direct contact with the substrate or may be in contact with the first buffer layer.

The link line may be disposed on the same layer as the gate electrode of the display area. The touch pad may be disposed on the same layer as the source electrode and drain electrode of the display area. The link line and the touch pad may be connected to each other through a first contact hole penetrating an insulating film interposed therebetween.

The touch pad may be disposed on the same layer as the source electrode and drain electrode of the display area. The link line may be disposed on the touch pad with at least one insulating film interposed therebetween. The link line and the touch pad may be connected to each other through a first contact hole penetrating the insulating film.

The link line may include the same material as that forming the touch electrode or touch routing line.

The display device according to the present invention may further include an encapsulation film that covers at least the pixels of the display area. The touch electrode may be disposed on the encapsulation film.

The pixel may include a transistor and a light-emitting device electrically connected to the transistor. The transistor includes a semiconductor layer disposed on a substrate, a gate insulating film disposed on the semiconductor layer, a gate electrode disposed on the gate insulating film and overlapping at least a portion of the semiconductor layer, an interlayer insulating film disposed on the gate electrode, and an interlayer insulating film. It is disposed and may include a source electrode and a drain electrode respectively connected to one side and the other side of the semiconductor layer through contact holes penetrating the interlayer insulating film, and a planarization film disposed on the source electrode and the drain electrode.

The link line may be disposed on the same layer as the gate electrode. The touch pad may be disposed on the same layer as the source electrode and the drain electrode. The link line and the touch pad may be connected to each other through a first contact hole penetrating the interlayer insulating film.

The display device according to the present invention may further include a first open hole penetrating the interlayer insulating film at one end of the substrate.

The display device according to the present invention may further include a second open hole penetrating the planarization film at one end of the substrate.

The touch pad may be disposed on the same layer as the source electrode and the drain electrode. Link lines may be placed on the planarization film. The link line and the touch pad may be connected to each other through a first contact hole penetrating the planarization film.

The display device according to the present invention may further include a first open hole penetrating through at least one of the gate insulating layer and the interlayer insulating layer at one end of the substrate.

The first open hole may expose the substrate.

The display device according to the present invention may further include a second open hole penetrating the planarization film at one end of the substrate.

A display device according to another embodiment of the present invention includes a substrate and a link line. On the substrate, a touch electrode, a touch pad, and a touch routing line connecting the touch electrode and the touch pad are disposed. The link line extends from the touch pad or touch routing line to one end of the substrate. One end of the link line remains separated at the edge portion of the substrate.

The link line and the touch pad are disposed on different layers with at least one insulating film interposed therebetween, and may be connected to each other through a contact hole penetrating the insulating film.

The link line and the touch routing line are disposed on different layers with at least one insulating film interposed therebetween, and may be connected to each other through an auxiliary contact hole penetrating the insulating film.

The link line may be a part branched from the touch routing line.

The link line and the touch routing line may be arranged on the same layer. The link line and the touch routing line may be electrically connected through a jumping line disposed on a different layer with at least one insulating film interposed between the link line and the touch routing line.

One end of the link line may correspond to one end of the substrate.

The display device according to the present invention may further include pixels disposed on a substrate, and an encapsulation film covering the pixels. The touch electrode may be disposed on the encapsulation film.

In the present invention, the inspection pads used during the inspection process are placed on the outside of the display panel and are removed after the inspection process. Accordingly, since there is no need to separately allocate areas for forming touch inspection pads on the display panel, there is an advantage in that the bezel area can be significantly reduced. Additionally, by deleting the touch inspection pads on the display panel, a certain amount of space is secured, which has the advantage of improving design freedom.

In the present invention, since the link line connecting the touch pad and the touch inspection pad or the touch routing line and the touch inspection pad is formed on the top layer before the scribing process, there is a problem that the link line is exposed to the etching process environment and is damaged. can be prevented. In addition, since the present invention can remove the inorganic and/or organic film in the scribing area in advance before forming the link line, not only can the generation and dispersion of foreign substances during the scribing process be minimized, but also the film thickness can be reduced. It has the advantage of minimizing cutting defects caused by cutting.

1 is a plan view showing a display device according to the present invention.
Figure 2 is an enlarged view of area A of Figure 1.
Figure 3 is an enlarged view of area B of Figure 2.
FIG. 4 is a plan view schematically showing the configuration of the display device in FIG. 1 excluding the touch element.
Figure 5 is a cross-sectional view of Figure 1 taken along II'.
Figure 6 is a plan view schematically showing a display device according to the present invention.
7 to 10 are diagrams showing the inspection area formation process and scribing process in time series according to the first embodiment of the present invention.
11 to 14 are diagrams showing the inspection area formation process and scribing process in time series according to the second embodiment of the present invention.
Figure 15 is a plan view schematically showing a display device according to a third embodiment of the present invention.
Figure 16 is a cross-sectional view of Figure 15 taken along line III-III'.
Figure 17 is a plan view schematically showing a display device according to a fourth embodiment of the present invention.
Figure 18 is a cross-sectional view taken along line IV-IV' of Figure 17.
Figure 19 is a cross-sectional view taken along line V-V' of Figure 17.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. In describing various embodiments, the same components may be representatively described at the beginning and omitted in other embodiments.

Terms containing ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

1 is a plan view showing a display device according to the present invention. Figure 2 is an enlarged view of area A of Figure 1. Figure 3 is an enlarged view of area B of Figure 2. FIG. 4 is a plan view schematically showing the configuration of the display device in FIG. 1 excluding the touch element. Figure 5 is a cross-sectional view of Figure 1 taken along II'.

Figure 3 is a cross-sectional view of Figure 1 taken along line II'. To simplify the explanation, FIG. 1 shows only the configuration of the touch element of the display device, and FIG. 4 shows only the configuration of the display device. In FIGS. 1 to 4 , for convenience of explanation, an electroluminescence display device will be used as an example.

In the drawings, the structure in which the touch device TD is formed on the encapsulation film is explained as an example, but the structure is not limited thereto. For example, the present invention can be applied to an on-cell type, add-on type, or integrated type touch device structure.

Referring to FIG. 1 , the display panel 10 includes a substrate SUB including a display area DA on which an image is displayed and a non-display area NDA outside the display area. The touch device (TD) is formed on the substrate (SUB). The touch element TD includes a plurality of first touch electrodes (Tx1 to Tx6) and a plurality of second touch electrodes (Rx1 to Rx4) arranged to intersect each other, and a plurality of first and second touch electrodes (Tx1). ~Tx6, Rx1 ~ Rx4) a plurality of first touch routing wires (TW1 ~ TW6) and a plurality of second touch routing wires (RW1 ~ RW4) respectively connected, and a plurality of first and second touch routing wires ( It includes a plurality of first touch pads (TP1 to TP6) and a plurality of second touch pads (RP1 to RP4) respectively connected to TW1 to TW6 and RW1 to RW4. In the drawing, six first touch electrodes (Tx1 to Tx6), first touch routing wires (TW1 to TW6), and first touch pads (TP1 to TP6) are shown, respectively, and four second touch electrodes are respectively shown. (Rx1 to Rx4), second touch routing wires (RW1 to RW4), and second touch pads (RP1 to RP4) are formed as an example, but the present invention is not limited thereto. That is, this is just an example for explaining the touch device, and may include a plurality of first and second touch electrodes, first and second touch routing wires, and first and second touch pads.

The plurality of first touch electrodes Tx1 to Tx6 are aligned with each other along the first direction (e.g., y-axis direction) on the encapsulation film ENC disposed in the display area DA of the substrate SUB. It is arranged and extends in a second direction (eg, x-axis direction) that intersects the first direction. Each of the plurality of first touch electrodes (Tx1 to Tx6) has a structure in which a plurality of first touch electrode patterns formed of mesh patterns such as triangles, squares, diamonds, polygons, etc. are connected in a continuous form, but the present invention This is not limited to this.

The plurality of second touch electrodes Rx1 to Rx4 are arranged side by side in the second direction on the encapsulation film ENC disposed in the display area DA of the substrate SUB and extend in the first direction. do. Like the first touch electrodes, the plurality of second touch electrodes (Rx1 to Rx4) may also have a structure in which a plurality of second touch electrode patterns in which mesh patterns are formed in triangles, squares, diamonds, polygons, etc. are connected in a continuous form. , the present invention is not limited thereto. For example, the first and second electrode patterns can be made into a variety of different shapes to improve touch recognition.

A plurality of first and second touch electrodes (Tx1 to Tx6, An insulating layer (not shown) may be disposed between Rx1 to Rx4), or insulating patterns (not shown) may be disposed only at their intersections.

The plurality of first touch routing wires TW1 to TW6 are disposed in the non-display area NDA of the substrate SUB and are respectively connected to the plurality of first touch electrodes Tx1 to Tx6. The first touch routing wires (TW1, TW3, TW5) are connected to the left ends of the first touch electrodes (Tx1, Tx3, Tx5) arranged in the odd row, and are connected to the non-display area (on the left side of the display area DA) It extends along the NDA) to the non-display area (NDA) below the display area (DA). The first touch routing wires (TW2, TW4, TW6) are connected to the right ends of the first touch electrodes (Tx2, Tx3, Tx6) arranged in the even-numbered rows, and are connected to the non-display area (on the right side of the display area DA) It extends along the NDA) to the non-display area (NDA) below the display area (DA).

The plurality of second touch routing wires (RW1 to RW4) are disposed in the non-display area (NDA) of the substrate SUB and are respectively connected to the lower ends of the plurality of second touch electrodes (Rx1 to Rx4) to form the display area. (DA) extends to the lower non-display area (NDA).

The plurality of first touch pads TP1 to TP6 are disposed at the ends of the non-display area NDA below the display area DA of the substrate SUB and are connected to the plurality of first touch routing wires TW1 to TW6. Each is connected. The first touch pads TP1, TP3, and TP5 are respectively connected to the first touch routing wires TW1, TW3, and TW5 connected to the first touch electrodes Tx1, Tx3, and Tx5 in odd rows. The first touch pads TP2, TP4, and TP6 are respectively connected to the first touch routing wires TW2, TW4, and TW6 connected to the first touch electrodes Tx2, Tx4, and Tx6 in the even-numbered rows.

The plurality of second touch pads RP1 to RP4 are disposed at the ends of the non-display area NDA below the display area DA of the substrate SUB and are connected to the plurality of second touch routing wires RW1 to RW4. Each is connected. The plurality of second touch pads RP1 to RP4 may be disposed between the group of first touch pads TP1, TP3, and TP5 and the group of first touch pads TP2, TP4, and TP6.

The first and second touch routing wires (TW1 to TW6, RW1 to RW4) and the first and second touch pads (TP1 to TP6, RP1 to RP4) may be formed in a single-layer or multi-layer structure. When the first and second touch routing wires (TW1 to TW6, RW1 to RW4) are a single layer, a metal layer such as Al, AlNd, Mo, MoTi, Cu, CuOx, Cr, or a transparent conductive material layer such as ITO or IZO. can be formed. When the first and second touch routing wires (TW1 to TW6, RW1 to RW4) have a multi-layer structure, they are made of metal materials such as Al, AlNd, Mo, MoTi, Cu, CuOx, and Cr, and transparent conductive materials such as ITO and IZO. Transparent conductive materials formed may be formed in a laminated form. For example, the first and second touch routing lines (TW1 to TW6 and RW1 to RW4) may be formed in a three-layer structure of Ti/Al/Ti or a four-layer structure of ITO/Ti/Al/Ti.

Referring to FIG. 2, the first touch electrode (Tx2) is arranged to extend in a second direction (for example, the x-axis direction), and the second touch electrode (Rx2) is disposed in a first direction (for example, It is arranged to extend in the y-axis direction. The first touch electrode (Tx2) includes a first mesh pattern (TxP) and the second touch electrode (Rx2) includes a second mesh pattern (RxP). Each of the first mesh pattern (TxP) and the second mesh pattern (RxP) forms a diamond shape and may have a structure in which multiple diamond shapes are connected in a continuous form. Each of the first mesh pattern (TxP) and the second mesh pattern (RxP) may be polygonal, such as a triangle, square, or pentagon, or circular, in addition to a diamond shape. In this embodiment, it will be explained as an example that each of the first mesh pattern (TxP) and the second mesh pattern (RxP) forms a diamond shape.

A bridge electrode (RCO) is disposed at an intersection where the first touch electrode (Tx2) and the second touch electrode (Rx2) intersect to prevent the first touch electrode (Tx2) and the second touch electrode (Rx2) from being connected to each other. Specifically, the first touch electrode Tx2 is arranged continuously along the second direction as one body. The second touch electrode (Rx2) is not connected to the first touch electrode (Tx2) but is connected through the bridge electrode (RCO) so that it can be arranged along the first direction. That is, the second touch electrode (Rx2) can be disposed in electrical continuity by contacting the bridge electrode (RCO) at the intersection with the first touch electrode (Tx2). In this embodiment, the second touch electrode (Rx2) is connected through the bridge electrode (RCO), but differently, the first touch electrode (Tx2) may be connected through the bridge electrode.

Referring to FIG. 3, the first touch electrode (Tx2) is formed with a first mesh pattern (TxP) and the second touch electrode (Rx2) is formed with a second mesh pattern (RxP). The first touch electrode (Tx2) and the second touch electrode (Rx2) are arranged to be spaced apart from each other so as not to be connected to each other.

At least one light emitting area (EA) is disposed between the first mesh pattern (TxP) of the first touch electrode (Tx2) and the second mesh pattern (TxP) of the second touch electrode (Rx2). The emission area EA may be an area where at least one subpixel is arranged to emit light. As an example, at least two or more subpixels may be arranged in the emission area EA.

The first touch electrode (Tx2) and the second touch electrode (Rx2) may be made of metal. The metal may be any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), or an alloy thereof. and may be composed of a single layer or multiple layers thereof.

As described above, since the first touch electrode (Tx2) and the second touch electrode (Rx2) are made of metal, the first mesh pattern (TxP) of the first touch electrode (Tx2) and the first mesh pattern (TxP) of the second touch electrode (Rx2) 2 The mesh pattern (TxP) may be placed in the non-emission area (NEA) that does not overlap with the emission area (EA). For example, the first mesh pattern (TxP) of the first touch electrode (Tx2) and the second mesh pattern (TxP) of the second touch electrode (Rx2) may be disposed to overlap in the bank layer, which will be described later. However, the first mesh pattern (TxP) of the first touch electrode (Tx2) and the second mesh pattern (TxP) of the second touch electrode (Rx2) of the present invention are located anywhere in the non-emissive area (NEA) where light is not emitted. can be placed.

Referring to FIG. 4, an electroluminescent display device according to an embodiment of the present invention may include a display panel 10, a data driver, a gate driver, a power supply (PS), and a timing controller (TC).

The display panel 10 includes a display area (DA) that displays information and a non-display area (NDA) that does not display information.

The display area DA is an area where an input image is displayed, and is an area where a pixel array in which a plurality of pixels P is arranged in a matrix type is arranged. The first and second touch electrodes Tx1 to Tx6 and Rx1 to Rx4 shown in FIG. 1 are disposed corresponding to the display area DA of the display panel 10.

The non-display area (NDA) contains the shift registers (SRa, SRb) of the gate driving circuit, various link signal lines (GL1~GLn, DL1~DLm), power supply lines (VDL1, VDL2, VSL1, VSL2), and power supply. This is the area where electrodes (VDLa, VDLb, VSLa, VSLb), etc. are placed. Corresponding to the non-display area (NDA) of the display panel 10, the first and second touch routing lines (TW1 to TW6, RW1 to RW4) and the first and second touch pads (TP1 to TP1) shown in FIG. TP6, RP1~RP4) are deployed.

The pixel array disposed in the display area DA includes a plurality of data lines (D1 to Dm) and a plurality of gate lines (G1 to Gn) arranged to intersect each other, and pixels ( P) includes.

Each pixel (P) includes a light emitting diode (LED), a driving thin film transistor (hereinafter referred to as a driving TFT) (DT) that controls the amount of current flowing through the light emitting diode (LED), and a gate of the driving TFT (DT). It includes a programming unit (SC) for setting the voltage between sources. The pixels (P) of the pixel array are transmitted from the power supply unit (PS) through the first power supply lines (VDL1, VDL2), the first power supply electrodes (VDLa, VDLb), and the first power lines (VD1 to VDm). A first power source (Vdd), which is a high potential voltage, is supplied, and a low potential voltage source is supplied from the power supply unit (PS) through the second power supply lines (VSL1 to VSL2) and the second power supply electrodes (VSLa, VSLb). 2 Receive power (Vss).

The first power lines (VD1 to VDm) are a lower first power supply electrode (VDLa) disposed in the non-display area (NDA) on the side where the chip on film (30) is attached, and the non-display area on the opposite side. The first power supply (Vdd) is supplied from the power supply unit (PS) on both sides through the upper first power supply electrode (VDLb) disposed at (NDA). Both ends of the lower first power supply electrode VDLa and the upper first power supply electrode VDLb may be connected to each other by first power supply lines VDL1 and VDL2. Accordingly, it is possible to minimize the deterioration of display quality due to an increase in RC depending on the positions of pixels arranged in the display area DA. However, the present invention is not limited to this, and in some cases, first power supply lines (VDL1, VDL2) connecting both ends of the lower first power supply electrode (VDLa) and the upper first power supply electrode (VDLb) to each other. Instead of forming it, it can be replaced with only the lower first power supply electrode (VDLa) and the first power lines (VD1 to VDm).

The programming unit SC may include at least one switch TFT and at least one storage capacitor. The switch TFT is turned on in response to a scan signal from the gate line GL, thereby applying the data voltage from the data line DL to one electrode of the storage capacitor. The driving TFT (DT) controls the amount of current supplied to the light emitting diode (LED) according to the level of voltage charged in the storage capacitor, thereby adjusting the amount of light emitted by the light emitting diode (LED). The amount of light emitted from a light emitting diode (LED) is proportional to the amount of current supplied from the driving TFT (DT).

TFTs constituting a pixel may be implemented as a p type or as an n type. Additionally, the semiconductor layer of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or oxide. A light emitting diode (LED) includes an anode electrode, a cathode electrode, and a light emitting structure sandwiched between the anode electrode and the cathode electrode. The anode electrode is connected to the driving TFT (DT). The light emitting structure includes an emission layer (EML), a hole injection layer (HIL) and a hole transport layer (HTL) on one side with the light emitting layer in between, and an electron transport layer (HTL) on the other side. An electron transport layer (ETL) and an electron injection layer (EIL) may each be disposed.

The data driver unit is equipped with a data IC (SD), one side is connected to one end of the source printed circuit board 20, and the other side is a chip-on-film 30 attached to the non-display area (NDA) of the display panel 10. Includes.

The data IC (SD) converts digital video data input from the timing controller (TC) into an analog gamma compensation voltage and generates a data voltage. The data voltage output from the data IC (SD) is supplied to the data lines (D1 to Dm).

The GIP type gate driver is formed in the level shifters (LSa, LSb) mounted on the source printed circuit board 20 and the non-display area (NDA) of the display panel 10, and transmits energy from the level shifters (LSa, LSb). It includes shift registers (SRa, SRb) that receive the supplied signals.

The level shifters (LSa, LSb) receive signals such as the start pulse (ST), gate shift clocks (GLCK), and flicker signal (FLK) from the timing controller (TC), and also receive the gate high voltage (VGH) and gate shift signal (FLK). It receives a driving voltage such as low voltage (VGL). The start pulse (ST), gate shift clocks (GCLK), and flicker signal (FLK) are signals that swing between approximately 0V and 3.3V. Gate shift clocks GLCK1 to n are n-phase clock signals with a predetermined phase difference. The gate high voltage (VGH) is a voltage higher than the threshold voltage of the thin film transistor (TFT) formed in the thin film transistor array of the display panel 10 and is approximately 28V, and the gate low voltage (VGL) is the voltage of the thin film transistor (TFT) of the display panel 10. This is a voltage lower than the threshold voltage of the thin film transistor (TFT) formed in the transistor array and is approximately -5V.

The output signals of the level shifters (LSa, LSb) are transferred to the shift register through lines formed on the chip-on-film 30 on which the data IC (SD) is placed and LOG (Line On Glass) lines formed on the substrate of the display panel 10. It can be supplied to (SRa, SRb). The shift registers SRa and SRb may be formed directly on the non-display area NDA of the display panel 10 through the GIP process.

The shift registers (SRa, SRb) shift the start pulse (VST) input from the level shifters (LSa, LSb) according to the gate shift clock signals (CLK1 to CLKn) between the gate high voltage and the gate low voltage (VGL). Shifts the swinging gate pulse sequentially. Gate pulses output from the shift registers SRa and SRb are sequentially supplied to the gate lines G1a to Gn and G1b to Gn.

The timing controller (TC) receives timing signals such as a vertical synchronization signal, horizontal synchronization signal, data enable signal, and main clock from the host system (not shown) and operates the data IC (SD) and the level shifter of the gate driver ( Synchronize the operation timing of LSa, LSb) and shift registers (SRa, SRb). The data timing control signal for controlling the data IC (SD) may include a source sampling clock (SSC), a source output enable signal (Source Output Enable), etc. The gate timing control signals for controlling the level shifters (LSa, LSb) and shift registers (SRa, SRb) of the gate driver are gate start pulse (GSP), gate shift clock (GSC), and gate start pulse (GSP). It may include an output enable signal (Gate Output Enable, GOE), etc.

In Figure 4, shift registers (SRa, SRb) are arranged on both sides outside the display area (DA) to supply gate pulses to the gate lines (G1a to Gn, G1b to Gn) at both ends of the display area (DA). Although shown, the present invention is not limited to this, and the shift register is disposed only on one side of the display area DA to supply gate pulses to the gate lines G1a to Gn and G1b to Gn from one side of the display area DA. It may be possible. When the shift registers SRa and SRb are disposed on both sides outside the display area DA, gate pulses of the same phase and same amplitude are supplied to the gate lines disposed on the same horizontal line of the pixel array.

In the above description according to the embodiment of the present invention, the case where the gate driver is of the GIP type has been described as an example, but the present invention is not limited to this. For example, the gate driver may be provided as a chip-on-film type and bonded to the non-display area (NDA) of the display panel.

Referring to FIG. 5 , a first buffer layer BUF1 having a single-layer or multi-layer structure may be disposed on the substrate SUB. The substrate (SUB) may be formed of a flexible translucent material. When the substrate (SUB) is formed of a material such as polyimide, the first buffer layer (BUF1) is made of an inorganic material and It can be formed as a single layer composed of any one of organic materials. In contrast, the first buffer layer BUF1 may be formed of multiple layers made of different inorganic materials. Additionally, the first buffer layer BUF1 may be formed as a multi-layer formed of an organic material layer and an inorganic material layer. The inorganic material layer may include either a silicon oxide film (SiOx) or a silicon nitride film (SiNx). Organic materials may include photoacryl.

The semiconductor layer A may be disposed on the first buffer layer BUF1 corresponding to the display area DA. The semiconductor layer (A) may include a source region (SA) and a drain region (DA) spaced apart from each other with a channel region (CA) interposed therebetween. The source area (SA) and drain area (DA) may be conductive areas. The semiconductor layer (A) may be formed using amorphous silicon or polycrystalline silicon obtained by crystallizing amorphous silicon. In contrast, the semiconductor layer (A) may be made of any one of zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), or zinc tin oxide (ZnSnO). Additionally, the semiconductor layer (A) may be made of a low-molecular-weight or high-molecular-weight organic material such as melocyanine, phthalocyanine, pentacene, or thiophene polymer.

A gate insulating film (GI) is disposed on the first buffer layer (BUF1) on which the semiconductor layer (A) is disposed to cover the semiconductor layer (A). The gate insulating film (GI) may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the gate insulating film (GI) may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof.

On the gate insulating film (GI) corresponding to the display area (DA), the gate electrode (GE) of the thin film transistor (TFT) and the gate electrode (GE) are formed so that at least a portion of the area overlaps with the channel layer (CA) of the semiconductor layer (A). A gate line (not shown) connected to may be disposed. The gate electrode (GE) and gate line are any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). , or an alloy thereof, and may be composed of a single layer or multiple layers.

An interlayer insulating layer INT may be disposed on the gate insulating layer GI on which the gate electrode GE and the gate line are disposed to cover them. The interlayer insulating film (INT) may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the interlayer insulating film INT may be formed of a silicon oxide film (SiOx) or a silicon nitride film (SiNx).

A source electrode (SE), a drain electrode (DE), and a data line (not shown) of a thin film transistor (TFT) may be disposed on the interlayer insulating film (INT) corresponding to the display area (DA). The source electrode (SE) and drain electrode (DE) are connected to the source region (SA) and drain region (DA) of the exposed semiconductor layer through contact holes penetrating the gate insulating film (GI) and the interlayer insulating film (INT), respectively. It can be. The source electrode (SE), drain electrode (DE), and data line are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be any one selected from the group consisting of, or an alloy thereof, and may be made of a single layer or multiple layers.

The second touch pad RP1 is disposed on the interlayer insulating layer INT corresponding to the non-display area NDA.

A first passivation film (PAS1) may be disposed to cover the source electrode (SE), the drain electrode (DE), and the data line. The first passivation film (PAS) may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the first passivation film (PAS1) may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof.

Additionally, a planarization layer (PNL) may be disposed on the first passivation layer (PAS1). The planarization film (PNL) is intended to protect the lower structure while alleviating the level difference in the lower structure, and may be formed of an organic material layer. For example, the planarization film (PNL) may be formed of a photo acrylic layer.

An anode electrode (ANO) may be disposed on the planarization film (PNL). The anode electrode (ANO) is connected to the exposed drain electrode (DE) through a contact hole penetrating the planarization film (PNL) and the first passivation film (PAS1). The anode electrode (ANO) may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

A bank layer (BN) having an opening exposing the anode electrode (AN) may be formed on the planarization film (PNL). The opening of the bank layer (BN) may be an area that defines the light emitting area. The bank layer (BN) is made of organic materials such as polyimide, benzocyclobutene series resin, and polyacrylate. A spacer (SPC) may be formed on the bank layer (BN). The spacer (SPC) serves to prevent a mask for subsequent manufacturing of the light emitting laminate (LES) from contacting the laminate below the spacer (SPC). The spacer (SPC) is manufactured simultaneously with the bank layer (BN) using a half-tone mask when manufacturing the bank layer (BN). Accordingly, the spacer (SPC) may be made of the same material as the bank layer (BN) and is formed as one body with the bank layer (BN).

A light-emitting laminate (LES) and a cathode electrode (CAT) are sequentially disposed on the anode electrode (ANO) exposed through the light-emitting area of the bank layer (BN) to form a light-emitting device (LED). The light emitting stack (LES) may include a hole-related layer, a light-emitting layer, and an electron-related layer. The cathode electrode (CAT) may be made of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof with a low work function. In the present invention, it has been explained that the light emitting laminate (LES) is disposed on the anode electrode (ANO), and the cathode electrode (CAT) is disposed on the light emitting laminate (LES). However, the light emitting laminate is placed on the cathode electrode (CAT). Water (LES) may be disposed, and an anode electrode (ANO) may be disposed on the light emitting laminate (LES).

A second passivation film (PAS2) may be disposed on the cathode electrode (CAT). The second passivation film PAS2 may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the second passivation film (PAS2) may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof. The second passivation film PAS2 may be disposed in the display area DA and the non-display area NDA.

An encapsulation film (ENC) may be disposed on the second passivation film (PAS2) to cover the cathode electrode (CAT) and the bank layer (BN). The encapsulation film (ENC) is intended to prevent external moisture or oxygen from penetrating into the light emitting laminate (LES) located inside the encapsulation film (ENC). It is formed as a single layer of an organic material layer or an inorganic material layer, or It can be formed into a multi-layer structure in which inorganic and organic layers are alternately arranged. The present invention discloses an encapsulation film (ENC) formed as a single layer of an organic material layer.

The encapsulation film (ENC) may be disposed in the display area (DA) and the non-display area (NDA). Specifically, the encapsulation film (ENC) may be disposed throughout the display area (DA). As will be described later, the encapsulation film (ENC) can be placed continuously up to the dam (DAM).

A third passivation film (PAS3) is disposed on the encapsulation film (ENC) to prevent moisture or oxygen from penetrating into the encapsulation film (ENC). The third passivation film (PAS3) may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the third passivation film (PAS3) may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof. The third passivation film (PAS3) may be formed of the same material as the above-described second passivation film (PAS2), but is not limited thereto. The third passivation film PAS2 may be disposed in the display area DA and the non-display area NDA.

A second buffer layer (BUF2) is disposed on the third passivation film (PAS3), and can prevent moisture or oxygen from penetrating into the underlying device along with the third passivation film (PAS3). The second buffer layer (BUF2) may be formed as a single layer made of an inorganic material or as a multiple layer made of different inorganic materials. For example, the second buffer layer BUF2 may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof. The second buffer layer BUF2 may be made of the same material as the third passivation layer PAS3 described above, but is not limited thereto. The second buffer layer BUF2 may be disposed in the display area DA and the non-display area NDA in the same manner as the third passivation layer PAS3.

As shown in FIG. 1, on the second buffer layer (BUF2), first and second touch electrodes (Tx1 to Tx6, Rx1 to Rx4) and first and second touch routing lines (TW1 to TW6, RW1 to RW4) This can be placed.

Specifically, a bridge electrode (RCO) connecting the first touch electrode (Rx1) is disposed on the second buffer layer (BUF2), and an insulating layer (INS) is placed on the bridge electrode (RCO) to insulate the bridge electrode (RCO). This is placed. The insulating layer (INS) may be disposed in the display area (DA) and the non-display area (NDA). The first touch electrodes (Rx1) are disposed on the insulating layer (INS) to be spaced apart from each other with the second touch electrodes (Tx6) in between, and the first touch electrodes (Rx1) are connected through the bridge electrode (RCO). A second touch routing line (RW1) is connected to one side of the first touch electrode (Rx1), and the second touch routing line (RW1) extends to the non-display area (NDA) and is connected to the second touch pad (RP1). do.

A fourth passivation film (PAS4) is disposed on the first and second touch electrodes (Tx1 to Tx6 and Rx1 to Rx4) to protect the lower touch elements from external moisture, oxygen or impact.

A dam (DAM) may be placed on the non-display area (NDA). When manufacturing the encapsulation film (ENC) of a display device, the dam (DAM) can prevent overflow so that the material of the encapsulation film (ENC) is confined inside the dam (DAM). The dam (DAM) may be arranged to completely surround the display area (DA) and may have a closed loop shape when viewed from a plan view. As shown, the dam (DAM) may have a structure in which a planarization film (PNL) forming material, a bank layer (BN) forming material, and a spacer (SPC) forming material are sequentially stacked, but is not limited thereto.

<First embodiment>

Figure 6 is a plan view showing a display device according to the present invention. 7 to 10 are diagrams showing the inspection area formation process and scribing process in time series according to the first embodiment of the present invention. 7 to 9 (a) is an enlarged plan view of the region R1 in FIG. 6, and (b) is a cross-sectional view of (a) taken along the line II-II'.

Referring to FIG. 6, the display device according to the first embodiment of the present invention includes a touch pad (RP), a touch inspection pad (IRP), and a link line connecting the touch pad (RP) and the touch inspection pad (IRP). LL).

The touch pad RP is disposed in the first area A1 of the substrate SUB. The touch inspection pad (IRP) is disposed in the second area (A2) of the substrate (SUB). The first area A1 of the substrate SUB refers to an area to be allocated as the non-display area NDA in the final completed display panel. The second area A2 of the substrate SUB is a remaining area provided outside the area to be allocated as a non-display area in the final completed display panel, and refers to an area to be removed by a future scribing process. Accordingly, the second area A2 of the substrate SUB is deleted and does not remain in the final completed display panel. To connect the touch pad RP and the touch test pad IRP, a portion of the link line LL is disposed on the first area A1 of the substrate SUB, and the other portion is disposed on the first area A1 of the substrate SUB. 2 It is placed on area A2.

After the inspection process, the touch inspection pad (IRP) and a portion of the link line (LL) disposed in the second area (A2) of the substrate (SUB) are cut along the scribing line through a scribing process and separated. do. Accordingly, in the final display panel, only the touch pad RP and a portion of the link line LL remain, and one end of the link line LL remains separated and not connected to any other electrode or signal line.

In the first embodiment of the present invention, since the touch inspection pads (IRPs) are removed after the inspection process, there is no need to separately allocate an area for forming the touch inspection pads (IRPs) on the non-display area of the substrate (SUB). . Accordingly, the first embodiment of the present invention has the advantage of significantly reducing the bezel area. Additionally, by deleting the touch inspection pads (IRPs) from the non-display area of the substrate (SUB), a predetermined space is secured, which has the advantage of improving design freedom.

More specifically, referring to FIG. 7 along with FIG. 5 , a scribing area (SCA) is defined on the substrate (SUB). The scribing line is set within the scribing area (SCA).

A link line LL is disposed on the substrate SUB. The link line LL is disposed on the first buffer layer BUF1 and the gate insulating layer GI. The link line (LL) is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or It may be an alloy of and may be composed of a single layer or multiple layers. The link line LL may be formed of the same material as the gate electrode GE of the thin film transistor TFT, but is not limited thereto.

An interlayer insulating film (INT) is disposed on the link line (LL). The interlayer insulating layer INT includes a first open hole OH1 exposing the link line LL of the scribing area SCA. In the first embodiment of the present invention, the interlayer insulating film (INT) of the scribing area (SCA) is removed in advance before scribing, so that foreign matter dispersed as the interlayer insulating film (INT) is cut during the scribing process is prevented. , it is possible to prevent problems of contact defects occurring during the bonding process of the touch pad RP and a connection member (eg, chip on film) for transmitting signals to the touch pad RP.

Although not shown, the substrate SUB may be exposed by the first open hole OH1 in an area of the scribing area SCA where the link line LL is not disposed. That is, in the corresponding area, the first open hole OH may be formed to penetrate the interlayer insulating layer INT, the gate insulating layer GI, and the first buffer layer BUF to expose the substrate SUB.

A touch pad (RP) and a touch test pad (IRP) are disposed on the interlayer insulating film (INT). The touch pad (RP) and touch inspection pad (IRP) are arranged to be spaced apart from each other on both sides with a scribing line in between. The touch pad RP is disposed on the first area A1 of the substrate SUB, and the touch inspection pad IRP is disposed on the second area A2 of the substrate SUB.

The touch pad (RP) and touch inspection pad (IRP) are a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be any one selected from, or an alloy thereof, and may be made of a single layer or multiple layers. The touch pad (RP) and the touch test pad (IRP) may be formed of the same material as the source electrode (SE) and drain electrode (DE) of the thin film transistor (TFT), but are not limited thereto. The touch pad (RP) and the touch inspection pad (IRP) may be formed of different materials and may have different stacked structures.

The touch pad RP is connected to the link line LL through the first contact hole CH1 penetrating the interlayer insulating film INT. The touch test pad (IRP) is connected to the link line (LL) through the second contact hole (CH2) penetrating the interlayer insulating film (INT). Accordingly, the touch pad (RP) and the touch test pad (IRP) are electrically connected through the link line (LL).

Referring further to FIG. 8, a planarization film (PNL) is disposed on the touch pad (RP) and the touch inspection pad (IRP). The planarization film (PNL) is arranged to cover the touch pad (RP) and the touch inspection pad (IRP), and functions to protect the touch pad (RP) and the touch inspection pad (IRP).

The planarization film (PNL) includes a second open hole (OH2) exposing the link line (LL) of the scribing area (SCA). The second open hole OH2 may be formed to expose the first open hole OH1, but is not limited thereto, and may be sufficient to expose the scribing line. Since the planarization film (PNL) is formed to have a predetermined thickness to perform its function, if the planarization film (PNL) remains in the scribing area (SCA), the scribing process may not be easy. In the first embodiment of the present invention, cutting through a scribing process can be easily performed by removing the planarization film (PNL) of the scribing area (SCA) in advance.

Referring further to FIG. 9, an upper touch inspection pad (UIRP) is disposed on the planarization film (PNL). The upper touch inspection pad (UIRP) is connected to the touch inspection pad (IRP) through the third contact hole (CH3) penetrating the planarization film (PNL). The upper touch inspection pad (UIRP) may be a part that an inspection pin (not shown) directly contacts to detect defects in the touch device (TD). The upper touch inspection pad (UIRP) may be formed of the same material as the touch electrodes (Tx, Rx) and/or the touch routing lines (TW, RW). Through the series of processes described above, an inspection area can be formed. Afterwards, the display panel can be provided on a cell basis through a scribing process.

Referring further to FIG. 10, after the inspection process to determine whether the touch device TD is operating normally, a scribing process is performed. That is, as the substrate SUB is cut along a preset scribing line, the display panel is separated into cells. Afterwards, only a portion of the touch pad RP and link line LL remain on the substrate SUB. One end of the remaining link line LL may be disposed to correspond to one end of the cut substrate SUB. The remaining touch pad RP may be disposed to be spaced inwardly at a predetermined distance from one end of the substrate SUB and may be connected to the other end of the link line LL extending from one end of the substrate SUB.

Referring again to FIGS. 7 and 8, the scribing process can be facilitated by forming the first open hole (OH1) and the second open hole (OH2) before the scribing process, but the first open hole (OH1) and the second open hole (OH2) can be formed in advance. Due to the etching process to form (OH1) and the second open hole (OH2), damage may occur to the link line (LL), causing a problem in which signals are not transmitted smoothly during the touch inspection process. .

To prevent this, a first open hole (OH1) and a second open hole (OH2) are formed to expose the scribing line, but the interlayer insulating film (INT) is left only in the area where the link line (LL) is disposed. You can consider this method. However, in this case, as described above, a contact defect may occur between the touch pad RP and the connection member due to foreign matter dispersed when the interlayer insulating film INT is cut, which is a problem.

<Second Embodiment>

11 to 14 are diagrams showing the inspection area formation process and scribing process in time series according to the second embodiment of the present invention. 11 to 13 (a) is an enlarged plan view of the region R1 in FIG. 6, and (b) is a cross-sectional view of (a) taken along line III-III'.

Referring to FIG. 6, the display device according to the second embodiment of the present invention includes a touch pad (RP), a touch inspection pad (IRP), and a link line connecting the touch pad (RP) and the touch inspection pad (IRP). LL).

The touch pad RP is disposed in the first area A1 of the substrate SUB. The touch inspection pad (IRP) is disposed in the second area (A2) of the substrate (SUB). The first area A1 of the substrate SUB refers to an area to be allocated as a non-display area in the final completed display panel. The second area A2 of the substrate SUB is a remaining area provided outside the area to be allocated as a non-display area in the final completed display panel, and refers to an area to be removed by a future scribing process. Accordingly, the second area A2 of the substrate SUB is deleted and does not remain in the final completed display panel. To connect the touch pad RP and the touch test pad IRP, a portion of the link line LL is disposed on the first area A1 of the substrate SUB, and the other portion is disposed on the first area A1 of the substrate SUB. 2 It is placed on area A2.

After the inspection process, the touch inspection pad (IRP) and a portion of the link line (LL) disposed in the second area (A2) of the substrate (SUB) are cut along the scribing line through a scribing process and separated. do. Accordingly, in the final display panel, only the touch pad RP and a portion of the link line LL remain, and one end of the link line LL remains separated and not connected to any other electrode or signal line.

In the second embodiment of the present invention, since the touch inspection pads (IRPs) are removed after the inspection process, there is no need to separately allocate an area for forming the touch inspection pads (IRPs) on the non-display area of the substrate (SUB). . Accordingly, the second embodiment of the present invention has the advantage of significantly reducing the bezel area. Additionally, by deleting the touch inspection pads (IRPs) from the non-display area of the substrate (SUB), a predetermined space is secured, which has the advantage of improving design freedom.

More specifically, referring further to FIG. 11 along with FIG. 5 , a scribing area (SCA) is defined on the substrate (SUB). The scribing line is set within the scribing area (SCA).

A first buffer layer (BUF1), a gate insulating layer (GI), and an interlayer insulating layer (INT) are sequentially disposed on the substrate SUB. The first buffer layer BUF1, the gate insulating layer GI, and the interlayer insulating layer INT include a first open hole OH1 that opens the scribing area SCA. The first open hole OH1 may penetrate the first buffer layer BUF1, the gate insulating layer GI, and the interlayer insulating layer INT in the scribing area SCA to expose the substrate SUB. Although not shown, the first open hole OH1 may be formed to open at least one of the first buffer layer BUF1, the gate insulating layer GI, and the interlayer insulating layer INT in the scribing area SCA. there is.

The second embodiment of the present invention removes inorganic layers such as the first buffer layer (BUF1), gate insulating layer (GI), and interlayer insulating layer (INT) of the scribing area (SCA) before scribing, thereby scribing. It is possible to prevent contact defects occurring during the bonding process of the touch pad RP and the connection member for transmitting signals to the touch pad RP due to foreign substances dispersed as the inorganic films are cut during the ice process.

A touch pad (RP) and a touch test pad (IRP) are disposed on the interlayer insulating film (INT). The touch pad (RP) and touch inspection pad (IRP) are arranged to be spaced apart from each other on both sides with a scribing line in between. The touch pad RP is disposed on the first area A1 of the substrate SUB, and the touch inspection pad IRP is disposed on the second area A2 of the substrate SUB. The touch pad (RP) and touch inspection pad (IRP) are a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be any one selected from, or an alloy thereof, and may be made of a single layer or multiple layers. The touch pad (RP) and the touch test pad (IRP) may be formed of the same material as the source electrode (SE) and drain electrode (DE) of the thin film transistor (TFT), but are not limited thereto. For example, the touch pad (RP) and the touch test pad (IRP) may be formed of the same material as the gate electrode (GE) of the thin film transistor (TFT). As another example, the touch pad (RP) and the touch test pad (IRP) include a first layer formed of the same material as the gate electrode (GE), and a first layer formed of the same material as the source electrode (SE) and the drain electrode (DE). It may have a two-layer laminated structure. In this case, the first layer and the second layer may be electrically connected through a via hole penetrating the insulating layer interposed therebetween. Additionally, the touch pad (RP) and the touch inspection pad (IRP) may be formed of different materials and may have different stacked structures.

Referring further to FIG. 12, a planarization film (PNL) is disposed on the touch pad (RP) and the touch inspection pad (IRP). The planarization film (PNL) is arranged to cover at least a portion of the touch pad (RP) and the touch inspection pad (IRP), and functions to protect the touch pad (RP) and the touch inspection pad (IRP).

The planarization film (PNL) includes a first open hole (OH1) that opens the scribing area (SCA). The second open hole (OH2) may be formed to expose the first open hole (OH1), but is not limited thereto. When the first open hole OH1 exposes the substrate SUB, the second open hole OH2 may be formed to expose the substrate SUB. Since the planarization film (PNL) is formed to have a predetermined thickness to perform its function, if the planarization film (PNL) remains in the scribing area (SCA), the scribing process may not be easy. In the second embodiment of the present invention, cutting through a scribing process can be easily performed by removing the planarization film (PNL) of the scribing area (SCA) in advance.

A first contact hole (CH1), a second contact hole (CH2), and a third contact hole (CH3) are formed in the planarization film (PNL). The first contact hole CH1 exposes at least a portion of the touch pad RP. The second contact hole (CH2) and the third contact hole (CH3) each expose at least a portion of the touch inspection pad (IRP). The second contact hole (CH2) is disposed closer to the first contact hole (CH1) than the third contact hole (CH2).

Referring further to FIG. 13, a link line LL is disposed on the planarization film PNL. The link line (LL) is made of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), and transparent materials such as ITO, IZO, etc. It may be any one selected from the group consisting of conductive materials, or an alloy thereof, and may be made of a single layer or multiple layers. For example, the link line LL may be formed of the same material as the touch electrodes Tx and Rx and/or the touch routing lines TW and RW, but is not limited thereto. That is, the link line LL may include at least one of the touch electrodes Tx and Rx and/or the touch routing lines TW and RW.

One end of the link line LL is connected to the touch pad RP through the first contact hole CH1 penetrating the planarization film PNL. The other end of the link line (LL) is connected to the touch inspection pad (IRP) through the second contact hole (CH2) penetrating the planarization film (PNL). Accordingly, the touch pad (RP) and the touch test pad (IRP) are electrically connected through the link line (LL). The link line LL may be in direct contact with the substrate SUB within the second open hole OH2 and the first open hole OH1.

On the planarization film (PNL), an upper touch inspection pad (UIRP) is disposed. The upper touch inspection pad (UIRP) is connected to the touch inspection pad (IRP) through the third contact hole (CH3) penetrating the planarization film (PNL). The upper touch inspection pad (UIRP) may be a part that an inspection pin (not shown) directly contacts to detect defects in the touch device (TD). The upper touch inspection pad (UIRP) may be formed of the same material as the touch electrodes (Tx, Rx) and/or the touch routing lines (TW, RW). That is, the link line LL may include at least one of the touch electrodes Tx and Rx and/or the touch routing lines TW and RW.

Although not shown, the upper touch inspection pad (UIRP) may be a part extending from the link line (LL). That is, the upper touch inspection pad (UIRP) may be a part branched from the link line (LL) and is electrically connected to the touch inspection pad (IRP) through the second contact hole (CH2) penetrating the planarization film (PNL). can be connected In this case, the third contact hole CH3 may be omitted. Through the series of processes described above, an inspection area may be formed. Afterwards, the display panel can be provided on a cell basis through a scribing process.

Referring further to FIG. 14, after the inspection process to determine whether the touch device TD is operating normally, a scribing process is performed. That is, as the substrate SUB is cut along a preset scribing line, the display panel is separated into cells. Afterwards, only a portion of the touch pad RP and link line LL remain on the substrate SUB. One end of the remaining link line LL may be disposed to correspond to one end of the cut substrate SUB. The remaining touch pad RP may be disposed to be spaced inwardly at a predetermined distance from one end of the substrate SUB and may be connected to the other end of the link line LL extending from one end of the substrate SUB.

In the second embodiment of the present invention, unlike the first embodiment, the link line LL is formed on the top layer before the scribing process, thereby preventing damage from exposure to the etching process environment. Furthermore, since the inorganic and/or organic films in the scribing area can be removed in advance before forming the link line (LL), not only can the generation and dispersion of foreign substances during the scribing process be minimized, but also the film thickness can be reduced. It has the advantage of minimizing cutting defects caused by cutting.

<Third Embodiment>

Figure 15 is a plan view schematically showing a display device according to a third embodiment of the present invention. Figure 16 is a cross-sectional view of Figure 15 taken along line III-III'. The third embodiment is a modification of the first embodiment, and description of substantially the same configuration as the first embodiment will be omitted.

Referring to FIG. 15, the display device according to the third embodiment of the present invention includes a touch pad (RP), a touch inspection pad (IRP), and a touch routing line (TW, RW) connecting the touch inspection pad (IRP). Includes link line (LL). That is, the link line LL of the present invention may be configured so that one end and the other end are connected to the touch pad RP and the touch test pad (IRP), respectively, as in the first embodiment, and the third embodiment As shown, one end and the other end may be configured to be connected to the touch routing lines (TW, RW) and the touch test pad (IRP), respectively.

The touch routing lines (TW, RW) and the link line (LL) may be placed on different layers. Accordingly, the touch routing lines (TW, RW) and the link line (LL) may be electrically connected through the auxiliary contact hole (AH) penetrating the insulating films interposed between them.

Referring to FIG. 16, the link line LL may be disposed on the gate insulating layer GI. The link line (LL) is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or It may be an alloy of and may be composed of a single layer or multiple layers. The link line LL may be formed of the same material as the gate electrode GE of the thin film transistor TFT, but is not limited thereto.

The touch routing line TW5 is disposed on the link line LL with at least one insulating film interposed therebetween. For example, an interlayer insulating layer INT, a second buffer layer BUF2, and an insulating layer INS may be interposed between the touch routing line TW5 and the link line LL. In this case, one end of the touch routing line (TW5) and the link line (LL) may be connected through an auxiliary contact hole (AH) penetrating the interlayer insulating film (INT), the second buffer layer (BUF2), and the insulating layer (INS). .

<Example 4>

Figure 17 is a plan view schematically showing a display device according to a fourth embodiment of the present invention. Figure 18 is a cross-sectional view taken along line IV-IV' of Figure 17. Figure 19 is a cross-sectional view taken along line V-V' of Figure 17. The fourth embodiment is a modification of the second embodiment, and description of substantially the same configuration as the second embodiment will be omitted.

Referring to FIG. 17, the display device according to the fourth embodiment of the present invention includes a touch pad (RP), a touch inspection pad (IRP), and a touch routing line (TW1, RW) connecting the touch inspection pad (IRP). Includes link line (LL). That is, the link line LL of the present invention may be configured so that one end and the other end are connected to the touch pad RP and the touch test pad IRP, respectively, as in the second embodiment, and the fourth embodiment As shown, one end and the other end may be configured to be connected to the touch routing lines (TW, RW) and the touch test pad (IRP), respectively.

The touch routing lines (TW, RW) and the link line (LL) may be arranged on the same layer. Accordingly, the link line LL may be a part branched from the touch routing lines TW and RW. For example, further referring to FIG. 18 , the fifth link line LL may be a part branched from the fifth touch routing line TW5.

One link line (LL) to which different signals are applied and one touch routing line (TW, RW) may be intersected in one area. For example, the first link line LL1 connected to the first touch routing line TW1, and the third and fifth touch routing lines TW3 and TW5 are lines to which different signals are applied and cross each other. can be placed. In this case, in order to prevent the first link line LL1 and the third and fifth touch routing lines TW3 and TW5 from being short-circuited, the first link line LL1 is connected to the third and fifth touch routing lines ( It may be connected to the first touch routing line (TW1) through a jumping line (JL) that bypasses TW3 and TW5).

More specifically, referring to FIG. 19 , the jumping line JL may be disposed on the gate insulating layer GI. The jumping line (JL) is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or It may be an alloy of and may be composed of a single layer or multiple layers. The jumping line JL may be formed of the same material as the gate electrode GE of the thin film transistor (TFT), but is not limited thereto. As another example, the jumping line JL may be disposed on the interlayer insulating layer INT and may be formed of the same material as the source/drain electrodes SE and DE of the thin film transistor TFT.

The first, third, and fifth touch routing lines (TW1, TW3, TW5) and the first link line (LL1) are disposed on the jumping line (JL) with at least one insulating film therebetween. For example, between the first, third, and fifth touch routing lines (TW1, TW3, TW5), the first link line (LL1), and the jumping line (JL), an interlayer insulating film (INT) and a second buffer layer ( BUF2), an insulating layer (INS) may be interposed. In this case, one end of the first touch routing line (TW1) and the jumping line (JL) is a first auxiliary contact hole (AH1) penetrating the interlayer insulating layer (INT), the second buffer layer (BUF2), and the insulating layer (INS). It can be connected through . The first link line LL1 and one end of the jumping line JL may be connected through a second auxiliary contact hole AH2 penetrating the interlayer insulating layer INT, the second buffer layer BUF2, and the insulating layer INS. there is. That is, the first touch routing line TW1 and the first link line LL1 may be electrically connected through a jumping line JL that crosses the third and fifth touch routing lines TW3 and TW5.

Through the above-described content, those skilled in the art will be able to make various changes and modifications without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be determined by the scope of the patent claims.

10: Display panel TD: Touch element
DA: Display area NDA: Non-display area
Tx: first touch electrode Rx: second touch electrode
TW: 1st touch routing line RW: 2nd touch routing line
TP: 1st touch pad RP: 2nd touch pad
LL: Link Line IRP: Touch Inspection Pad

Claims (26)

A substrate including a display area where pixels are arranged, and a non-display area outside the display area;
a touch electrode disposed on the display area;
a touch pad disposed on the non-display area;
a touch routing line disposed on the non-display area and electrically connecting the touch electrode and the touch pad;
a link line disposed on the non-display area, connected to the touch pad, and extending from the touch pad to one end of the substrate; and
Comprising a first buffer layer on the substrate,
At least a portion of the link line is in contact with a side surface of the first buffer layer.
According to claim 1,
The link line and the touch pad are,
A display device disposed in different layers with at least one planarization film interposed therebetween and connected to each other through a contact hole penetrating the planarization film.
delete delete delete According to claim 1,
One end of the link line is,
A display device corresponding to one end of the substrate.
delete According to claim 1,
The link line is,
disposed on the same layer as the gate electrode of the display area,
The touch pad is,
disposed on the same layer as the source electrode and drain electrode of the display area,
The link line and the touch pad are,
A display device connected through a first contact hole penetrating a planarization film disposed between the link line and the touch pad.
delete In clause 8
The link line is,
A display device comprising the same material as a forming material of the touch electrode or the touch routing line.
According to claim 1,
further comprising an encapsulation film that covers at least the pixels of the display area,
The touch electrode is,
A display device disposed on the encapsulation film.
According to claim 1,
The pixel is,
Comprising a transistor and a light-emitting element electrically connected to the transistor,
The transistor is,
a semiconductor layer disposed on the substrate;
a gate insulating film disposed on the semiconductor layer;
a gate electrode disposed on the gate insulating film and overlapping at least a portion of the semiconductor layer;
an interlayer insulating film disposed on the gate electrode;
a source electrode and a drain electrode disposed on the interlayer insulating film and connected to one side and the other side of the semiconductor layer, respectively, through contact holes penetrating the interlayer insulating film; and
A display device comprising a planarization film disposed on the source electrode and the drain electrode.
delete delete delete According to claim 12,
The touch pad is,
disposed on the same layer as the source electrode and the drain electrode,
The link line is,
It is disposed on the planarization film,
The link line and the touch pad are,
A display device connected through a first contact hole penetrating the planarization film.
According to claim 16,
At one end of the substrate, the display device further includes a first open hole penetrating through at least one of the gate insulating layer and the interlayer insulating layer.
According to claim 17,
The first open hole is,
A display device exposing the substrate.
According to claim 16,
The display device further includes a second open hole penetrating the planarization film at one end of the substrate.
A substrate including a display area where pixels are arranged, and a non-display area outside the display area;
a touch electrode disposed on the display area;
a touch pad disposed on the non-display area;
a touch routing line disposed on the non-display area and electrically connecting the touch electrode and the touch pad; and
A display device comprising a link line disposed on the non-display area, connected to the touch routing line, and extending from the touch routing line to one end of the substrate.
According to claim 20,
The link line and the touch routing line are,
A display device disposed in different layers with at least one insulating film interposed therebetween, and interconnected through an auxiliary contact hole penetrating the insulating film.
According to claim 20,
The link line is,
A display device that is a part branched from the touch routing line.
According to claim 20,
The link line and the touch routing line are placed on the same floor,
A display device electrically connected to the link line and the touch routing line through a jumping line disposed on a different layer with at least one insulating film interposed therebetween.
According to claim 20,
One end of the link line is,
A display device corresponding to one end of the substrate.

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