KR102596604B1 - Drive ic and display device using the same - Google Patents

Abstract

According to this embodiment, a level shifter that receives a plurality of gate control signals and outputs a plurality of gate driving signals so that the number of the plurality of gate driving signals is greater than the plurality of gate control signals, and a plurality of data control signals The aim is to provide a drive IC including a source drive IC that receives data signals and outputs them, and a display device using the same.
According to the present embodiments, a display device that can be implemented with a thinner thickness and has a lower manufacturing cost can be provided.

Description

Drive IC and display device using the same {DRIVE IC AND DISPLAY DEVICE USING THE SAME}

These embodiments relate to a drive IC and a display device using the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), organic Various matrix-type display devices, such as organic light emitting display devices (OLED), are being used.

Recently, display devices are being made thinner to enhance aesthetics. Therefore, there is a need to reduce the size of the PCB and make the display device thinner. Also, if you reduce the PCB,

In addition, display devices use PCBs to transmit signals to each element, and if the PCB area is small, manufacturing costs can be reduced, so there is a need to reduce the size of the PCB.

Additionally, in a matrix type display device, a gate signal is transmitted for each gate line. The gate signal and signals for generating the gate signal are transmitted in the form of pulses, which may appear as noise. Therefore, there is a need to suppress noise generation.

The purpose of these embodiments is to provide a thin and light display device.

Another purpose of the present embodiments is to provide a drive IC that is less affected by noise and a display device using the same.

In one aspect, the present embodiments include a level shifter that receives a plurality of gate control signals and outputs a plurality of gate driving signals so that the number of the plurality of gate driving signals is greater than the plurality of gate control signals; And a drive IC including a source drive IC that receives a plurality of data control signals and outputs data signals, and a display device using the same can be provided.

In another aspect, the present embodiments include a display panel in which pixels are formed in an area where a plurality of gate lines and a plurality of data lines intersect, a control unit that outputs a plurality of gate control signals to control the driving of the display panel, and a plurality of devices. A first group of drive ICs including a first drive IC that receives a gate control signal and outputs a first gate drive signal corresponding to an odd-numbered gate line among a plurality of gate lines, a plurality of drive ICs that receive a plurality of gate control signals A second group of drive ICs including a second drive IC that outputs a second gate driving signal corresponding to the even-numbered gate line among the gate lines, a first circuit connecting the control unit and the first group of drive ICs, and a control unit and a first group of drive ICs. It includes a second circuit unit connecting two groups of drive ICs, and the first drive IC and the second drive IC provide a display device including a level shifter and a source drive IC, respectively.

According to the present embodiments, a display device that can be implemented with a thinner thickness and has a lower manufacturing cost can be provided.

Additionally, according to the present embodiments, a drive IC that can reduce the influence of noise and a display device using the same can be provided.

1 is a structural diagram showing an example of a display device according to this embodiment.
Figure 2 is a structural diagram showing another embodiment of the display device according to this embodiment.
FIG. 3A is a diagram illustrating an embodiment of the first drive IC used in the display device shown in FIG. 2.
FIG. 3B is a diagram showing an embodiment of the second drive IC used in the display device shown in FIG. 2.
FIG. 3C is a diagram showing an embodiment of a third drive IC used in the display device shown in FIG. 2.
FIG. 4A is a structural diagram showing an embodiment of the first level shifter shown in FIG. 3A.
FIG. 4B is a structural diagram showing an embodiment of the second level shifter shown in FIG. 3B.
FIG. 5A is a conceptual diagram showing a method for determining that the level shifter shown in FIG. 4A operates in the first mode.
FIG. 5B is a conceptual diagram showing a method for determining that the level shifter shown in FIG. 4B operates in the second mode.
FIG. 6 is a conceptual diagram showing an embodiment of the first PCB shown in FIG. 2.
FIG. 7 is a conceptual diagram showing another embodiment of the first drive IC shown in FIG. 2.
FIG. 8 is a conceptual diagram showing another embodiment of the first PCB shown in FIG. 2.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

1 is a structural diagram showing an example of a display device according to this embodiment.

Referring to FIG. 1 , the display device 100 may include a display panel 110, a data driver 120, a gate driver 130, and a control unit 140.

The display panel 110 has pixels 111 in the area where a plurality of gate lines (G1, G2,..., Gn-1, Gn) and a plurality of data lines (D1, D2,..., Dm-1, Dm) intersect. ) can be formed. A plurality of pixels 111 are transmitted to data lines (D1, D2,..., Dm-1, Dm) in response to gate signals sequentially transmitted to gate lines (G1, G2,..., Gn-1, Gn). Light can be emitted in response to data signals. Here, the display panel 110 may be a liquid crystal display device, a plasma display device, or an organic light emitting display device. However, it is not limited to this.

The data driver 120 is connected to a plurality of data lines (D1, D2,...,Dm-1, Dm) and can transmit a data signal to the data line 120. The data driver 120 can receive a digital image signal from the control unit 240, convert the digital image signal into a data signal, and transmit it to a plurality of data lines (D1, D2,..., Dm-1, Dm). The data driver 120 may receive a plurality of data control signals from the control unit 140. The data control signal may be a start pulse, clock signal, horizontal synchronization signal, or vertical synchronization signal. However, it is not limited to this. The data driver 120 may be referred to as a source driver IC.

The gate driver 130 is connected to a plurality of gate lines (G1, G2,..., Gn-1, Gn) and can sequentially transmit gate signals to the gate lines (G1, G2,..., Gn-1, Gn). . However, it is not limited to this. The gate driver 130 may receive a plurality of gate control signals from the control unit 140. The gate driver 130 may output a plurality of gate driving signals by changing a plurality of gate control signals. The number of the plurality of gate driving signals is greater than the number of the plurality of gate control signals, so the number of wires transmitting the gate control signal from the control unit 140 to the gate driver 130 is larger than the number of the plurality of gate driving signals. You can reduce it more than you can.

Additionally, the gate driver 130 may include a level shifter 131 and a gate circuit 132. The level shifter 131 can change the plurality of gate control signals received from the control unit 140 and output a plurality of gate driving signals.

The plurality of gate control signals received by the level shifter 131 are even/odd (E/O) clock, gate start pulse (GST), gate shift clock (GCLK), modulation timing shift clock (MCLK), and power supply voltage ( VCC) may be included. Additionally, the level shifter 131 can receive a plurality of gate control signals and output a plurality of gate drive signals. The plurality of gate driving signals may include first to tenth clocks, an even gate high voltage (VGH_E), an odd gate high voltage (VGH_O), a start pulse (VST), and a reset signal. However, it is not limited to this. Additionally, the number of gate driving signals may be greater than the number of gate control signals. As a result, the number of wires transmitting signals from the control unit 140 to the gate driver 130 can be reduced. By reducing the number of wires, the space occupied by the wires can be reduced, which can be advantageous for lightening and thinning.

The gate circuit 132 generates a gate signal and is connected to a plurality of gate lines (G1, G2,..., Gn-1, Gn) to send a gate signal to the gate lines (G1, G2,..., Gn-1, Gn). can be transmitted. The gate circuit 132 may receive a plurality of gate driving signals from the level shifter 131 and generate a gate signal.

The control unit 140 may transmit a data control signal and a gate control signal to the data driver 120 and the gate driver 130. Additionally, the control unit 140 may transmit a digital image signal to the data driver 120.

Figure 2 is a structural diagram showing another embodiment of a display device according to this embodiment.

Referring to FIG. 2, the display device 200 includes a display panel 210, a plurality of drive ICs (221a, 222a, 223a, 221b, 222b, 223b), a control unit 240, and a plurality of drive ICs (221a, 222a, It may include a first PCB (212a) and a second PCB (212b) connecting 223a, 221b, 222b, 223b) and the control unit 240.

The display panel 210 has a plurality of pixels formed in an area created by the intersection of a gate line (GL) and a data line (DL), and includes an active area (210a) that displays an image and an inactive area (210a) that does not display an image. 211a, 211b) may be included. A plurality of GIP (Gate In Panel) circuits (2111a, 2111b) may be disposed in the non-active areas (211a, 211b). However, it is not limited to this. Here, the inactive areas 211a and 211b are shown as being formed on the left and right sides of the active area 210a, but are not limited thereto and may be placed on either the left or right side of the display panel 210. .

The plurality of GIP circuits 2111a and 2111b are each connected to the gate line GL and can transmit a gate signal to the gate line GL. Among the plurality of GIP circuits 2111a and 2111b, the GIP circuits 2111a and 2111b arranged on the left side of the display panel 210 are respectively connected to the odd gate line GL among the plurality of gate lines GL and are connected to the display panel 2111b. The GIP circuit 2111a disposed on the right side of 210 may be connected to each even-numbered gate line GL. However, it is not limited to this. In addition, the plurality of GIP circuits (2111a, 2111b) receive a plurality of gate driving signals from the drive ICs (221a, 221b) disposed at both left and right ends among the plurality of drive ICs (221a, 222a, 223a, 221b, 222b, 223b). A gate signal can be generated by receiving the signal. However, it is not limited to this, and if the plurality of GIP circuits (2111a, 2111b) are arranged only on the left side of the inactive area, the plurality of drive ICs (221a, 222a, 223a, 221b, 222b, 223b) arranged at the left end. A gate driving signal can be received from the drive IC 221a.

A plurality of drive ICs 221a, 222a, 223a, 221b, 222b, and 223b are disposed at one end of the panel and are connected to a plurality of data lines DL to transmit data signals to the data lines DL. Six drive ICs (221a, 222a, 223a, 221b, 222b, 223b) are shown, but are not limited thereto. In addition, the plurality of drive ICs arranged on the left side of the center of the display panel 210 can be referred to as the first group of drive ICs 221a, 222a, and 223a, and the plurality of drive ICs arranged on the right side can be referred to as the first group of drive ICs 221a, 222a, and 223a. It can be referred to as group 2 drive ICs (221b, 222b, 223b).

Among the drive ICs 221a, 222a, and 223a of the first group, the drive IC disposed on the leftmost side can be referred to as the first drive IC 221a, and the first drive IC 221a is located on the left side of the display panel 210. A plurality of gate driving signals can be transmitted to the GIP circuits (2111a, 2111b) formed in the arranged inactive areas (211a, 211b), and the rightmost one of the second group of drive ICs (221b, 222b, 223b) The arranged drive IC can be referred to as the second drive IC (221b), and the second drive IC (221b) is a GIP circuit formed in the inactive areas (211a and 211b) arranged on the right side of the display panel (210). A plurality of gate driving signals can be transmitted to (2111a, 2111b). The plurality of gate control signals may include first to tenth clocks (CLK 1 to 10), even gate high voltage (VGH_E), odd gate high voltage (VGH_O), start pulse (VST), and reset signal. In addition, among the plurality of gate control signals, the even gate high voltage (VGH_E) may be transmitted to the GIP circuit disposed on the left side of the display panel 210, and the odd gate high voltage (VGH_O) may be transmitted to the right side of the display panel 210. It can be transmitted to the GIP circuit placed in .

In addition, the first group of drive ICs (221a, 222a, 223a) and the second group of drive ICs (221b, 222b, 223b) operate by receiving data control signals, and are each connected to a plurality of data lines (DL). Data signals can be transmitted.

The control unit 240 may transmit data control signals and gate control signals to a plurality of drive ICs 221a, 222a, 223a, 221b, 222b, and 223b. Additionally, the control unit 240 may transmit digital image signals to a plurality of drive ICs 221a, 222a, 223a, 221b, 222b, and 223b. The gate control signal transmitted from the control unit 240 may be a gate start pulse (GST), gate shift clock (GCLK), modulation timing shift clock (MCLK), and power supply voltage (VCC). However, it is not limited to this.

The control unit 240 can independently transmit data control signals and gate control signals to the first group of drive ICs (221a, 222a, and 223a) and the second group of drive ICs (221b, 222b, and 223b). For this purpose, the control unit 240 includes a first connection unit 241a that transmits a data control signal and a gate control signal to the first group of drive ICs 221a, 222a, and 223a, and a second group of drive ICs 221b, 222b, and 223b. ) may include a second connection portion 241b that transmits a data control signal and a gate control signal. The first connection part 241a and the second connection part 241b are formed with wiring (not shown) that transmits a data control signal and a gate control signal, respectively.

And, wiring is formed to transmit the data control signal and gate control signal transmitted from the control unit 240 to the first group drive ICs (221a, 222a, 223a) and the second group drive ICs (221b, 222b, 223b). The first PCB (212a) and the second PCB (212b) are between the control unit 240 and the first group drive ICs (221a, 222a, and 223a), respectively, and the control unit 240 and the second group drive ICs (221b, 222b). ,223b). In more detail, the first connection portion 241a of the control unit 240 is connected to one end of the first PCB 212a, and the first group of drive ICs 221a, 222a, and 223a are connected to the other end of the first PCB 212a. . Additionally, the second connection portion 241b of the control unit 240 is connected to one end of the second PCB 212b, and the second group of drive ICs 221b, 222b, and 223b are connected to the other end of the second PCB 212b. Also, wiring may be formed on the first PCB 212a and the second PCB 212b, respectively. The wiring formed on the first PCB (212a) and the second PCB (212b) may be a wiring that transmits a plurality of gate control signals, a digital image signal, and a data control signal that are transmitted to the source drive IC.

The wiring formed on the first PCB (212a) allows the data control signal to be transmitted to the first group of drive ICs (221a, 222a, 223a) and the gate control signal to the first group of drive ICs (221a, 222a, 223a). It can be transmitted to the first drive IC (221a) on the leftmost side. The wiring formed on the second PCB (212b) allows the data control signal to be transmitted to the second group of drive ICs (221b, 222b, and 223b) and the gate control signal to one of the second group of drive ICs (221b, 222b, and 223b). It can be transmitted to the second drive IC (221b) on the far right. The first PCB (212a) and the second PCB (212b) may be referred to as a first circuit unit and a second circuit unit, respectively.

In this case, a plurality of gate control signals are output from the control unit 240 and transmitted to the first drive IC (221a) and/or the second drive IC (221b), and the first drive IC (221a) and/or the second drive The IC 221b can output a plurality of transmitted gate control signals as a plurality of gate driving signals. Since the number of gate control signals is smaller than the number of gate drive signals, the first PCB (212a) and/or the second PCB (212b) are connected to the first drive IC (221a) and/or the second drive IC (221b). The number of gate control signals transmitted is smaller than the number of gate drive signals output from the first drive IC 221a and/or the second drive IC 221b. Therefore, the number of wires through which the gate control signal line transmitted from the control unit 240 to the first drive IC (221a) and/or the second drive IC (221b) is transmitted can be reduced, thereby reducing the thickness of the first PCB (212a). It can be implemented. Accordingly, the manufacturing cost of the first PCB 212a can be reduced. Here, only the first PCB 212a is described, but this can also be applied to the second PCB 212b.

FIG. 3A is a diagram showing an embodiment of the first drive IC used in the display device shown in FIG. 2, and FIG. 3B is a diagram showing an embodiment of the second drive IC employed in the display device shown in FIG. 2. , and FIG. 3C is a diagram showing an embodiment of the third drive IC employed in the display device shown in FIG. 2.

Referring to FIG. 3A, the first drive IC 221a may include a source drive IC 2211a and a level shifter 2212a disposed on a flexible printed circuit board (FPCB) 2213a. The source drive IC 2211a may be placed on the right side of the FPCB 2213a and the level shifter 2212a may be placed on the left side of the FPCB 2213a. That is, the source drive IC 2211a and the level shifter 2212a may be placed on the left side of the FPCB 2213a. They can be arranged side by side on the FPCB 2213a. The source drive IC 2211a and the level shifter 2212a can receive a plurality of gate control signals and a plurality of data control signals through different wiring on the FPCB 2213a. there is.

The source drive IC 2211a is connected to a plurality of data lines DL and can transmit data signals to the plurality of data lines DL. The source drive IC 2211a can receive a data control signal and a digital image signal from the control unit 240, generate a data signal, and transmit it to a plurality of data lines DL. The level shifter 2212a can receive a plurality of gate control signals from the control unit 240. The level shifter 2212a is connected to a plurality of GIP circuits 2111a and can transmit a gate driving signal to the GIP circuit 2111a. Since the plurality of gate driving signals are directly transmitted to the plurality of GIP circuits 2111a, the influence of noise may be small.

Referring to FIG. 3b, the second drive IC 221b may include a source drive IC 2211b and a level shifter 2212b disposed on a flexible printed circuit board (FPCB) 2213b. The source drive IC 2211b may be placed on the left side of the FPCB 2213b and the level shifter 2212b may be placed on the right side of the FPCB 2213b.

The source drive IC 2211b is connected to a plurality of data lines DL and can transmit data signals to the plurality of data lines DL. The source drive IC 2211b can receive a data control signal and a digital image signal from the control unit 240, generate a data signal, and transmit it to a plurality of data lines DL. The level shifter 2212b can receive a plurality of gate control signals from the control unit 240. The level shifter 2212b is connected to a plurality of GIP circuits 2111b and can transmit a gate driving signal to the GIP circuit 2111b.

The order in which the source drive IC (2211a) and level shifter (2212a) of the first drive IC (221a) are arranged on the FPCB (2213a) is the same as that of the source drive (2211b) and level shifter (2212b) of the second drive IC (221b). The order in which they are placed in the FPCB 2213b may be reversed.

Referring to FIG. 3C, the third drive IC 222a and the source drive IC 2221a may be disposed on the FPCB 2223a. The source drive IC 2221a can receive a data control signal and a digital image signal from the control unit 240, generate a data signal, and transmit it to a plurality of data lines DL. Additionally, the fourth drive IC 222b, the fifth drive IC 223a, and the sixth drive IC 223b may be formed identically to the third drive IC 222a.

In addition, each FPCB (2213a, 2213b, 2223a) included in the first drive IC (221a), second drive IC (221b), and third drive IC (222a) may have the same size, so that an FPCB with one size can be used. Therefore, there is no need to manufacture FPCBs of different sizes corresponding to the location where the drive IC is placed. Here, identical does not mean complete identical but may include slight differences in size.

FIG. 4A is a structural diagram showing an embodiment of the first level shifter shown in FIG. 3A, and FIG. 4B is a structural diagram showing an embodiment of the second level shifter shown in FIG. 3B.

Referring to FIG. 4A, the first level shifter 2211a can receive a plurality of gate control signals from the control unit 240 and transmit a plurality of gate driving signals. The plurality of gate control signals may be an even/odd (E/O) clock, gate start pulse (GST), gate shift clock (GCLK), modulation timing shift clock (MCLK), and power supply voltage (VCC). In addition, the first level shifter (2211a) includes a plurality of input pins, and from left to right, even/odd (E/O) clock, gate start pulse (GST), gate shift clock (GCLK), and modulation timing shift It can receive clock (MCLK) and power voltage (VCC). And, the first level shifter (2211a) shifts the received even/odd (E/O) clock, gate start pulse (GST), gate shift clock (GCLK), modulation timing shift clock (MCLK), and power supply voltage (VCC). Using this, the first to tenth clocks (CLK 1 to 10), even gate high voltage (VGH_E), odd gate high voltage (VGH_O), start pulse (VST), and reset signal (Reset) can be output. The first level shifter (2211a), from left to right, includes first to tenth clocks (CLK 1 to 10), even gate high voltage (VGH_E), odd gate high voltage (VGH_O), start pulse (VST), and reset signal. (Reset) can be output.

Referring to FIG. 4B, the second level shifter 2211b can receive a plurality of gate control signals from the control unit 240 and transmit a plurality of gate driving signals. The plurality of gate control signals may be an even/odd (E/O) clock, gate start pulse (GST), gate shift clock (GCLK), modulation timing shift clock (MCLK), and power supply voltage (VCC). In addition, the second level shifter (2211b), from right to left, includes an even/odd (E/O) clock, gate start pulse (GST), gate shift clock (GCLK), modulation timing shift clock (MCLK), and power supply voltage ( VCC) can be delivered. And, the second level shifter (2211b) shifts the received even/odd (E/O) clock, gate start pulse (GST), gate shift clock (GCLK), modulation timing shift clock (MCLK), and power supply voltage (VCC). Using this, the first to tenth clocks (CLK 1 to 10), even gate high voltage (VGH_E), odd gate high voltage (VGH_O), start pulse (VST), and reset signal (Reset) can be output. The second level shifter (2211b) operates from right to left: first to tenth clocks (CLK 1 to 10), even gate high voltage (VGH_E), odd gate high voltage (VGH_O), start pulse (VST), and reset signal. (Reset) can be output.

FIG. 5A is a conceptual diagram showing a method for determining that the first level shifter shown in FIG. 4A operates in the first mode, and FIG. 5B is a method for determining that the second level shifter shown in FIG. 4B operates in the second mode. This is a conceptual diagram showing the method.

Referring to FIGS. 5A and 5B, the first level shifter 2211a may connect the power supply voltage (VCC) to the first pin (vcc) and the second pin (CLK_option). When connected in this way and the power supply voltage (VCC) is transmitted to the first pin (vcc) and the second pin (CLK_option), the first level shifter (2211a) can operate at high (H). And, the second level shifter (2211b) can connect the power supply voltage (VCC) to the first pin (vcc) and the ground (GND) to the second pin (CLK_option). When the power supply voltage (VCC) is transmitted to the first pin (vcc) and the ground (GND) is transmitted to the second pin (CLK_option), the second level shifter (2211b) can operate in low (L).

The first level shifter 2211a may be placed on the left side of the display panel when operated at high (H) level, and the second level shifter 2211b may be placed on the right side of the display panel when operated at low (L) level. Accordingly, the first level shifter 2211a and the second level shifter can be placed on the left or right side of the display panel 210 by adjusting the voltage delivered to the first pin (vcc) and the second pin (CLK_option). Therefore, there is no need to design the level shifter considering its placement on the left and right.

Table 1 below shows the signals output from the output pin when the level shifter operates high (H) and low (L).

H L P number output signal P number One CLK1 One CLK10 2 CLK2 2 CLK9 3 CLK3 3 CLK8 4 CLK4 4 CLK7 5 CLK5 5 CLK6 6 CLK6 6 CLK5 7 CLK7 7 CLK4 8 CLK8 8 CLK3 9 CLK9 9 CLK2 10 CLK10 10 CLK1

Looking at Table 1 above, when the level shifter operates high (H) and when it operates low (L), the order of signals coming out of the pin may be reversed. Also, by changing the order of output signals according to the level shifter being placed on the left and right sides of the display panel, the wiring of the signal transmitted from the control unit to the level shifter can be prevented from being twisted.

FIG. 6 is a conceptual diagram showing an embodiment of the first PCB shown in FIG. 2.

Referring to FIG. 6, the first PCB (212a) can receive five gate control signals from the input pad (IN) and transmit them to the output pad (OUT). Five gate control signals can each be transmitted through five wires. Accordingly, the first PCB 212a may include five lines for transmitting the gate control signal. Additionally, five wires may be arranged horizontally in one section of the first PCB 212a. The thickness of the first PCB 212a can be determined by the width of five wires. Here, the horizontal direction may be the direction in which the first PCB 212a is long. Additionally, one section may mean a distance that prevents the input pad (IN) and output pad (OUT) from being vertically aligned. Here, the first PCB (212a) is shown, but the same can be applied to the second PCB (212b) shown in FIG. 2.

FIG. 7 is a conceptual diagram showing another embodiment of the first drive IC shown in FIG. 2.

Referring to FIG. 7, the source drive IC 7112 is placed in the center of the first drive IC 721a, and wiring 7111a and 7111b for signals transmitted from the control unit can be formed on both sides of the source drive IC 7112, respectively. there is. In this case, the control unit includes a level shifter (not shown), transfers a plurality of gate control signals from the control unit to the level shifter, and the level shifter can change the plurality of gate control signals into a plurality of gate driving signals and output them. And, the plurality of gate control signals include an even/odd (E/O) clock, gate start pulse (GST), gate shift clock (GCLK), modulation timing shift clock (MCLK), and power supply voltage (VCC). The gate driving signal of the source drive IC 7112 includes the first to tenth clock, even gate high voltage (VGH_E), odd gate high voltage (VGH_O), start pulse (VST), and reset signal (Reset). The number of lines of wiring (7111a, 7111b) arranged on both sides may be 14.

In addition, a plurality of gate driving signals are output from the level shifter connected to the control unit and transmitted to the GIP circuit through the wiring (7111a, 7111b) formed in the first PCB (212a) and the first drive IC (721a), so that the plurality of gate driving signals are output from the level shifter connected to the control unit. The length of the wiring through which the driving signal is transmitted may be long. As a result, the plurality of gate driving signals may be greatly affected by noise.

FIG. 8 is a conceptual diagram showing another embodiment of the first PCB shown in FIG. 2.

Referring to FIG. 8, the first PCB (812a) can receive 14 gate drive signals from the input pad (IN) and transmit them to the output pad (OUT). Accordingly, the first PCB 812a may include 14 lines for transmitting gate control signals. Therefore, the number of lines included in the wiring is 9 more than those shown in FIG. 6 and the first PCB 212a, and since the wiring runs in the horizontal direction, the width is wider than that of the first PCB 212a shown in FIG. 6. It may become thick. The width of the first PCB 812a may refer to the length in the vertical direction.

The above description and attached drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art will be able to combine the components without departing from the essential characteristics of the present invention. , various modifications and transformations such as separation, substitution, and change will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

200: display device
210: display panel
210a: active area
211a, 211b: Inactive area
212a, 212b: 1st PCB, 2nd PCB
221a, 222a, 223a: First group drive IC
221b, 222b, 223b: second group drive IC
240: control unit
241a, 241b: first connection part, second connection part
2111a, 2111b: GIP circuit
GL: Gateline
DL: data line

Claims (12)

delete delete delete A display panel in which pixels are formed in an area where a plurality of gate lines and a plurality of data lines intersect;
a plurality of drive ICs that drive the display panel by transmitting gate signals and data signals to the plurality of gate lines and the plurality of data lines; and
It includes a control unit that outputs a plurality of gate control signals and a plurality of data control signals,
The plurality of drive ICs include a first drive IC and a second drive IC,
The first drive IC includes a first level shifter,
The second drive IC includes a second level shifter,
The first level shifter receives power voltage from the first and second pins,
The second level shifter receives the power voltage through a first pin and a ground voltage through a second pin,
A display device in which the output channels of the first level shifter are arranged in a reverse order to the output channels of the second level shifter. According to paragraph 4,
The display panel further includes a GIP circuit that drives a gate signal to the gate line, and the plurality of gate driving signals are supplied to the GIP circuit. According to paragraph 4,
A display device in which the first drive IC is disposed at the left end of the display panel and the second drive IC is disposed at the right end of the display panel. According to paragraph 4,
A first group of drive ICs including a first drive IC that receives the plurality of gate control signals and outputs a first gate driving signal corresponding to an odd-numbered gate line among the plurality of gate lines;
a second group of drive ICs including a second drive IC that receives the plurality of gate control signals and outputs a second gate driving signal corresponding to an even-numbered gate line among the plurality of gate lines;
a first circuit unit connecting the control unit and the first group of drive ICs; and
It includes a second circuit unit connecting the control unit and the second group of drive ICs,
A display device in which wiring for transmitting the plurality of gate control signals is arranged horizontally in one section of the first circuit unit and the second circuit unit. A display panel in which pixels are formed in an area where a plurality of gate lines and a plurality of data lines intersect;
a control unit outputting a plurality of gate control signals to control driving of the display panel;
A first group of drive ICs including a first drive IC that receives the plurality of gate control signals and outputs a first gate driving signal corresponding to an odd-numbered gate line among the plurality of gate lines;
a second group of drive ICs including a second drive IC that receives the plurality of gate control signals and outputs a second gate driving signal corresponding to an even-numbered gate line among the plurality of gate lines;
a first circuit unit connecting the control unit and the first group of drive ICs;
A second circuit unit connecting the control unit and the second group of drive ICs,
The first drive IC includes a first level shifter and a first source drive IC,
The second drive IC includes a second level shifter and a second source drive IC,
The first level shifter receives power voltage from the first and second pins,
The second level shifter receives the power voltage through a first pin and a ground voltage through a second pin,
A display device in which the output channels of the first level shifter are arranged in a reverse order to the output channels of the second level shifter. According to clause 8,
A display device in which the first drive IC is disposed at the left end of the display panel and the second drive IC is disposed at the right end of the display panel. According to clause 8,
The display panel further includes a plurality of GIP circuits that transmit gate signals to the gate lines, wherein the first gate driving signal is supplied to the GIP circuit connected to the odd-numbered gate line and the second gate driving signal is supplied to the even-numbered gate line. A display device supplied to the GIP circuit connected to the gate line. According to clause 8,
The plurality of gate control signals include an even/odd (E/O) clock, gate start pulse (GST), gate shift clock (GCLK), modulation timing shift clock (MCLK), and power supply voltage (VCC). The first gate driving signal and the plurality of second gate driving signals are respectively first to tenth clocks (CLK 1 to 10), even gate high voltage (VGH_E), odd gate high voltage (VGH_O), and start pulse (VST). ), a display device including a reset signal (Reset). According to clause 8,
A display device in which wiring for transmitting the plurality of gate control signals is arranged horizontally in one section of the first circuit unit and the second circuit unit.

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