CN111243500B - Display panel - Google Patents
Display panel Download PDFInfo
- Publication number
- CN111243500B CN111243500B CN201811444500.9A CN201811444500A CN111243500B CN 111243500 B CN111243500 B CN 111243500B CN 201811444500 A CN201811444500 A CN 201811444500A CN 111243500 B CN111243500 B CN 111243500B
- Authority
- CN
- China
- Prior art keywords
- signal
- driving circuit
- display panel
- display area
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The invention provides a display panel, the display panel includes display area and non-display area, the display panel includes: a substrate; a plurality of first signal lines extending along a first direction, the first signal lines being located on the substrate, the plurality of first signal lines penetrating the display area along the first direction; the first signal driving circuit is positioned on the substrate and positioned in the non-display area on any side of the display area in a second direction, and the second direction is vertical to the first direction; a plurality of first signal connecting lines extending along the second direction, located on the substrate, for connecting each first signal line from the display area to the first signal driving circuit of the non-display area; and an IC drive circuit on the substrate, the first signal drive circuit being located between the IC drive circuit and the display region, the IC drive circuit providing N input signals to the first signal drive circuit through the N connection portions, and outputting M output signals to the first signal lines by the first signal drive circuit. The invention realizes the narrow frame of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel.
Background
In recent years, the OLED (Organic Light-Emitting Diode) technology has been developed rapidly, and has become a promising technology for replacing the LCD (Liquid Crystal Display) most probably.
In the prior art, the OLED display panel includes an array substrate and a scan signal driving circuit and/or a light emitting signal driving circuit on the array substrate, however, the scan signal driving circuit and/or the light emitting signal driving circuit generally occupy a larger area, and particularly, the scan signal driving circuit and/or the light emitting signal driving circuit are generally disposed on one side or both sides of a display region in an extending direction of a scan signal line/a light emitting signal line.
In particular, reference may be made to fig. 1, which shows a schematic view of a prior art display panel. The display panel is an OLED display panel 20. The OLED display panel 20 includes at least a display unit 200, a scan driver 220, and a data driver 230. Other devices and/or elements may also be included in the OLED display device 20.
The display unit 200 may include a plurality of sub-pixels (or pixels) 210 connected to scan lines (S1 to Sn), emission control lines (EM1 to EMn), and data lines (D1 to Dm).
The display unit 200 may display an image so as to correspond to a first power source (ELVdd) provided from the outside and a second power source (ELVss) provided from the outside. The display unit 200 may also display images corresponding to scan signals supplied from the scan lines S1 to Sn generated by the scan driver 220 and light emission control signals supplied from the light emission control lines EM1 to EMn, and data signals supplied from the data lines D1 to Dm generated by the data driver 230.
The scan driver 220 may generate a scan signal and a light emission control signal. The scan signal generated within the scan driver 220 may be sequentially supplied to the gate lines (S1 to Sn), and the light emission control signal may be sequentially supplied to each of the light emission control lines (EM1 to EMn). The scan signal and the light emission signal may also be supplied to the gate lines S1 to Sn and the light emission control lines EM1 to EMn, respectively, out of order. In other embodiments, the light emission control signal may also be generated by a light emission control driver.
The data driver 230 may receive an input signal, for example, RGB data, and may generate a data signal corresponding to the received input signal. The data signals generated in the data driver 230 may be supplied to the subpixels 210 through the data lines (D1 through Dm) so as to be synchronized with the scan signals. The data signals may also be supplied to the data lines D1 through Dm in a manner asynchronous with the scan signals.
Therefore, in the prior art, the scan signal driving circuit and/or the light emitting signal driving circuit are generally disposed on one side or both sides of the display area in the extending direction of the scan signal line/the light emitting signal line, so that the side frame of the display panel is wider, and it is difficult to realize a narrow frame of the display panel.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art, and provides a display panel, which realizes a narrow bezel of the display panel and reduces the number of connection portions between an IC driving circuit and a first signal driving circuit.
The invention provides a display panel, the display panel includes display area and non-display area, the display panel includes:
a substrate;
a plurality of first signal lines extending along a first direction, the plurality of first signal lines being located on the substrate and penetrating through the display area along the first direction;
the first signal driving circuit is positioned on the substrate and positioned in a non-display area on any side of the display area in a second direction, and the second direction is perpendicular to the first direction;
a plurality of first signal connection lines extending along the second direction, located on the substrate, for connecting each first signal line from the display area to the first signal driving circuit of the non-display area; and
the IC drive circuit is positioned on the substrate, the first signal drive circuit is positioned between the IC drive circuit and the display area, the IC drive circuit provides N input signals for the first signal drive circuit through N connecting parts, and M output signals are output to the first signal line by the first signal drive circuit, wherein N, M is a positive integer, and N is less than M.
Optionally, the first signal driving circuit comprises a plurality of multiplexers.
Optionally, each of the multiplexers includes 1 input terminal, k nMOS or pMOS terminals, k control terminals, and k output terminals, the k control terminals respectively receiving 1 clock signal, where k is an integer greater than 1, and M is k times N.
Optionally, each of the multiplexers includes 1 input terminal, k CMOS, k pairs of control terminals and k output terminals, each pair of control terminals receives the same clock signal, where k is an integer greater than 1, and M is k times N.
Optionally, each of the multiplexers includes 1 input terminal, k bootstrap boost circuits, k pairs of control terminals and k output terminals, each pair of control terminals receives a different clock signal, where k is an integer greater than 1, and M is k times N.
Optionally, the first signal driving circuit includes a plurality of shift register units.
Alternatively, the first signal line includes a scanning signal line and/or a light emitting signal line, and the first signal driver circuit includes a scanning signal driver circuit and/or a light emitting signal driver circuit.
Alternatively, the first signal driving circuit includes the scanning signal driving circuit and a light-emitting signal driving circuit.
Optionally, the first signal driving circuit includes one of the scanning signal driving circuit and the light-emitting signal driving circuit, and the other is located in a non-display area on a side of the display area different from the first signal driving circuit in the second direction.
Optionally, each of the first signal connection lines is connected to the first signal line through a via.
Compared with the prior art, the display panel provided by the invention has the advantages that the first signal driving circuit is arranged in the extending direction perpendicular to the first signal lines, the first signal connecting lines are arranged in the extending direction perpendicular to the first signal lines, so that the signals of the first signal driving circuit are supplied to the first signal lines, and the narrow frame of the display panel is realized in the extending direction of the first signal lines. On the other hand, through the first signal driving circuit, the IC driving circuit provides N input signals to the first signal driving circuit through N connecting parts, and the first signal driving circuit outputs M output signals to the first signal line, so that the number of the connecting parts is reduced, the manufacturing cost is reduced, and the display panel is more suitable for the display panel with low resolution requirements.
Drawings
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 shows a schematic view of a prior art display panel.
Fig. 2 shows a schematic diagram of a display panel of an embodiment of the invention.
Fig. 3 shows a schematic diagram of a multiplexer of the first signal driving circuit of an embodiment of the present invention.
Fig. 4 shows a schematic diagram of a multiplexer according to a first embodiment of the invention.
Fig. 5 shows a schematic diagram of a multiplexer according to a second embodiment of the present invention.
Fig. 6 shows a timing diagram of the signals of the circuit of fig. 5.
Fig. 7 shows a schematic diagram of a multiplexer according to a third embodiment of the present invention.
Fig. 8 shows a timing diagram of the circuit signals in fig. 7.
Fig. 9 shows a schematic diagram of a multiplexer according to a fourth embodiment of the present invention.
Fig. 10 shows a timing diagram of the circuit signals in fig. 9.
Fig. 11 shows a schematic diagram of a shift register unit of the first signal driving circuit according to an embodiment of the present invention.
Fig. 12 shows a schematic view of a display panel of another embodiment of the present invention.
Fig. 13 shows a schematic view of a display panel according to still another embodiment of the present invention.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In some instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the invention.
The drawings of the present invention are only for illustrating the relative positional relationship, and the dimensions of some parts are exaggerated in the drawing for easy understanding, and the dimensions in the drawings do not represent the proportional relationship of the actual dimensions.
In order to realize a narrow bezel of a display panel while reducing the number of connection portions between an IC driving circuit and a first signal driving circuit, the present invention provides a display panel. The display panel includes: a substrate; a plurality of first signal lines extending along a first direction, the plurality of first signal lines being located on the substrate and penetrating through the display area along the first direction; the first signal driving circuit is positioned on the substrate and positioned in a non-display area on any side of the display area in a second direction, and the second direction is perpendicular to the first direction; a plurality of first signal connection lines extending along the second direction, located on the substrate, for connecting each first signal line from the display area to the first signal driving circuit of the non-display area; and an IC drive circuit on the substrate, the first signal drive circuit being between the IC drive circuit and the display region, the IC drive circuit providing N input signals to the first signal drive circuit through N connecting portions and outputting M output signals to the first signal line by the first signal drive circuit, wherein N, M is a positive integer and N is less than M.
The following describes several embodiments provided by the present invention with reference to the drawings.
Referring first to fig. 2, fig. 2 shows a schematic view of a display panel of an embodiment of the present invention. The display panel 100 includes a display area 101 and a non-display area 102. The display panel 100 includes a substrate 110, a plurality of first signal lines 120, a first signal driving circuit 140, a plurality of first signal connecting lines 130, and an IC driving circuit 150.
The plurality of first signal lines 120 extend in a first direction (horizontal direction in fig. 1). The plurality of first signal lines 120 are disposed on the substrate 110, and the plurality of first signal lines 120 penetrate the display region 101 along a first direction.
The first signal driving circuit 140 is located on the substrate 110. The first signal driving circuit 140 is located in the non-display area 102 on either side of the display area 101 in a second direction (vertical direction in the drawing) perpendicular to the first direction.
Specifically, the first signal lines 120 may be scanning signal lines, and the corresponding first signal driving circuits 140 may be scanning signal driving circuits. The first signal line 120 may be a light emitting signal line, and the corresponding first signal driving circuit 140 may be a light emitting signal driving circuit. The first signal lines 120 may include light emitting signal lines and scanning signal lines, and the corresponding first signal driving circuits 140 may include light emitting signal driving circuits and scanning signal line driving circuits.
The plurality of first signal connection lines 130 extend in the second direction. A plurality of first signal connecting lines 130 are disposed on the substrate 110 for connecting each first signal line 120 from the display area 101 to the first signal driving circuit 140 of the non-display area 102. Specifically, each of the first signal connection lines 130 is connected to the first signal line 120 through a via.
The IC driving circuit 150 is located on the substrate 110. The first signal driving circuit 140 is located between the IC driving circuit 150 and the display region 101, the IC driving circuit 150 provides N input signals to the first signal driving circuit 140 through N connection portions 160 (see fig. 2), and the first signal driving circuit 140 outputs M output signals to the first signal line 120, where N, M is a positive integer and N is less than M.
Therefore, according to the display panel provided by the invention, the first signal driving circuit is arranged in the extending direction perpendicular to the first signal lines, and the first signal connecting lines are arranged in the extending direction perpendicular to the first signal lines, so that the signals of the first signal driving circuit are supplied to the first signal lines, and the narrow frame of the display panel is realized in the extending direction of the first signal lines. On the other hand, through the first signal driving circuit, the IC driving circuit provides N input signals to the first signal driving circuit through N connecting parts, and the first signal driving circuit outputs M output signals to the first signal line, so that the number of the connecting parts is reduced, the manufacturing cost is reduced, and the display panel is more suitable for the display panel with low resolution requirements.
In one embodiment of the present invention, the first signal driving circuit 140 includes a plurality of multiplexers 141 (see fig. 1 and 2). Each of the multiplexers 141 includes an input terminal connected to the connection 160 and a plurality of output terminals connected to the first signal connection line 130, thereby achieving a reduction in the number of connections 160.
In a first embodiment of the multiplexer, see fig. 4. Each of the multiplexers includes 1 input terminal connected to the connection 160, k nmoss, k control terminals (e.g., gates of k nmoss) respectively receiving 1 clock signal, where k is an integer greater than 1, and M is k times N, and k output terminals. In this embodiment, k is 3, and the clock signals include three clock signals CLKA, CLKB, and CLKC. The connection 160 inputs the signal Sn-1 to the input terminal of the multiplexer 141, and the multiplexer 141 outputs three signals Sout (n-1,1), Sout (n-1,2) and Sout (n-1, 3). Thus, M is 3 times N, which is not a limitation of the present invention.
Fig. 5 shows a schematic diagram of a multiplexer according to a second embodiment of the present invention. In this embodiment, each of the multiplexers includes 1 input terminal connected to the connection part 160, k pMOS terminals, k control terminals (for example, gates of the k pMOS terminals), and k output terminals, and the k control terminals respectively receive 1 clock signal, where k is an integer greater than 1, and M is k times N. In this embodiment, k is 3, and the clock signals include three clock signals CLKA, CLKB, and CLKC. The connection 160 inputs the signal Sn-1 to the input terminal of the multiplexer 141, and the multiplexer 141 outputs three signals Sout (n-1,1), Sout (n-1,2) and Sout (n-1, 3). Thus, M is 3 times N, which is not a limitation of the present invention. Fig. 6 shows a timing diagram of the signals of the circuit of fig. 5. Wherein Sn and Sn +1 are input signals of the next two multiplexers, Sout (n,1), Sout (n,2), and Sout (n,3) are output signals of the related signal Sn, Sout (n +1,1), Sout (n +1,2), and Sout (n +1,3) are output signals of the related signal Sn + 1. The invention is not limited thereto.
Fig. 7 shows a schematic diagram of a multiplexer according to a third embodiment of the present invention. In this embodiment, each of the multiplexers 141 includes 1 input terminal, k CMOS, k pairs of control terminals and k output terminals, each pair of control terminals receives the same clock signal, where k is an integer greater than 1, and M is k times N. In this embodiment, k is 3, and the clock signals include three clock signals CLKA, CLKB, and CLKC. Each CMOS is connected to the same clock signal, the connection 160 inputs the signal Sn-1 to the input of the multiplexer 141, and the multiplexer 141 outputs three signals Sout (n-1,1), Sout (n-1,2), Sout (n-1, 3). Thus, M is 3 times N, which is not a limitation of the present invention. Fig. 8 shows a timing diagram of the circuit signals in fig. 7. Wherein Sn and Sn +1 are input signals of the next two multiplexers, Sout (n,1), Sout (n,2), and Sout (n,3) are output signals of the related signal Sn, Sout (n +1,1), Sout (n +1,2), and Sout (n +1,3) are output signals of the related signal Sn + 1. The invention is not limited thereto.
Fig. 9 shows a schematic diagram of a multiplexer according to a fourth embodiment of the present invention. In this embodiment, each of the multiplexers includes 1 input terminal, k bootstrap boost circuits, k pairs of control terminals and k output terminals, each pair of control terminals receives a different clock signal, where k is an integer greater than 1, and M is k times N. In this embodiment, k is 3, and the clock signals include three clock signals CLKA, CLKB, and CLKC. Each bootstrap boosting circuit connects two adjacent clock signals, the connection 160 inputs the signal Sn-1 to the input of the multiplexer 141, and the multiplexer 141 outputs three signals Sout (n-1,1), Sout (n-1,2), Sout (n-1, 3). Fig. 10 shows a timing diagram of the circuit signals in fig. 9. Wherein Sn and Sn +1 are input signals of the next two multiplexers, Sout (n,1), Sout (n,2), and Sout (n,3) are output signals of the related signal Sn, Sout (n +1,1), Sout (n +1,2), and Sout (n +1,3) are output signals of the related signal Sn + 1. The invention is not limited thereto.
In one embodiment of the present invention, the first signal driving circuit 140 includes a plurality of shift register units 141 (see fig. 11). The first shift register unit 141 of the plurality of shift register units 141 receives the start vertical driving signal, and each shift register unit 141 outputs a signal to the next shift register unit 141 in addition to outputting a signal to the first signal connection line. In this embodiment, two clock signals CLKA, CLKB are supplied to the first signal driving circuit 140. The adjacent two shift register units 141 are connected to different clock signals, thereby achieving a reduction in the number of connection sections 160. The invention is not limited thereto.
Referring now to fig. 12, fig. 12 is a schematic diagram of a display panel according to another embodiment of the present invention.
In the present embodiment, the first signal lines 120 are scanning signal lines. The display panel includes a light emitting signal line and a light emitting signal driving circuit 141 extending in a first direction, in addition to the substrate, the plurality of first signal lines, the first signal driving circuit (scanning signal driving circuit 142), the plurality of first signal connection lines, and the IC driving circuit 150. The light emitting signal driving circuit 141 connects the light emitting signal lines through light emitting signal connection lines extending in the second direction. The display region 101 is located between the light-emission signal driving circuit 141 and the scan signal driving circuit 142, thereby realizing a narrow bezel of the display panel. In this embodiment, the scanning signal driving circuit 142 can be interchanged with the light emitting signal driving circuit 141 in position, and the scanning signal line can be interchanged with the light emitting signal line in position. In the present embodiment, the via holes between the scan signal lines and the scan signal connection lines and the via holes between the light emitting signal lines and the light emitting signal connection lines are disposed opposite to each other, and the via holes form a triangle toward the IC driving circuit 150, thereby optimizing the via hole distribution.
Referring now to fig. 13, fig. 13 is a schematic diagram of a display panel in accordance with yet another embodiment of the present invention.
In the present embodiment, the display panel includes a substrate, a plurality of first signal lines, a first signal driving circuit, a plurality of first signal connecting lines, and an IC driving circuit 150. The first signal line includes a scan signal line and a light emitting signal line, and the first signal driving circuit includes a scan signal driving circuit 141 and a light emitting signal driving circuit 142. The scan signal driving circuit 141 is disposed adjacent to the light emission signal driving circuit 142 in the first direction. In the present embodiment, the via holes between the scan signal lines and the scan signal connection lines and the via holes between the light emitting signal lines and the light emitting signal connection lines are oppositely disposed to form a triangle toward the IC driving circuit 150, thereby optimizing the via hole distribution.
The above embodiments and variations are merely illustrative of the basic concept of the present invention, and those skilled in the art can implement many modifications without departing from the basic concept of the present invention.
Compared with the prior art, the display panel provided by the invention has the advantages that the first signal driving circuit is arranged in the extending direction perpendicular to the first signal lines, the first signal connecting lines are arranged in the extending direction perpendicular to the first signal lines, so that the signals of the first signal driving circuit are supplied to the first signal lines, and the narrow frame of the display panel is realized in the extending direction of the first signal lines. On the other hand, through the first signal driving circuit, the IC driving circuit provides N input signals to the first signal driving circuit through N connecting parts, and the first signal driving circuit outputs M output signals to the first signal line, so that the number of the connecting parts is reduced, the manufacturing cost is reduced, and the display panel is more suitable for the display panel with low resolution requirements.
Exemplary embodiments of the present invention are specifically illustrated and described above. It is to be understood that the invention is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.
Claims (8)
1. A display panel, comprising a display area and a non-display area, the display panel comprising:
a substrate;
a plurality of first signal lines extending along a first direction, the plurality of first signal lines being located on the substrate and penetrating through the display area along the first direction;
the first signal driving circuit is positioned on the substrate and positioned in a non-display area on any side of the display area in a second direction, and the second direction is perpendicular to the first direction;
a plurality of first signal connection lines extending along the second direction, located on the substrate, for connecting each first signal line from the display area to the first signal driving circuit of the non-display area; and
an IC drive circuit on the substrate, the first signal drive circuit being between the IC drive circuit and the display area, the IC drive circuit providing N input signals to the first signal drive circuit through N connection portions and outputting M output signals to the first signal line by the first signal drive circuit, wherein N, M is a positive integer and N is less than M,
the first signal line includes a scan signal line and/or a light emitting signal line, the first signal driving circuit includes a scan signal driving circuit and/or a light emitting signal driving circuit, the first signal driving circuit includes a plurality of multiplexers, and the multiplexers include a plurality of control terminals receiving a clock signal.
2. The display panel of claim 1, wherein each of the multiplexers includes 1 input terminal, k nMOS or pMOS, k control terminals respectively receiving 1 clock signal, and k output terminals, wherein k is an integer greater than 1, and M is k times N.
3. The display panel of claim 1, wherein each of the multiplexers includes 1 input terminal, k CMOS, k pairs of control terminals and k output terminals, each pair of control terminals receiving a same clock signal, wherein k is an integer greater than 1, and M is k times N.
4. The display panel of claim 1, wherein each of the multiplexers includes 1 input terminal, k bootstrap boost circuits, k pairs of control terminals and k output terminals, each pair of control terminals receiving a different clock signal, wherein k is an integer greater than 1 and M is k times N.
5. The display panel according to claim 1, wherein the first signal driving circuit includes a plurality of shift register units.
6. The display panel according to claim 1, wherein the first signal driver circuit includes the scan signal driver circuit and a light-emission signal driver circuit.
7. The display panel according to claim 1, wherein the first signal driver circuit includes one of the scan signal driver circuit and the light-emission signal driver circuit, and the other is located in a non-display region on a side of the display region different from the first signal driver circuit in the second direction.
8. The display panel according to any one of claims 1 to 5, wherein each of the first signal connection lines is connected to the first signal line through a via.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811444500.9A CN111243500B (en) | 2018-11-29 | 2018-11-29 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811444500.9A CN111243500B (en) | 2018-11-29 | 2018-11-29 | Display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111243500A CN111243500A (en) | 2020-06-05 |
| CN111243500B true CN111243500B (en) | 2022-02-11 |
Family
ID=70879229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811444500.9A Active CN111243500B (en) | 2018-11-29 | 2018-11-29 | Display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111243500B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256732A (en) * | 2007-03-02 | 2008-09-03 | 三星Sdi株式会社 | Organic light emitting display |
| CN104505031A (en) * | 2014-09-19 | 2015-04-08 | 深圳市华星光电技术有限公司 | Display panel and drive method thereof |
| US20150097190A1 (en) * | 2013-10-07 | 2015-04-09 | Tianma Micro-Electronics Co., Ltd. | Tft array substrate, display panel and display device |
| CN104700796A (en) * | 2013-12-09 | 2015-06-10 | 乐金显示有限公司 | Liquid crystal display device and manfatureing method thereof |
| CN204706018U (en) * | 2015-06-30 | 2015-10-14 | 京东方科技集团股份有限公司 | Touch-control display panel and display device |
| CN105742312A (en) * | 2014-12-31 | 2016-07-06 | 乐金显示有限公司 | Organic light emitting display device |
| CN106200176A (en) * | 2016-08-25 | 2016-12-07 | 深圳市华星光电技术有限公司 | Display floater and display |
| CN106444192A (en) * | 2016-11-09 | 2017-02-22 | 厦门天马微电子有限公司 | Array substrate and drive method, display panel thereof |
| CN206349087U (en) * | 2016-10-31 | 2017-07-21 | 厦门天马微电子有限公司 | A kind of display panel and display device |
| CN107644612A (en) * | 2016-07-22 | 2018-01-30 | 上海和辉光电有限公司 | Display device and its driving method |
| CN107919059A (en) * | 2017-11-09 | 2018-04-17 | 上海中航光电子有限公司 | Display base plate, display panel and display device |
| CN108254984A (en) * | 2018-01-31 | 2018-07-06 | 上海天马微电子有限公司 | Display panel and display device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2546289A1 (en) * | 2003-11-13 | 2005-06-02 | Metrologic Instruments, Inc. | Hand-supportable imaging-based bar code symbol reader supporting narrow-area and wide-area modes of illumination and image capture |
| CN102629053A (en) * | 2011-08-29 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate and display device |
| JP2015195327A (en) * | 2013-06-05 | 2015-11-05 | 株式会社半導体エネルギー研究所 | semiconductor device |
| CN103871341A (en) * | 2014-03-19 | 2014-06-18 | 深圳市华星光电技术有限公司 | Test circuit and display panel |
| CN103956131B (en) * | 2014-04-16 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of pixel-driving circuit and driving method, display floater, display device |
| WO2016189414A1 (en) * | 2015-05-22 | 2016-12-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and display device including the semiconductor device |
| CN205264704U (en) * | 2016-01-04 | 2016-05-25 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN107464824B (en) * | 2016-06-03 | 2020-02-21 | 上海和辉光电有限公司 | Display panel |
| CN106406623B (en) * | 2016-10-31 | 2020-04-03 | 厦门天马微电子有限公司 | Array substrate, touch display panel and touch display device |
| CN108630144A (en) * | 2018-06-19 | 2018-10-09 | 武汉天马微电子有限公司 | Display panel and display device |
-
2018
- 2018-11-29 CN CN201811444500.9A patent/CN111243500B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256732A (en) * | 2007-03-02 | 2008-09-03 | 三星Sdi株式会社 | Organic light emitting display |
| US20150097190A1 (en) * | 2013-10-07 | 2015-04-09 | Tianma Micro-Electronics Co., Ltd. | Tft array substrate, display panel and display device |
| CN104700796A (en) * | 2013-12-09 | 2015-06-10 | 乐金显示有限公司 | Liquid crystal display device and manfatureing method thereof |
| CN104505031A (en) * | 2014-09-19 | 2015-04-08 | 深圳市华星光电技术有限公司 | Display panel and drive method thereof |
| CN105742312A (en) * | 2014-12-31 | 2016-07-06 | 乐金显示有限公司 | Organic light emitting display device |
| CN204706018U (en) * | 2015-06-30 | 2015-10-14 | 京东方科技集团股份有限公司 | Touch-control display panel and display device |
| CN107644612A (en) * | 2016-07-22 | 2018-01-30 | 上海和辉光电有限公司 | Display device and its driving method |
| CN106200176A (en) * | 2016-08-25 | 2016-12-07 | 深圳市华星光电技术有限公司 | Display floater and display |
| CN206349087U (en) * | 2016-10-31 | 2017-07-21 | 厦门天马微电子有限公司 | A kind of display panel and display device |
| CN106444192A (en) * | 2016-11-09 | 2017-02-22 | 厦门天马微电子有限公司 | Array substrate and drive method, display panel thereof |
| CN107919059A (en) * | 2017-11-09 | 2018-04-17 | 上海中航光电子有限公司 | Display base plate, display panel and display device |
| CN108254984A (en) * | 2018-01-31 | 2018-07-06 | 上海天马微电子有限公司 | Display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111243500A (en) | 2020-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10643563B2 (en) | Display device | |
| US9495932B2 (en) | Display device | |
| US9857900B2 (en) | Array substrate, touch display panel and driving method for array substrate | |
| US11132953B2 (en) | Display device | |
| CN106847148B (en) | Display device | |
| US7920109B2 (en) | Emission driving device of organic light emitting display device | |
| TWI514344B (en) | Display apparatus | |
| JP2022501653A (en) | Gate drive circuits, methods for controlling gate drive circuits, and mobile terminals | |
| CN109935186B (en) | Chip on film and display device including the same | |
| US9805637B2 (en) | Display devices for compensating for kickback-voltage effect | |
| KR101904277B1 (en) | Iquid crystal display apparatus | |
| KR100685699B1 (en) | Electro-optical device and electronic apparatus | |
| KR20150141263A (en) | Gate circuit and display device using the same | |
| KR20160017390A (en) | Gate driver of display device | |
| CN105139797A (en) | Special-shaped display panel and display device | |
| CN111430433B (en) | Display panel and display device | |
| WO2019186751A1 (en) | Display device | |
| US20180144679A1 (en) | Display device | |
| US7535444B2 (en) | Organic light-emitting display device including pixels commonly having initialization switching element and power supply element | |
| US7932881B2 (en) | Image display device and driver circuit therefor | |
| CN111243500B (en) | Display panel | |
| CN114072918A (en) | Display panel, driving method thereof and display device | |
| US20190197937A1 (en) | Display apparatus | |
| CN118435725A (en) | Display panel and display device | |
| US10998069B2 (en) | Shift register and electronic device having the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 1568 Jiugong Road, Jinshan Industrial Zone, Jinshan District, Shanghai, 201506 Applicant after: Shanghai Hehui optoelectronic Co.,Ltd. Address before: 1568 Jiugong Road, Jinshan District, Shanghai, 201506 Applicant before: EVERDISPLAY OPTRONICS (SHANGHAI) Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |