KR102588069B1 - Pixel circuit and display apparatus having the same - Google Patents

Abstract

The pixel circuit includes a first switching element, a second switching element, a light emitting element, and a timer circuit. The first switching element is connected to a first power voltage terminal. The second switching element is connected in series with the first switching element. The light emitting element is connected to the second switching element and a second power voltage terminal. The timer circuit is connected to the control electrode of the first switching element. The timer circuit includes an inverter and a coupling capacitor including a first end connected to the output terminal of the inverter and a second end connected to the control electrode of the first switching element.

Description

Pixel circuit and display device including same {PIXEL CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME}

The present invention relates to a pixel circuit and a display device including the same, and to a pixel circuit and a display device including the same that can improve display quality by reducing the turn-off transition time of a light-emitting element.

A conventional organic light emitting diode (OLED) display device adjusts the amount of light emitted from the organic light emitting diode by changing the size of the current density flowing through the organic light emitting diode to control the brightness of the pixel.

However, in a micro LED display device, changing the size of the current density causes a change in brightness, but there is a problem in that the emission wavelength changes somewhat. Therefore, in order to control the brightness of the pixel in a micro LED display device, it is necessary to fix the size of the current density and adjust the brightness by adjusting the emission time per frame.

The conventional micro LED pixel circuit for controlling the emission time has the disadvantage that the transition time is long when the micro LED transitions from the on state to the off state. If the transition time is long, not only is it difficult to accurately control the brightness, but also the magnitude of the current density changes continuously during the transition time, so a change in the emission wavelength may occur during the transition time.

In particular, at low gray levels where the emission time is short, the change in emission wavelength may be noticeable to the user, which may result in distortion of screen color.

Accordingly, the technical problem of the present invention was conceived from this point, and the purpose of the present invention is to provide a pixel circuit that can reduce the turn-off transition time of a light-emitting device.

Another object of the present invention is to provide a display device including the above pixel circuit.

A pixel circuit according to an embodiment for realizing the object of the present invention described above includes a first switching element, a second switching element, a light emitting element, and a timer circuit. The first switching element is connected to a first power voltage terminal. The second switching element is connected in series with the first switching element. The light emitting element is connected to the second switching element and a second power voltage terminal. The timer circuit is connected to the control electrode of the first switching element. The timer circuit includes an inverter and a coupling capacitor including a first end connected to the output terminal of the inverter and a second end connected to the control electrode of the first switching element.

In one embodiment of the present invention, the pixel circuit may further include a third switching element that applies an ON voltage to the control electrode of the first switching element in response to a third switching signal.

In one embodiment of the present invention, the storage capacitor may further include a first terminal connected to the first power voltage terminal and a second terminal connected to the control electrode of the first switching element.

In one embodiment of the present invention, the timer circuit includes a sweeping capacitor including a first terminal to which a sweeping signal is applied and a second terminal connected to the input terminal of the inverter, and a data voltage in response to a gate signal to the inverter. It may further include a timer switching element applied to the input terminal.

In one embodiment of the present invention, the inverter includes a control electrode connected to the input terminal of the inverter, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the inverter. It may include an inverter switching element and a second inverter switching element including a control electrode connected to the input terminal of the inverter, a first electrode connected to the output terminal of the inverter, and a second electrode connected to the second power voltage terminal. You can.

In one embodiment of the present invention, the first inverter switching element may be a P-type transistor, and the second inverter switching element may be an N-type transistor.

In one embodiment of the present invention, the inverter includes a control electrode connected to the input terminal of the inverter, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the inverter. It includes an inverter switching element and a second inverter switching element including a control electrode connected to the second power voltage terminal, a first electrode connected to the output terminal of the inverter, and a second electrode connected to the second power voltage terminal. can do.

In one embodiment of the present invention, the first inverter switching element and the second inverter switching element may be P-type transistors.

In one embodiment of the present invention, the inverter includes a control electrode connected to the first power voltage terminal, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the inverter. It includes a first inverter switching element and a second inverter switching element including a control electrode connected to the input terminal of the inverter, a first electrode connected to the output terminal of the inverter, and a second electrode connected to the second power voltage terminal. can do.

In one embodiment of the present invention, the first inverter switching element and the second inverter switching element may be N-type transistors.

In one embodiment of the present invention, the first switching element is connected to a control electrode connected to a first node, a first electrode connected to the first power voltage terminal, and a first electrode of the second switching element. It may include a second electrode. The second switching element may include a control electrode to which a second switching signal is applied, a first electrode connected to the second electrode of the first switching element, and a second electrode connected to the first electrode of the light-emitting element. You can. The light emitting device may include a first electrode connected to the second electrode of the second switching device and a second electrode connected to the second power voltage terminal. The pixel circuit includes a control electrode to which a third switching signal is applied, a third switching element including a first electrode to which an ON voltage is applied and a second electrode connected to the first node, and the first power voltage terminal. A storage capacitor including a first terminal connected to and a second terminal connected to the first node, a sweeping capacitor including a first terminal to which a sweeping signal is applied and a second terminal connected to the input terminal of the inverter, and a gate signal. It may further include a timer switching element including a control electrode to which a voltage is applied, a first electrode to which a data voltage is applied, and a second electrode connected to the input terminal of the inverter.

In one embodiment of the present invention, the gate signal may have a pulse at an activation level in a first section and maintain a deactivation level in a second section.

In one embodiment of the present invention, the third switching signal may maintain an activation level in a first section and an inactivation level in a second section.

In one embodiment of the present invention, the second switching signal may maintain an inactivation level in a first section and an activation level in a second section.

In one embodiment of the present invention, the sweeping signal may maintain a high level in the first section and gradually decrease in the second section.

A pixel circuit according to an embodiment for realizing the object of the present invention described above includes a first switching element, a second switching element, a light emitting element, and a timer circuit. The first switching element is connected to a first power voltage terminal. The second switching element is connected in series with the first switching element. The light emitting element is connected to the second switching element and a second power voltage terminal. The timer circuit is connected to the control electrode of the first switching element. The timer circuit includes a plurality of inverter stages and a coupling capacitor including a first end connected to the output terminal of the last inverter stage of the plurality of inverter stages and a second end connected to the control electrode of the first switching element. Includes.

In one embodiment of the present invention, the timer circuit includes a sweeping capacitor including a first stage to which a sweeping signal is applied and a second stage connected to the input terminal of the first inverter stage among the plurality of inverter stages, and a gate signal. It may further include a timer switching element that responds and applies a data voltage to the input terminal of the first inverter stage.

In one embodiment of the present invention, when the number of the plurality of inverter stages is odd, the sweeping signal may maintain a high level in the first section and gradually decrease in the second section.

In one embodiment of the present invention, when the number of the plurality of inverter stages is an even number, the sweeping signal may maintain a low level in the first section and gradually increase in the second section.

In one embodiment of the present invention, the timer circuit may include a first inverter stage and a second inverter stage. The first inverter stage includes a control electrode connected to the input terminal of the first inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the first inverter stage. An inverter switching element and a control electrode connected to the input terminal of the first inverter stage, a first electrode connected to the output terminal of the first inverter stage, and a second electrode connected to the second power voltage terminal. It may include an inverter switching element. The second inverter stage includes a control electrode connected to the input terminal of the second inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the second inverter stage. A fourth circuit comprising an inverter switching element and a control electrode connected to the input terminal of the second inverter stage, a first electrode connected to the output terminal of the second inverter stage, and a second electrode connected to the second power voltage terminal. It may include an inverter switching element.

In one embodiment of the present invention, the first inverter switching element and the third inverter switching element may be P-type transistors, and the second inverter switching element and the fourth inverter switching element may be N-type transistors.

In one embodiment of the present invention, the first inverter switching element may further include a feedback control electrode connected to the output terminal of the second inverter stage. The second inverter switching element may further include a feedback control electrode connected to the output terminal of the second inverter stage.

In one embodiment of the present invention, the timer circuit may include a first inverter stage and a second inverter stage. The first inverter stage includes a control electrode connected to the input terminal of the first inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the first inverter stage. A second inverter switching comprising an inverter switching element and a control electrode connected to the second power voltage terminal, a first electrode connected to the output terminal of the first inverter stage, and a second electrode connected to the second power voltage terminal. It may include elements. The second inverter stage includes a control electrode connected to the input terminal of the second inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the second inverter stage. A fourth inverter switching comprising an inverter switching element and a control electrode connected to the second power voltage terminal, a first electrode connected to the output terminal of the second inverter stage, and a second electrode connected to the second power voltage terminal. It may include elements.

In one embodiment of the present invention, the first inverter switching element, the second inverter switching element, the third inverter switching element, and the fourth inverter switching element may be P-type transistors.

In one embodiment of the present invention, the first inverter switching element may further include a feedback control electrode connected to the output terminal of the second inverter stage.

In one embodiment of the present invention, the timer circuit may include a first inverter stage and a second inverter stage. The first inverter stage includes a control electrode connected to the first power voltage terminal, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the first inverter stage. A second inverter switching comprising a switching element and a control electrode connected to the input terminal of the first inverter stage, a first electrode connected to the output terminal of the first inverter stage, and a second electrode connected to the second power voltage terminal. It may include elements. The second inverter stage is a third inverter including a control electrode connected to the first power voltage terminal, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the second inverter stage. A fourth inverter switching comprising a switching element and a control electrode connected to the input terminal of the second inverter stage, a first electrode connected to the output terminal of the second inverter stage, and a second electrode connected to the second power voltage terminal. It may include elements.

In one embodiment of the present invention, the first inverter switching element, the second inverter switching element, the third inverter switching element, and the fourth inverter switching element may be N-type transistors.

In one embodiment of the present invention, the second inverter switching element may further include a feedback control electrode connected to the output terminal of the second inverter stage.

In one embodiment of the present invention, when the last inverter stage among the plurality of inverter stages is the M-th inverter stage, at least one of the inverter switching elements of the M-1th inverter stage includes a feedback control electrode, The output terminal of the M-th inverter stage may be connected to the feedback control electrode of the inverter switching element of the M-1th inverter stage. M may be a natural number of 2 or more.

In one embodiment of the present invention, when the last inverter stage among the plurality of inverter stages is the M-th inverter stage, at least one of the inverter switching elements of the M-3 inverter stage includes a feedback control electrode, The output terminal of the M-th inverter stage may be connected to the feedback control electrode of the inverter switching element of the M-3 inverter stage. M may be a natural number of 4 or more.

A display device according to an embodiment for realizing the object of the present invention described above includes a display panel, a gate driver that outputs a gate signal to the pixel circuit of the display panel, and a data voltage that outputs a data voltage to the pixel circuit of the display panel. Includes a driving part. The pixel circuit displays an image based on the gate signal and the data voltage. The pixel circuit includes a first switching element, a second switching element, a light emitting element, and a timer circuit. The first switching element is connected to a first power voltage terminal. The second switching element is connected in series with the first switching element. The light emitting element is connected to the second switching element and a second power voltage terminal. The timer circuit is connected to the control electrode of the first switching element. The timer circuit includes an inverter and a coupling capacitor including a first end connected to the output terminal of the inverter and a second end connected to the control electrode of the first switching element.

A display device according to an embodiment for realizing the object of the present invention described above includes a display panel, a gate driver that outputs a gate signal to the pixel circuit of the display panel, and a data voltage that outputs a data voltage to the pixel circuit of the display panel. Includes a driving part. The pixel circuit displays an image based on the gate signal and the data voltage. The pixel circuit includes a first switching element, a second switching element, a light emitting element, and a timer circuit. The first switching element is connected to a first power voltage terminal. The second switching element is connected in series with the first switching element. The light emitting element is connected to the second switching element and a second power voltage terminal. The timer circuit is connected to the control electrode of the first switching element. The timer circuit includes a plurality of inverter stages and a coupling capacitor including a first end connected to the output terminal of the last inverter stage of the plurality of inverter stages and a second end connected to the control electrode of the first switching element. Includes.

According to such a pixel circuit and a display device including the pixel circuit, the timer circuit includes at least one inverter and a coupling capacitor, and the coupling capacitor is disposed between the output terminal of the inverter and the control electrode of the first switching element. Located in , the potential of the control electrode of the first switching element can also rapidly transition from the turn-on level to the turn-off level due to the coupling effect at the moment the output of the inverter rapidly transitions from low to high. .

Accordingly, the brightness of the pixel circuit can be accurately controlled, and changes in the emission wavelength during the transition time can be prevented. In particular, it is possible to prevent screen color distortion from occurring due to changes in the emission wavelength in low gray levels with a short emission time. As a result, the display quality of the display device can be improved.

Although micro LED displays are not currently commercialized, they are receiving great attention as next-generation displays. Micro LED displays have advantages such as high efficiency, high brightness, and long lifespan, and can be used in flexible displays, wearable devices, and head-mounted displays. However, micro LED has the problem that wavelength change, or color change, occurs due to current density. The present invention proposes a method to solve the wavelength change problem of micro LED display by improving the operation speed of the pixel circuit, thereby improving micro LED display. It can contribute to accelerating the commercialization of displays.

1 is a block diagram showing a display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of a pixel circuit of the display panel of FIG. 1.
FIG. 3 is a circuit diagram showing an example of a pixel circuit of the display panel of FIG. 1.
FIG. 4 is a circuit diagram showing an example of a pixel circuit of the display panel of FIG. 1.
FIG. 5 is a circuit diagram showing an example of a pixel circuit of the display panel of FIG. 1.
FIG. 6 is a timing diagram illustrating an example of signals applied to the pixel circuit of the display panel of FIG. 1.
FIG. 7 is a timing diagram illustrating an example of signals applied to the pixel circuit of the display panel of FIG. 1.
FIG. 8 is a circuit diagram showing an example of a pixel circuit of the display panel of FIG. 1.
FIG. 9 is a cross-sectional view showing a three-terminal switching element of the pixel circuit of FIG. 8.
FIG. 10 is a cross-sectional view showing a four-terminal switching element of the pixel circuit of FIG. 8.
FIG. 11 is a circuit diagram showing an example of a pixel circuit of the display panel of FIG. 1.
FIG. 12 is a circuit diagram showing an example of a pixel circuit of the display panel of FIG. 1.
FIG. 13 is a circuit diagram showing an example of a pixel circuit of the display panel of FIG. 1.
FIG. 14 is a circuit diagram showing an example of a pixel circuit of the display panel of FIG. 1.

Regarding the embodiments of the present invention disclosed in the text, specific structural and functional descriptions are merely illustrative for the purpose of explaining the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms. It should not be construed as limited to the embodiments described in.

Since the present invention can be subject to various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another component. For example, a first component may be referred to as a second component, and similarly, the second component may be referred to as a first component without departing from the scope of the present invention.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between. Other expressions that describe the relationship between components, such as "between" and "immediately between" or "neighboring" and "directly adjacent to" should be interpreted similarly.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as “comprise” or “have” are intended to designate the presence of a described feature, number, step, operation, component, part, or combination thereof, and one or more other features or numbers, It should be understood that this does not exclude in advance the possibility of the presence or addition of steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless clearly defined in the present application, should not be interpreted as having an ideal or excessively formal meaning. .

Meanwhile, if an embodiment can be implemented differently, functions or operations specified within a specific block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, or the blocks may be performed in reverse depending on the functions or operations involved.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions for the same components are omitted.

1 is a block diagram showing a display device according to an embodiment of the present invention.

Referring to FIG. 1, the display device includes a display panel 100 and a display panel driver. The display panel driver may include a drive control unit 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a voltage generator 600.

For example, the drive control unit 200 and the data driver 500 may be formed integrally. For example, the drive control unit 200, the gamma reference voltage generator 400, and the data driver 500 may be formed as one body. For example, the drive control unit 200, the gamma reference voltage generator 400, the data driver 500, and the voltage generator 600 may be formed as one body. A driving module in which at least the driving control unit 200 and the data driving unit 500 are integrated can be called a timing controller embedded data driver (TED).

The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels electrically connected to each of the gate lines GL and the data lines DL. Includes P). The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 that intersects the first direction D1.

The driving control unit 200 may receive input image data (IMG) and input control signal (CONT) from an external device. For example, the input image data (IMG) may include red image data, green image data, and blue image data. The input image data (IMG) may include white image data. The input image data (IMG) may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

The driving control unit 200 generates a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), and a third control signal (CONT3) based on the input image data (IMG) and the input control signal (CONT). 4 Control signal (CONT4) and data signal (DATA) can be generated.

The drive control unit 200 may generate the first control signal (CONT1) for controlling the operation of the gate driver 300 based on the input control signal (CONT) and output it to the gate driver 300. there is. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

The drive control unit 200 may generate the second control signal (CONT2) for controlling the operation of the data driver 500 based on the input control signal (CONT) and output it to the data driver 500. there is. The second control signal CONT2 may include a horizontal start signal and a load signal.

The driving control unit 200 generates a data signal (DATA) based on the input image data (IMG). The driving control unit 200 may output the data signal DATA to the data driving unit 500.

The drive control unit 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and generates the gamma reference voltage generator ( 400).

The drive control unit 200 generates the fourth control signal (CONT4) to control the operation of the voltage generator 600 based on the input control signal (CONT) and outputs it to the voltage generator 600. can do.

The gate driver 300 may generate gate signals for driving the gate lines GL in response to the first control signal CONT1 received from the drive controller 200. The gate driver 300 may output the gate signals to the gate lines GL. For example, the gate driver 300 may sequentially output the gate signals to the gate lines GL. For example, the gate driver 300 may be mounted on the display panel 100. For example, the gate driver 300 may be integrated on the display panel 100.

The gamma reference voltage generator 400 may generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the drive control unit 200. The gamma reference voltage generator 400 may provide the gamma reference voltage (VGREF) to the data driver 500. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

In one embodiment of the present invention, the gamma reference voltage generator 400 may be disposed within the drive control unit 200 or within the data driver 500.

The data driver 500 receives the second control signal (CONT2) and the data signal (DATA) from the drive controller 200, and generates the gamma reference voltage (VGREF) from the gamma reference voltage generator 400. can be input. The data driver 500 may convert the data signal DATA into an analog data voltage using the gamma reference voltage VGREF. The data driver 500 may output the data voltage to the data line DL.

The voltage generator 600 may receive the fourth control signal CONT4 from the drive control unit 200. The voltage generator 600 may generate a power supply voltage of the display panel 100 and provide the power voltage to the display panel 100 .

FIG. 2 is a circuit diagram showing an example of the pixel circuit P of the display panel 100 of FIG. 1 .

1 and 2, the pixel circuit (P) includes a first switching element (TCC) connected to a first power voltage terminal to which a first power voltage (VDD) is applied, and the first switching element (TCC) A second switching element (TEMI) connected in series, a light emitting element (EE) connected to a second power voltage terminal to which the second switching element (TEMI) and the second power voltage (VSS) are applied, and the first switching element It may include a timer circuit connected to the control electrode of the device (TCC).

The timer circuit includes an inverter (INV), a first terminal connected to the output terminal (NI) of the inverter (INV), and a second terminal connected to the control electrode (N1) of the first switching element (TCC). It may include a coupling capacitor (C2).

The pixel circuit (P) has a third switching element (TSCC) that applies an ON voltage (VON) to the control electrode (N1) of the first switching element (TCC) in response to a third switching signal (VSCC). ) may further be included.

In addition, the pixel circuit (P) includes a storage capacitor (C1) including a first end connected to the first power voltage terminal and a second end connected to the control electrode (N1) of the first switching element (TCC). ) may further be included.

The timer circuit responds to the gate signal (VSPWM) and a sweeping capacitor (CSWEEP) including a first stage to which the sweeping signal (VSWEEP) is applied and a second stage connected to the input terminal (N2) of the inverter (INV). It may further include a timer switching element (TSPWM) that applies the data voltage (VDATA) to the input terminal (N2) of the inverter (INV).

To describe the pixel circuit in more detail, the first switching element (TCC) includes a control electrode connected to the first node (N1), a first electrode connected to the first power voltage terminal, and the second switching element. (TEMI) may include a second electrode connected to the first electrode.

The second switching element (TEMI) includes a control electrode to which the second switching signal (VEMI) is applied, a first electrode connected to the second electrode of the first switching element (TCC), and the light emitting element (EE). It may include a second electrode connected to the first electrode.

The light emitting element EE may include a first electrode connected to the second electrode of the second switching element TEMI and a second electrode connected to the second power voltage terminal.

The third switching element (TSCC) is connected to a control electrode to which the third switching signal (VSCC) is applied, a first electrode to which the ON voltage (VON) is applied, and the first node (N1). It may include 2 electrodes.

The timer switching element (TSPWM) includes a control electrode to which the gate signal (VSPWM) is applied, a first electrode to which the data voltage (VDATA) is applied, and a second electrode connected to the input terminal (N2) of the inverter (INV). may include.

The inverter (INV) may include the first inverter switching element (T11) and the second inverter switching element (T12) of FIG. 5, and the first inverter switching element (T11) and the second inverter switching element (T12) of FIG. 11 ( T12), and may include the first inverter switching element T11 and the second inverter switching element T12 of FIG. 13. This will be described later with reference to FIGS. 5, 11, and 13.

In this embodiment, the light emitting element EE may be a micro LED. Micro LED displays, which attach inorganic LED elements with a chip size smaller than 100㎛ to the backplane, a display substrate, using a transfer method and use these inorganic LED elements as pixels, have recently been attracting a lot of attention. Since inorganic LED devices are technologically quite mature, if a micro LED display is successfully implemented, it will have many advantages in terms of image quality, efficiency, and lifespan. Additionally, if a micro LED display is implemented on a plastic-based backplane, it can be applied to flexible displays, wearable displays, and head-mounted displays. In order to successfully implement a micro LED display, it is necessary to secure stable transfer technology and develop an active matrix backplane.

Although active matrix backplane technology has already been established in OLED displays, there are problems with using it as a backplane for micro LED displays. In OLED displays, brightness is controlled by adjusting the size of the current density flowing through the OLED element to express the gradation of the pixel. However, if the current density flowing through the inorganic LED device changes, the central wavelength of the emitted light may shift. Therefore, when the brightness of a micro LED display is adjusted by adjusting the size of the current density flowing through the device as in the current OLED display, a problem occurs in which the color coordinates of the three primary colors, RGB and RGB, shift slightly depending on the brightness of the pixel. To solve this problem, the size of the instantaneous current density flowing through the inorganic LED is kept constant, but the time when the current flows through the inorganic LED each frame is adjusted to control brightness, that is, a method of expressing gradation by adjusting the emission time is used. It may be necessary.

FIG. 3 is a circuit diagram showing an example of the pixel circuit P of the display panel 100 of FIG. 1 . FIG. 4 is a circuit diagram showing an example of the pixel circuit P of the display panel 100 of FIG. 1 .

The pixel circuit of FIG. 3 is substantially the same as the pixel circuit of FIG. 2, except that the timer circuit includes two inverter stages (INV1 and INV2), and the pixel circuit of FIG. 4 includes the timer circuit having M inverter stages (INV1, INV2). Since it is substantially the same as the pixel circuit of FIG. 2 except that it includes INV1, INV2, ?, INVM), the same reference numbers are used for the same or similar components, and overlapping descriptions are omitted.

In FIG. 3, the output terminal of the first inverter stage (INV1) is indicated as NI1, and the output terminal of the second inverter stage (INV2) is indicated as NI2.

In FIG. 4, the output terminal of the first inverter stage (INV1) is denoted as NI1, the output terminal of the second inverter stage (INV2) is denoted as NI2, and the output terminal of the M-th inverter stage (INVM) is denoted as NIM.

FIG. 5 is a circuit diagram showing an example of the pixel circuit P of the display panel 100 of FIG. 1 .

The pixel circuit of FIG. 5 illustrates that the timer circuit includes two inverter stages (INV1 and INV2) as shown in FIG. 3. Except that the pixel circuit of FIG. 5 illustrates that the timer circuit includes two inverter stages (INV1 and INV2) as shown in FIG. 3, and each inverter stage includes two inverter switching elements connected in series, Since it is substantially the same as the pixel circuit of FIG. 2, the same reference numerals are used for the same or similar components, and overlapping descriptions are omitted.

The timer circuit may include a first inverter stage and a second inverter stage connected in series.

The first inverter stage includes a control electrode connected to the input terminal (N2) of the first inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal (NI1) of the first inverter stage. A first inverter switching element (T11) including an electrode, a control electrode connected to the input terminal (N2) of the first inverter stage, a first electrode connected to the output terminal (NI1) of the first inverter stage, and 2 It may include a second inverter switching element T12 including a second electrode connected to the power voltage terminal.

The second inverter stage includes a control electrode connected to the input terminal (NI1) of the second inverter stage, which is the same as the output terminal (NI1) of the first inverter stage, a first electrode connected to the first power voltage terminal, and the first electrode. 2 A third inverter switching element (T21) including a second electrode connected to the output terminal (NI2) of the inverter stage, a control electrode connected to the input terminal (NI1) of the second inverter stage, and the second inverter stage. It may include a fourth inverter switching element T22 including a first electrode connected to the output terminal NI2 and a second electrode connected to the second power voltage terminal.

In this embodiment, each inverter stage may be configured as a CMOS inverter stage. The first inverter switching element (T11) and the third inverter switching element (T21) may be P-type transistors, and the second inverter switching element (T12) and the fourth inverter switching element (T22) may be N-type transistors. there is.

FIG. 6 is a timing diagram illustrating an example of signals applied to the pixel circuit P of the display panel 100 of FIG. 1 . FIG. 7 is a timing diagram illustrating an example of signals applied to the pixel circuit P of the display panel 100 of FIG. 1 .

6 and 7 show examples of signals applied to the pixel circuit P during one frame period FR.

As shown in FIGS. 6 and 7, one frame period (FR) can be divided into a first section (TP1) corresponding to the first half and a second section (TP2) corresponding to the second half.

FIGS. 6 and 7 are identical to each other except for the waveform of the sweeping signal (VSWEEP). When the number of the plurality of inverter stages is odd, the sweeping signal VSWEEP may maintain a high level in the first section TP1 and gradually decrease in the second section TP2, as shown in FIG. 7 . On the other hand, when the number of the plurality of inverter stages is an even number, the sweeping signal (VSWEEP) maintains a low level in the first section (TP1) and gradually increases in the second section (TP2), as shown in FIG. 6. You can.

The gate signal VSPWM may have an activation level pulse in the first section TP1 and maintain a deactivation level in the second section TP2. Here, since the timer switching element (TSPWM) receiving the gate signal (VSPWM) is a P-type transistor, the activation level of the gate signal (VSPWM) may be a low level and the deactivation level may be a high level.

In the first section TP1, N gate signals (VSPWM[1] to VSPWM[N]) are sequentially scanned, and the data voltage VDATA can be written to the pixel rows of the display panel 100. there is. The section corresponding to one gate signal can be called 1 horizontal section (1H). Additionally, the first section TP1 may be called a writing section or a programming section. Additionally, the second section TP2 may be called a light emission section or an emission section.

The third switching signal VSCC may maintain an activated level in the first section TP1 and a deactivated level in the second section TP2. Here, the third switching element (TSCC) receiving the third switching signal (VSCC) is a P-type transistor, so the activation level of the third switching signal (VSCC) is a low level and the deactivation level is a high level. It can be.

The second switching signal VEMI may maintain an inactive level in the first section TP1 and an active level in the second section TP2. Here, the second switching element (TEMI) receiving the second switching signal (VEMI) is a P-type transistor, so the activation level of the second switching signal (VEMI) is a low level and the deactivation level is a high level. It can be.

Referring to the circuit diagram of FIG. 5 and the timing diagram of FIG. 6, the operation of the pixel circuit P will be described in detail as follows.

In the first period (TP1), the third switching signal (VSCC) first turns on the third switching element (TSCC) to turn on the first switching element (TCC). VON) is stored in the storage capacitor C1. Next, the timer switching element (TSPWM) is turned on by the gate signal (VSPWM) applied to the pixel circuit (P) of FIG. 5 among the N gate signals (VSPWM[1] to VSPWM[N]), and the data A voltage (VDATA) is stored in the sweeping capacitor (CSWEEP) to be used as the input potential of the first inverter stage. Here, N means the number of pixel rows. In this case, N pixels are connected to one data line (DL), and a gate signal (VSPWM), which is N sequential pulses, is required to deliver a data voltage to each of the N pixels through one data line (DL). Each pixel must have one timer switching element (TSPWM) that acts as a switch.

The subsequent emission time of the micro LED (EE) can be determined by the height of the potential stored in the sweeping capacitor (CSWEEP). In the second section (TP2), the second switching signal (VEMI) turns on the second switching element (TEMI) so that a certain amount of current determined by the first switching element (TCC) flows through the micro LED (EE). flows through, and the pixel begins to emit light. At the same time, the sweeping signal (VSWEEP) begins to rise, raising the input potential of the first inverter stage through coupling. The time at which the output of the first inverter stage begins to change from high to low varies depending on the data voltage (VDATA), that is, the initial potential value of the input terminal (N2) of the first inverter stage. When the output of the first inverter stage begins to change from high to low, the remaining inverter stages also change their output, and the output of the last inverter stage switches from low to high through a coupling effect through the coupling capacitor (C2). The gate potential of the first switching element (TCC) is raised so that the first switching element (TCC) is turned off. This completes the emission of one frame, and when one frame period (FR) ends, the operation of the next frame continues to repeat in the manner described above.

According to this embodiment, the timer circuit includes at least one inverter (INV) and a coupling capacitor (C2), and the coupling capacitor (C2) controls the output terminal of the inverter and the first switching element (TCC). Located between the electrodes N1, the moment the output of the inverter INV suddenly transitions from low to high, the potential of the control electrode N1 of the first switching element TCC also rapidly changes due to the coupling effect. It allows transition from the turn-on level to the turn-off level.

Accordingly, the brightness of the pixel circuit can be accurately controlled, and changes in the emission wavelength during the transition time can be prevented. In particular, it is possible to prevent screen color distortion from occurring due to changes in the emission wavelength in low gray levels with a short emission time. As a result, the display quality of the display device can be improved.

Although micro LED displays are not currently commercialized, they are receiving great attention as next-generation displays. Micro LED displays have advantages such as high efficiency, high brightness, and long lifespan, and can be used in flexible displays, wearable devices, and head-mounted displays. However, micro LED has the problem that wavelength change, or color change, occurs due to current density. The present invention proposes a method to solve the wavelength change problem of micro LED display by improving the operation speed of the pixel circuit, thereby improving micro LED display. It can contribute to accelerating the commercialization of displays.

FIG. 8 is a circuit diagram showing an example of the pixel circuit P of the display panel 100 of FIG. 1. FIG. 9 is a cross-sectional view showing a three-terminal switching element of the pixel circuit P of FIG. 8. FIG. 10 is a cross-sectional view showing a four-terminal switching element of the pixel circuit P of FIG. 8.

The pixel circuit of FIG. 8 further includes a feedback control electrode where the first inverter switching element T11 and the second inverter switching element T12 of the first inverter stage are connected to the output terminal NI2 of the second inverter stage. Except for this, since it is substantially the same as the pixel circuit of FIG. 5, the same reference numerals are used for the same or similar components, and overlapping descriptions are omitted.

8 to 10, the timer circuit may include a first inverter stage and a second inverter stage connected in series.

The first inverter stage includes a control electrode connected to the input terminal (N2) of the first inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal (NI1) of the first inverter stage. A first inverter switching element (T11) including an electrode, a control electrode connected to the input terminal (N2) of the first inverter stage, a first electrode connected to the output terminal (NI1) of the first inverter stage, and 2 It may include a second inverter switching element T12 including a second electrode connected to the power voltage terminal.

The second inverter stage includes a control electrode connected to the input terminal (NI1) of the second inverter stage, which is the same as the output terminal (NI1) of the first inverter stage, a first electrode connected to the first power voltage terminal, and the first electrode. 2 A third inverter switching element (T21) including a second electrode connected to the output terminal (NI2) of the inverter stage, a control electrode connected to the input terminal (NI1) of the second inverter stage, and the second inverter stage. It may include a fourth inverter switching element T22 including a first electrode connected to the output terminal NI2 and a second electrode connected to the second power voltage terminal.

In this embodiment, each inverter stage may be configured as a CMOS inverter stage. The first inverter switching element (T11) and the third inverter switching element (T21) may be P-type transistors, and the second inverter switching element (T12) and the fourth inverter switching element (T22) may be N-type transistors. there is.

In this embodiment, the first inverter switching element (T11) further includes a feedback control electrode connected to the output terminal (NI2) of the second inverter stage, and the second inverter switching element (T12) is connected to the second inverter stage. It may further include a feedback control electrode connected to the output terminal (NI2) of the inverter stage.

That is, the first inverter switching element (T11) and the second inverter switching element (T12) may be four-terminal switching elements. On the other hand, switching elements in the pixel circuit P, excluding the first inverter switching element T11 and the second inverter switching element T12, may be three-terminal switching elements.

Figure 9 shows a cross-sectional view of a three-terminal switching element. For example, an active layer (AL) may be disposed on the substrate (G), an insulating layer (INS) may be disposed on the active layer (AL), and a gate electrode may be disposed on the insulating layer (INS). (GE) may be disposed, and a gate insulating layer (GI) may be disposed on the gate electrode (GE). A source electrode (SE) passing through the gate insulating layer (GI) and the insulating layer (INS) and connected to the source region on the first side of the active layer (AL) may be disposed on the gate insulating layer (GI). and a drain electrode DE that passes through the gate insulating layer GI and the insulating layer INS and is connected to the drain region on the second side of the active layer AL is disposed on the gate insulating layer GI. It can be. The control electrode of the three-terminal switching elements may be the gate electrode (GE) of FIG. 9, and the first electrode and the second electrode of the three-terminal switching elements may be the source electrode (SE) and the drain electrode (SE) of FIG. DE) may be.

Figure 10 shows a cross-sectional view of a 4-terminal switching element. For example, a feedback gate electrode (FGE) is disposed on the substrate (G), a first gate insulating layer (GI1) is disposed on the feedback gate electrode (FGE), and the first gate insulating layer (GI1) An active layer (AL) may be disposed on the active layer (AL), an insulating layer (INS) may be disposed on the active layer (AL), and a main gate electrode (MGE) may be disposed on the insulating layer (INS), A second gate insulating layer (GI2) may be disposed on the main gate electrode (MGE). A source electrode (SE) passing through the second gate insulating layer (GI2) and the insulating layer (INS) on the second gate insulating layer (GI2) and connected to the source region on the first side of the active layer (AL) may be disposed on the second gate insulating layer GI2, passing through the second gate insulating layer GI2 and the insulating layer INS, and connected to the drain region on the second side of the active layer AL. A drain electrode DE may be disposed. The control electrode of the four-terminal switching elements may be the main gate electrode (MGE) of FIG. 10, and the feedback control electrode may be the feedback gate electrode (FGE) of FIG. 10. The first electrode and the second electrode of the four-terminal switching elements may be the source electrode (SE) and the drain electrode (DE) of FIG. 10.

For example, when the last inverter stage among the plurality of inverter stages is the M-th inverter stage, at least one of the inverter switching elements of the M-1th inverter stage includes a feedback control electrode, and the M-th inverter stage includes a feedback control electrode. The output terminal may be connected to the feedback control electrode of the inverter switching element of the M-1th inverter stage. Here, M is a natural number of 2 or more.

For example, when the last inverter stage among the plurality of inverter stages is the M-th inverter stage, at least one of the inverter switching elements of the M-3 inverter stage includes a feedback control electrode, and the The output terminal may be connected to the feedback control electrode of the inverter switching element of the M-3 inverter stage. Here, M is a natural number of 4 or more.

For example, when the last inverter stage among the plurality of inverter stages is the M-th inverter stage, at least one of the inverter switching elements of the M-5th inverter stage includes a feedback control electrode, and the The output terminal may be connected to the feedback control electrode of the inverter switching element of the M-5th inverter stage. Here, M is a natural number of 6 or more.

In this embodiment, a 4-terminal switching element with a feedback gate structure is used, and a shorter transition time can be realized by feeding back the signal from the final output stage of the timer circuit to the feedback gate of the transistor that constitutes the preceding inverter stage.

The reason why faster inverter operation is achieved by feeding back the signal from the final output stage of the timer circuit is as follows. Generally, the rate of change of the output signal is higher than the rate of change of the signal input to the inverter. Therefore, when multiple inverter stages are connected in series, the rate of change of the output signal of the final inverter stage becomes higher than the rate of change of the signal input to the first inverter stage. In one inverter, when the input changes from low to high, the output changes in the opposite direction to the input, that is, from high to low, but when multiple inverter stages are connected in series, the direction of change of the output of the final inverter stage and that of the preceding inverter stage There must be a stage where the direction of change of the input matches.

Therefore, coupling the output of the final inverter stage to a preceding inverter stage whose input change direction matches the same results in increasing the rate of change of the input of the preceding inverter stage. Ultimately, the rate of change of output of the final inverter stage becomes higher than when coupling is not used.

Here, as a method of coupling, the structure of the transistor constituting the inverter stage is adopted as a double gate structure. An input signal with a relatively low change rate is applied to the main gate electrode (MGE), but a feedback signal with a higher change rate is applied to the feedback gate electrode (FGE), thereby inducing a faster output change of this preceding inverter stage.

In this embodiment, the output of the final inverter stage may be fed back to all preceding inverter stages whose change direction matches the change direction of the input signal, or may be fed back only to a specific inverter stage. An example of what is referred to herein as a specific inverter stage could be the first inverter stage.

According to this embodiment, the timer circuit includes at least one inverter (INV) and a coupling capacitor (C2), and the coupling capacitor (C2) controls the output terminal of the inverter and the first switching element (TCC). Located between the electrodes N1, the moment the output of the inverter INV suddenly transitions from low to high, the potential of the control electrode N1 of the first switching element TCC also rapidly changes due to the coupling effect. It allows transition from the turn-on level to the turn-off level.

Accordingly, the brightness of the pixel circuit can be accurately controlled, and changes in the emission wavelength during the transition time can be prevented. In particular, it is possible to prevent screen color distortion from occurring due to changes in the emission wavelength in low gray levels with a short emission time. As a result, the display quality of the display device can be improved.

Although micro LED displays are not currently commercialized, they are receiving great attention as next-generation displays. Micro LED displays have advantages such as high efficiency, high brightness, and long lifespan, and can be used in flexible displays, wearable devices, and head-mounted displays. However, micro LED has the problem that wavelength change, or color change, occurs due to current density. The present invention proposes a method to solve the wavelength change problem of micro LED display by improving the operation speed of the pixel circuit, thereby improving micro LED display. It can contribute to accelerating the commercialization of displays.

In addition, in order to further shorten the transition time, a double gate structure rather than a single gate structure is adopted as the structure of the transistor constituting the inverter, and the feedback gate electrode added in addition to the main gate electrode contains the signal generated in the final inverter stage of the timer circuit. A feedback signal can be applied. By applying the feedback signal to the feedback gate electrode of the preceding inverter stage, faster inverter operation can be achieved.

FIG. 11 is a circuit diagram showing an example of the pixel circuit P of the display panel 100 of FIG. 1 .

Except that the pixel circuit of FIG. 11 illustrates that the timer circuit includes two inverter stages (INV1 and INV2) as shown in FIG. 3, and each inverter stage includes two inverter switching elements connected in series, Since it is substantially the same as the pixel circuit of FIG. 2, the same reference numerals are used for the same or similar components, and overlapping descriptions are omitted.

The timer circuit may include a first inverter stage and a second inverter stage connected in series.

The first inverter stage includes a control electrode connected to the input terminal (N2) of the first inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal (NI1) of the first inverter stage. A first inverter switching element T11 including an electrode, a control electrode connected to the second power voltage terminal, a first electrode connected to the output terminal NI1 of the first inverter stage, and a control electrode connected to the second power voltage terminal. It may include a second inverter switching element T12 including a connected second electrode.

The second inverter stage includes a control electrode connected to the input terminal (NI1) of the second inverter stage, which is the same as the output terminal (NI1) of the first inverter stage, a first electrode connected to the first power voltage terminal, and the first electrode. 2 A third inverter switching element (T21) including a second electrode connected to the output terminal (NI2) of the inverter stage, a control electrode connected to the second power voltage terminal, and a control electrode connected to the output terminal (NI2) of the second inverter stage. It may include a fourth inverter switching element T22 including a first electrode connected to the first electrode and a second electrode connected to the second power voltage terminal.

In this embodiment, each inverter stage may be configured as a PMOS inverter stage including only P-type transistors. The first inverter switching element (T11), the second inverter switching element (T12), the third inverter switching element (T21), and the fourth inverter switching element (T22) may be P-type transistors.

Comparing the pixel circuit of FIG. 11 with FIG. 5, in the CMOS inverter stage of FIG. 5, N-type transistors (T12, T22 in FIG. 5) are replaced with diode-connected P-type transistors (T12, T22 in FIG. 11).

FIG. 12 is a circuit diagram showing an example of the pixel circuit P of the display panel 100 of FIG. 1.

The pixel circuit of FIG. 12 is similar to the pixel circuit of FIG. 11, except that the first inverter switching element T11 of the first inverter stage further includes a feedback control electrode connected to the output terminal NI2 of the second inverter stage. Since they are substantially the same, the same reference numbers are used for identical or similar components, and overlapping descriptions are omitted.

Referring to FIG. 12, the first inverter switching element T11 of the first inverter stage may further include a feedback control electrode connected to the output terminal NI2 of the second inverter stage.

According to this embodiment, the timer circuit includes at least one inverter (INV) and a coupling capacitor (C2), and the coupling capacitor (C2) controls the output terminal of the inverter and the first switching element (TCC). Located between the electrodes N1, the moment the output of the inverter INV suddenly transitions from low to high, the potential of the control electrode N1 of the first switching element TCC also rapidly changes due to the coupling effect. It allows transition from the turn-on level to the turn-off level.

Accordingly, the brightness of the pixel circuit can be accurately controlled, and changes in the emission wavelength during the transition time can be prevented. In particular, it is possible to prevent screen color distortion from occurring due to changes in the emission wavelength in low gray levels with a short emission time. As a result, the display quality of the display device can be improved.

Although micro LED displays are not currently commercialized, they are receiving great attention as next-generation displays. Micro LED displays have advantages such as high efficiency, high brightness, and long lifespan, and can be used in flexible displays, wearable devices, and head-mounted displays. However, micro LED has the problem that wavelength change, or color change, occurs due to current density. The present invention proposes a method to solve the wavelength change problem of micro LED display by improving the operation speed of the pixel circuit, thereby improving micro LED display. It can contribute to accelerating the commercialization of displays.

In addition, in order to further shorten the transition time, a double gate structure rather than a single gate structure is adopted as the structure of the transistor constituting the inverter, and the feedback gate electrode added in addition to the main gate electrode contains the signal generated in the final inverter stage of the timer circuit. A feedback signal can be applied. By applying the feedback signal to the feedback gate electrode of the preceding inverter stage, faster inverter operation can be achieved.

FIG. 13 is a circuit diagram showing an example of the pixel circuit P of the display panel 100 of FIG. 1.

Except that the pixel circuit of FIG. 13 illustrates that the timer circuit includes two inverter stages (INV1 and INV2) as shown in FIG. 3, and each inverter stage includes two inverter switching elements connected in series, Since it is substantially the same as the pixel circuit of FIG. 2, the same reference numerals are used for the same or similar components, and overlapping descriptions are omitted.

The timer circuit may include a first inverter stage and a second inverter stage connected in series.

The first inverter stage includes a control electrode connected to the first power voltage terminal, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal (NI1) of the first inverter stage. a first inverter switching element (T11) and a control electrode connected to the input terminal (N2) of the first inverter stage, a first electrode connected to the output terminal (NI1) of the first inverter stage, and the second power supply voltage terminal. It may include a second inverter switching element T12 including a second electrode connected to .

The second inverter stage includes a control electrode connected to the first power voltage terminal, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal NI2 of the second inverter stage. a third inverter switching element (T21) and a control electrode connected to the input terminal (NI1) of the second inverter stage, which is the same as the output terminal (NI1) of the first inverter stage, and the output terminal (NI2) of the second inverter stage. It may include a fourth inverter switching element T22 including a first electrode connected to and a second electrode connected to the second power voltage terminal.

In this embodiment, each inverter stage may be configured as an NMOS inverter stage including only N-type transistors. The first inverter switching element (T11), the second inverter switching element (T12), the third inverter switching element (T21), and the fourth inverter switching element (T22) may be N-type transistors.

Comparing the pixel circuit of FIG. 13 with FIG. 5, in the CMOS inverter stage of FIG. 5, the P-type transistors (T11 and T21 in FIG. 5) are replaced with diode-connected N-type transistors (T11 and T21 in FIG. 13).

FIG. 14 is a circuit diagram showing an example of the pixel circuit P of the display panel 100 of FIG. 1.

The pixel circuit of FIG. 14 is similar to the pixel circuit of FIG. 13, except that the second inverter switching element T12 of the first inverter stage further includes a feedback control electrode connected to the output terminal NI2 of the second inverter stage. Since they are substantially the same, the same reference numbers are used for identical or similar components, and overlapping descriptions are omitted.

Referring to FIG. 14, the second inverter switching element T12 of the first inverter stage may further include a feedback control electrode connected to the output terminal NI2 of the second inverter stage.

According to this embodiment, the timer circuit includes at least one inverter (INV) and a coupling capacitor (C2), and the coupling capacitor (C2) controls the output terminal of the inverter and the first switching element (TCC). Located between the electrodes N1, the moment the output of the inverter INV suddenly transitions from low to high, the potential of the control electrode N1 of the first switching element TCC also rapidly changes due to the coupling effect. It allows transition from the turn-on level to the turn-off level.

Accordingly, the brightness of the pixel circuit can be accurately controlled, and changes in the emission wavelength during the transition time can be prevented. In particular, it is possible to prevent screen color distortion from occurring due to changes in the emission wavelength in low gray levels with a short emission time. As a result, the display quality of the display device can be improved.

Although micro LED displays are not currently commercialized, they are receiving great attention as next-generation displays. Micro LED displays have advantages such as high efficiency, high brightness, and long lifespan, and can be used in flexible displays, wearable devices, and head-mounted displays. However, micro LED has the problem that wavelength change, or color change, occurs due to current density. The present invention proposes a method to solve the wavelength change problem of micro LED display by improving the operation speed of the pixel circuit, thereby improving micro LED display. It can contribute to accelerating the commercialization of displays.

In addition, in order to further shorten the transition time, a double gate structure rather than a single gate structure is adopted as the structure of the transistor constituting the inverter, and the feedback gate electrode added in addition to the main gate electrode contains the signal generated in the final inverter stage of the timer circuit. A feedback signal can be applied. By applying the feedback signal to the feedback gate electrode of the preceding inverter stage, faster inverter operation can be achieved.

According to the pixel circuit and display device according to the present invention described above, it will contribute to improving the display quality of the display device and accelerating the commercialization of micro LED displays that can be used in next-generation displays such as flexible displays, wearable devices, and head-mounted displays. You can.

Although the description has been made with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will be able to.

100: display panel 200: driving control unit
300: Gate driver 400: Gamma reference voltage generator
500: data driver 600: voltage generator

Claims (32)

delete delete delete a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit is,
inverter;
a coupling capacitor including a first end connected to the output terminal of the inverter and a second end connected to the control electrode of the first switching element;
A sweeping capacitor including a first terminal to which a sweeping signal is applied and a second terminal connected to the input terminal of the inverter; and
A pixel circuit comprising a timer switching element that applies a data voltage to the input terminal of the inverter in response to a gate signal. delete delete delete a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit includes an inverter and a coupling capacitor including a first end connected to an output terminal of the inverter and a second end connected to the control electrode of the first switching element,
The inverter is,
a first inverter switching element including a control electrode connected to the input terminal of the inverter, a first electrode connected to the first power voltage terminal, and a second electrode connected to an output terminal of the inverter; and
A second inverter switching element including a control electrode connected to the second power voltage terminal, a first electrode connected to the output terminal of the inverter, and a second electrode connected to the second power voltage terminal,
A pixel circuit, wherein the first inverter switching element and the second inverter switching element are P-type transistors. a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit includes an inverter and a coupling capacitor including a first end connected to an output terminal of the inverter and a second end connected to the control electrode of the first switching element,
The inverter is
a first inverter switching element including a control electrode connected to the first power voltage terminal, a first electrode connected to the first power voltage terminal, and a second electrode connected to an output terminal of the inverter; and
A pixel comprising a second inverter switching element including a control electrode connected to the input terminal of the inverter, a first electrode connected to the output terminal of the inverter, and a second electrode connected to the second power voltage terminal. Circuit. The pixel circuit of claim 9, wherein the first inverter switching element and the second inverter switching element are N-type transistors. delete delete delete delete delete delete a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit is,
a plurality of inverter stages;
a coupling capacitor including a first end connected to the output terminal of the last inverter stage among the plurality of inverter stages and a second end connected to the control electrode of the first switching element;
a sweeping capacitor including a first stage to which a sweeping signal is applied and a second stage connected to an input terminal of a first inverter stage among the plurality of inverter stages; and
A pixel circuit comprising a timer switching element that applies a data voltage to the input terminal of the first inverter stage in response to a gate signal. The pixel circuit of claim 17, wherein when the number of the plurality of inverter stages is odd, the sweeping signal maintains a high level in a first section and gradually decreases in a second section. The pixel circuit of claim 17, wherein when the number of the plurality of inverter stages is an even number, the sweeping signal maintains a low level in a first section and gradually increases in a second section. a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit includes a plurality of inverter stages and a coupling capacitor including a first end connected to the output terminal of the last inverter stage of the plurality of inverter stages and a second end connected to the control electrode of the first switching element. Including,
The timer circuit includes a first inverter stage and a second inverter stage,
The first inverter stage is
a first inverter switching element including a control electrode connected to an input terminal of the first inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to an output terminal of the first inverter stage; and
A second inverter switching element including a control electrode connected to the input terminal of the first inverter stage, a first electrode connected to the output terminal of the first inverter stage, and a second electrode connected to the second power voltage terminal. Includes,
The second inverter stage is
a third inverter switching element including a control electrode connected to the input terminal of the second inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the second inverter stage; and
A fourth inverter switching element including a control electrode connected to the input terminal of the second inverter stage, a first electrode connected to the output terminal of the second inverter stage, and a second electrode connected to the second power voltage terminal. A pixel circuit comprising: The pixel circuit of claim 20, wherein the first inverter switching element and the third inverter switching element are P-type transistors, and the second inverter switching element and the fourth inverter switching element are N-type transistors. 21. The method of claim 20, wherein the first inverter switching element further includes a feedback control electrode connected to the output terminal of the second inverter stage,
The second inverter switching element further includes a feedback control electrode connected to the output terminal of the second inverter stage. a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit includes a plurality of inverter stages and a coupling capacitor including a first end connected to the output terminal of the last inverter stage of the plurality of inverter stages and a second end connected to the control electrode of the first switching element. Including,
The timer circuit includes a first inverter stage and a second inverter stage,
The first inverter stage is
a first inverter switching element including a control electrode connected to an input terminal of the first inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to an output terminal of the first inverter stage; and
A second inverter switching element including a control electrode connected to the second power voltage terminal, a first electrode connected to the output terminal of the first inverter stage, and a second electrode connected to the second power voltage terminal; ,
The second inverter stage is
a third inverter switching element including a control electrode connected to the input terminal of the second inverter stage, a first electrode connected to the first power voltage terminal, and a second electrode connected to the output terminal of the second inverter stage; and
A fourth inverter switching element including a control electrode connected to the second power voltage terminal, a first electrode connected to the output terminal of the second inverter stage, and a second electrode connected to the second power voltage terminal. A pixel circuit characterized in that. The pixel circuit of claim 23, wherein the first inverter switching element, the second inverter switching element, the third inverter switching element, and the fourth inverter switching element are P-type transistors. The pixel circuit of claim 23, wherein the first inverter switching element further includes a feedback control electrode connected to the output terminal of the second inverter stage. a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit includes a plurality of inverter stages and a coupling capacitor including a first end connected to the output terminal of the last inverter stage of the plurality of inverter stages and a second end connected to the control electrode of the first switching element. Including,
The timer circuit includes a first inverter stage and a second inverter stage,
The first inverter stage is
a first inverter switching element including a control electrode connected to the first power voltage terminal, a first electrode connected to the first power voltage terminal, and a second electrode connected to an output terminal of the first inverter stage; and
It includes a second inverter switching element including a control electrode connected to the input terminal of the first inverter stage, a first electrode connected to the output terminal of the first inverter stage, and a second electrode connected to the second power voltage terminal. And
The second inverter stage is
a third inverter switching element including a control electrode connected to the first power voltage terminal, a first electrode connected to the first power voltage terminal, and a second electrode connected to an output terminal of the second inverter stage; and
It includes a fourth inverter switching element including a control electrode connected to the input terminal of the second inverter stage, a first electrode connected to the output terminal of the second inverter stage, and a second electrode connected to the second power voltage terminal. A pixel circuit characterized in that. The pixel circuit of claim 26, wherein the first inverter switching element, the second inverter switching element, the third inverter switching element, and the fourth inverter switching element are N-type transistors. The pixel circuit of claim 26, wherein the second inverter switching element further includes a feedback control electrode connected to the output terminal of the second inverter stage. a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit includes a plurality of inverter stages and a coupling capacitor including a first end connected to the output terminal of the last inverter stage of the plurality of inverter stages and a second end connected to the control electrode of the first switching element. Including,
When the last inverter stage among the plurality of inverter stages is the M-th inverter stage, at least one of the inverter switching elements of the M-1th inverter stage includes a feedback control electrode, and the output terminal of the M-th inverter stage is the first inverter stage. A pixel circuit connected to the feedback control electrode of the inverter switching element of the M-1 inverter stage (M is a natural number of 2 or more). a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit includes a plurality of inverter stages and a coupling capacitor including a first end connected to the output terminal of the last inverter stage of the plurality of inverter stages and a second end connected to the control electrode of the first switching element. Including,
When the last inverter stage among the plurality of inverter stages is the M-th inverter stage, at least one of the inverter switching elements of the M-3-th inverter stage includes a feedback control electrode, and the output terminal of the M-th inverter stage is the first inverter stage. M-3 A pixel circuit connected to the feedback control electrode of the inverter switching element of the inverter stage (M is a natural number of 4 or more). display panel;
a gate driver that outputs a gate signal to a pixel circuit of the display panel; and
a data driver outputting a data voltage to the pixel circuit of the display panel;
The pixel circuit displays an image based on the gate signal and the data voltage,
The pixel circuit is
a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit is
inverter;
a coupling capacitor including a first end connected to the output terminal of the inverter and a second end connected to the control electrode of the first switching element;
A sweeping capacitor including a first terminal to which a sweeping signal is applied and a second terminal connected to the input terminal of the inverter; and
A display device comprising a timer switching element that applies a data voltage to the input terminal of the inverter in response to a gate signal. display panel;
a gate driver that outputs a gate signal to a pixel circuit of the display panel; and
a data driver outputting a data voltage to the pixel circuit of the display panel;
The pixel circuit displays an image based on the gate signal and the data voltage,
The pixel circuit is
a first switching element connected to a first power voltage terminal;
a second switching element connected in series with the first switching element;
a light emitting element connected to the second switching element and a second power voltage terminal; and
It includes a timer circuit connected to the control electrode of the first switching element,
The timer circuit is
a plurality of inverter stages;
a coupling capacitor including a first end connected to the output terminal of the last inverter stage among the plurality of inverter stages and a second end connected to the control electrode of the first switching element;
a sweeping capacitor including a first stage to which a sweeping signal is applied and a second stage connected to an input terminal of a first inverter stage among the plurality of inverter stages; and
A display device comprising a timer switching element that applies a data voltage to the input terminal of the first inverter stage in response to a gate signal.