KR102147402B1 - Pixel and Display comprising pixels - Google Patents

Abstract

Embodiments of the present invention relate to a pixel and a display device including the same and, more specifically, to a display device capable of converting a signal related with a pixel circuit. The display device includes: a pixel part in which a plurality of pixels including a light emitting element and a pixel circuit connected to the light emitting element are arranged; a data operating part generating a bit string of n bit data and outputting the bit string to the pixels; a clock generation part generating at least one clock signal corresponding to a bit of the bit string in every frame including a data writing period and a light emitting period; and a parallel-serial converter converting at least one clock signal into a serial clock signal. The pixel circuit of the pixels includes: a first pixel circuit receiving and storing the bit string during the data writing period, and generating a control signal based on the serial clock signal and n bit values of the stored bit string during the light emitting period; and a second pixel circuit controlling the light emission and non-light emission of the light emitting element in response to the control signal during the light emitting period. The at least one clock signal is generated to individually include an edge which switches levels when a time allocated to a bit of a corresponding bit string begins, and the serial clock signal includes the edge included in each of the at least one clock signal.

Description

Pixel and display comprising pixels

Embodiments of the present invention relate to a pixel and a display device including the same, and specifically, to a display device capable of converting a signal related to a pixel circuit.

Along with the rapid growth of the AR and MR markets in recent years, the growth of the micro-display device (or micro-display) market to which micro LEDs are applied is expected thanks to low power consumption characteristics and excellent luminance characteristics.

In the case of PWM (Digital) driving of a pixel circuit with a built-in memory, a large number of wirings are required in an active area of a display device because connection to the pixel circuit is required for a plurality of gray expression signals. Therefore, in order to test for defective bonding in the related art, in particular, in the case of a large display panel in which a pixel driving circuit (IC) and a scan/data driver driving circuit (Scan/Data Driver IC) are separately assembled, a plurality of input pads are provided in the pixel driving circuit (Input PAD) is required.

In the case of a conventional display device, since it is impossible to embed a large number of memories, a frequency required for related driving must be increased, and a large number of subframes are required, resulting in problems such as image deterioration. Accordingly, various methods for expressing gray in a display device including a pixel circuit with a built-in memory of a PWM (digital) driving method have been proposed.

However, in the case of a conventional display device, a connection between a plurality of gray expression signals and a pixel circuit is required, and a large number of wirings are required in the entire display area. In particular, in the case of a large display device in which a pixel circuit and a scan/data driving circuit are separately assembled, a plurality of input pads (PADs) are required, and power consumption is severe on wiring.

The present invention is in accordance with the above-described necessity, and an object of the present invention is to reduce power consumption and to provide a micro display device in which the connection between circuits is simplified, and a driving method thereof.

However, these problems are exemplary, and the scope of the present invention is not limited thereby.

A display device according to an exemplary embodiment of the present invention includes: a pixel portion in which a plurality of pixels including a light emitting device and a pixel circuit connected to the light emitting device are arranged; a data driver generating a bit stream of n-bit data and outputting the bit stream to the pixel; And a clock generator that generates at least one clock signal corresponding to a bit of the bit string for each frame including a data write period and a light emission period, and converts the at least one clock signal into a serial clock signal. Parallel-to-serial converter; The pixel circuit of the pixel receives and stores the bit string during the data writing period, and generates a control signal based on the n bit values of the stored bit string and the serial clock signal during the light emission period. Pixel circuit; And a second pixel circuit for controlling light emission and non-emission of the light emitting device in response to the control signal during the light emission period, wherein the at least one clock signal is a time allocated to a bit of the corresponding bit string. It is generated to include an edge at which the level is switched at the starting point, and the serial clock signal may include the edge included in each of the at least one clock signal.

Further, when an edge included in the serial clock signal is input, the first pixel circuit may generate the control signal by reading a bit value of a bit corresponding to the input edge among the n bits.

In addition, the clock generator may generate at least one clock signal corresponding to an odd-numbered bit among n bits of the bit string.

At this time, the edge includes a rising edge and a falling edge, and the first pixel circuit reads a bit value of an odd-numbered bit among n bits of the bit string when a rising edge of the edge is input, and the falling edge of the edge When is input, the bit value of the even-numbered bit among n bits of the bit string can be read.

Other aspects, features, and advantages other than those described above will become apparent from the detailed content, claims and drawings for carrying out the following invention.

According to an embodiment of the present invention made as described above, by converting an external input signal for gray expression into a serial signal, wiring can be minimized, and an increase in current consumption generated on the wiring can be suppressed. have.

In addition, according to an embodiment of the present invention, it is possible to minimize a transition in a clock signal by utilizing time information of each edge when switching a serial structure.

Of course, the scope of the present invention is not limited by these effects.

1 is a schematic diagram illustrating a manufacturing process of a display device according to an exemplary embodiment of the present invention.
2 and 3 are diagrams schematically illustrating a display device according to an exemplary embodiment of the present invention.
4A and 4B are circuit diagrams showing a current supply unit according to an embodiment of the present invention.
5 is a circuit diagram illustrating a pixel PX according to an exemplary embodiment of the present invention.
6 is an exemplary diagram illustrating a clock signal generated in parallel according to a time allocated for each bit in a conventional display device.
7A and 7B are simple block diagrams illustrating a parallel-to-serial converter according to an embodiment of the present invention.
8A and 8B are timing diagrams for explaining a method of driving a serial clock signal according to an embodiment of the present invention.
9 is a timing diagram illustrating a method of driving a serial clock signal according to an embodiment of the present invention.

Hereinafter, various embodiments of the present disclosure will be described in connection with the accompanying drawings. Various embodiments of the present disclosure may be subjected to various changes and may have various embodiments, and specific embodiments are illustrated in the drawings and related detailed descriptions are described. However, this is not intended to limit the various embodiments of the present disclosure to a specific embodiment, and it should be understood that all changes and/or equivalents or substitutes included in the spirit and scope of the various embodiments of the present disclosure are included. In connection with the description of the drawings, similar reference numerals have been used for similar elements.

In various embodiments of the present disclosure, expressions such as "or" include any and all combinations of words listed together. For example, "A or B" may include A, may include B, or may include both A and B.

In the following embodiments, terms such as first and second are not used in a limiting meaning, but are used for the purpose of distinguishing one component from another component. In addition, in the following embodiments, expressions in the singular include plural expressions unless the context clearly indicates otherwise.

In the following embodiments, when X and Y are connected, X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. I can. Here, X and Y may be objects (eg, devices, devices, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship indicated in the drawings or detailed description, and may include anything other than the connection relationship indicated in the drawing or detailed description.

When X and Y are electrically connected, for example, an element (e.g., a switch, a transistor, a capacitor element, an inductor, a resistance element, a diode, etc.) that enables the electrical connection of X and Y, It may include a case in which at least one is connected between X and Y.

In the following embodiments, "ON" used in connection with the device state may refer to an activated state of the device, and "OFF" may refer to an inactive state of the device. "On" used in connection with a signal received by the device may refer to a signal that activates the device, and "off" may refer to a signal that disables the device. The device can be activated by a high voltage or a low voltage. For example, a P-type transistor is activated by a low voltage, and an N-type transistor is activated by a high voltage. Therefore, it should be understood that the "on" voltage for the P-type and N-type transistors is at opposite (low vs. high) voltage levels.

In the following embodiments, terms such as include or have means that the features or elements described in the specification are present, and do not preclude the possibility of adding one or more other features or elements in advance. Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram illustrating a manufacturing process of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device 30 according to an exemplary embodiment may include a light emitting device array 10 and a driving circuit board 20. The light emitting device array 10 may be coupled to the driving circuit board 20. The display device 30 may be a micro display device.

The light emitting device array 10 may include a plurality of light emitting devices. The light emitting device may be a light emitting diode (LED). The light emitting device may be a light emitting diode (LED) having a micro to nano unit size. At least one light emitting device array 10 may be manufactured by growing a plurality of light emitting diodes on a semiconductor wafer. Accordingly, the display device 30 can be manufactured by combining the light emitting device array 10 with the driving circuit board 20 without the need to individually transfer the light emitting diodes to the driving circuit board 20.

Pixel circuits corresponding to each of the light emitting diodes on the light emitting device array 10 may be arranged on the driving circuit board 20. The light emitting diodes on the light emitting device array 10 and the pixel circuits on the driving circuit board 20 may be electrically connected to each other to form a pixel.

2 and 3 are diagrams schematically illustrating a display device according to an exemplary embodiment of the present invention.

2 and 3, the display device 30 may include a pixel unit 110, a driver 120, and a parallel serial converter 130.

The pixel unit 110 may display an image using an n-bit digital image signal capable of displaying 1 to 2m gray scales. The pixel unit 110 may include a plurality of pixels PX arranged in various patterns such as a predetermined pattern, for example, a matrix type and a zigzag type. The pixel PX emits one color and, for example, may emit one color of red, blue, green, and white. The pixel PX may emit colors other than red, blue, green, and white.

The pixel PX may include a light emitting device. The light emitting device may be a self-luminous device. For example, the light emitting device may be a light emitting diode (LED). The light emitting device may be a light emitting diode (LED) having a micro to nano unit size. The light emitting device may emit light with a single peak wavelength or may emit light with a plurality of peak wavelengths.

The pixel PX may further include a pixel circuit connected to the light emitting device. The pixel circuit may include at least one thin film transistor and at least one capacitor. The pixel circuit may be implemented by a semiconductor stack structure on a substrate.

The pixel PX may operate in a frame unit. Each frame may include a data writing period and a light emission period. Digital data of a predetermined bit may be applied to the pixel PX and stored during the data writing period. Digital data of a predetermined bit stored in the light emission period is read in synchronization with a clock signal, and the digital data is converted into a PWM signal, so that the pixel PX can express gray scale.

Meanwhile, according to an embodiment of the present invention, one frame may include a plurality of subframes. Even in this case, each subframe may include a data writing period and a light emission period, and the light emission period of the subframe may be a sum of times allocated to each bit of digital data.

The driving unit 120 may drive and control the pixel unit 110. The driving unit 120 may include a control unit 121, a gamma setting unit 123, a data driving unit 125, a current supply unit 127, and a clock generation unit 129.

The controller 121 receives input image data DATA1 of one frame from an external (for example, a graphic controller), receives a correction value from the gamma setting unit 123, and uses the correction value to input image data ( Corrected image data can be generated by performing gamma correction on DATA1).

The controller 121 may extract a gray level for each pixel PX from the corrected image data of one frame, and convert the extracted gray level into digital data DATA2 of a predetermined number of bits (eg, n bits). .

The controller 121 may output n-bit digital data to the data driver 125. The time (length) of the frame may be equal to the sum of the times allocated to each bit of n-bit digital data. The time allocated to each bit may be the same or different.

The gamma setting unit 123 may set a gamma value using a gamma curve, set a correction value of image data based on the set gamma value, and output the set correction value to the controller 121. The gamma setting unit 123 may be provided as a separate circuit from the control unit 121 or may be provided to be included in the control unit 121.

The data driver 125 may receive n-bit digital data in a frame unit from the control unit 121 and transmit it to each pixel PX of the pixel unit 110. The data driver 125 may include a line buffer and a shift register circuit. The line buffer may be a 1 line buffer or a 2 line buffer. The data driver 125 may provide n-bit digital data to each pixel for each frame on a line basis (row basis).

The current supply unit 127 may generate and supply the driving current of each pixel PX. The configuration of the current supply unit 127 will be described later with reference to FIGS. 4A and 4B.

The clock generator 129 may generate n clock signals during one frame and output them to the pixels PX. The n clock signals may be output corresponding to each bit of bit data. The signal width (length or ON time) of the clock signal may be determined according to a time allocated to each bit of n-bit digital data. The clock generator 129 may sequentially supply n clock signals to the clock line CL for each frame.

Each component of the driving unit 120 is formed in the form of a separate integrated circuit chip or a single integrated circuit chip, and is mounted directly on the substrate on which the pixel unit 110 is formed, or on a flexible printed circuit film. It may be mounted or attached to a substrate in the form of a TCP (tape carrier package), or may be formed directly on the substrate. In one embodiment, the control unit 121, the gamma setting unit 123, and the data driver 125 are connected to the pixel unit 110 in the form of an integrated circuit chip, and the current supply unit 127 and the clock generation unit 129 Can be formed directly on the substrate.

The parallel serial converter 130 is a configuration for converting n clock signals generated in parallel for each bit (eg, MSB, LSB) by the clock generation unit 129 into a serial signal. The parallel serial converter 130 may be a component including a logic circuit including an OR gate.

4A and 4B are circuit diagrams showing a current supply unit according to an embodiment of the present invention.

Referring to FIG. 4A, the current supply unit 127 may include a first transistor 51, a second transistor 53, an operational amplifier 55, and a variable resistor 57.

The first transistor 51 has a gate connected to the pixel PX, a first terminal connected to a power voltage VDD supply source, and a second terminal connected to the gate and a first terminal of the second transistor 55 .

The second transistor 53 has a gate connected to the output terminal of the operational amplifier 55, a first terminal connected to a second terminal of the first transistor 51, and a second terminal connected to the second terminal of the operational amplifier 55. It is connected to the input terminal (-).

The first input terminal (+) of the operational amplifier 55 is connected to the supply source of the reference voltage (Vref), and the second input terminal (-) is connected to the variable resistor 57. The output terminal of the operational amplifier 55 is connected to the gate of the second transistor 53. When the reference voltage Vref is applied to the first input terminal (+), the second transistor 53 is turned on or turned on according to the voltage of the output terminal due to the voltage difference between the first input terminal (+) and the second input terminal (-) and the output terminal. It can be turned off.

The resistance value of the variable resistor 57 may be determined according to the control signal SC from the controller 121. The voltage of the output terminal of the operational amplifier 55 is changed according to the resistance value of the variable resistor 57, and the current Iref flowing through the first transistor 51 and the second transistor 53 turned on from the power voltage VDD Can be determined.

The current supply unit 127 may supply a driving current corresponding to the current Iref to the pixel PX by configuring a transistor and a current mirror in the pixel PX. The driving current may determine the total luminance (brightness) of the pixel unit 110.

In the above-described embodiment, an example in which the current supply unit 127 includes a first transistor 51 implemented as a P-type transistor and a second transistor 53 implemented as an N-type transistor is illustrated, but the embodiment of the present invention The present invention is not limited thereto, and the current supply unit 127 may be configured by implementing the first transistor 51 and the second transistor 53 as different types of transistors and configuring an operational amplifier corresponding thereto.

In the embodiment of FIG. 4A, the current supply unit 127 is connected to one pixel PX, but the current supply unit 127 may be shared with a plurality of pixels PX. For example, as shown in FIG. 4B, the first transistor 51 of the current supply unit 127 is electrically connected to the first transistor 501 of each of all pixels PX of the pixel unit 110. A current mirror circuit can be configured. In another embodiment, the current supply unit 127 is provided for each row, and the current supply unit 127 of each row may be shared by a plurality of pixels PX in the same row.

In the above-described embodiment, an example in which the pixel is composed of P-type transistors is illustrated, but the embodiment of the present invention is not limited thereto, and the pixel is composed of N-type transistors, and in this case, the pixel is applied by P-type transistors. The level of the signal can be driven by an inverted signal.

5 is a circuit diagram illustrating a pixel PX according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the pixel PX may include a light emitting device ED and a pixel circuit including a first pixel circuit 40 and a second pixel circuit 50 connected thereto. The first pixel circuit 40 may be a low voltage driving circuit, and the second pixel circuit 50 may be a high voltage driving circuit. The first pixel circuit 40 may be implemented with a plurality of logic circuits.

The light emitting device ED can selectively emit or non-emit light based on the bit value (logical level) of the image data provided from the data driver 125 for each frame, so that the light emission time can be adjusted within one frame to display the gradation. have.

The first pixel circuit 40 stores a bit value of n-bit digital data applied from the data driver 125 in a data writing period for each frame, and a first PWM signal based on n bit values and a clock signal in the light emission period. Can be created. The first pixel circuit 40 may include a PWM controller 401 and a memory 403. In this case, the clock signal may be a serial clock signal in which n clock signals generated in parallel by the clock generator 129 are converted to a serial signal through the parallel serial converter 130.

According to an embodiment of the present invention, a frame may include a subframe. In this case, the light emitting device ED may emit light or non-emit light based on the bit value of the image data provided for each subframe, and the first pixel circuit 40 may be configured from the data driver 125 in the data writing period for each subframe. A bit value of the applied data may be stored, and a first PWM signal may be generated based on the bit value and the clock signal during the light emission period.

The PWM controller 401 may generate a first PWM signal based on a clock signal CK input from the clock generator 129 and a bit value of image data read from the memory 403 during the light emission period. When a clock signal is input from the clock generator 120, the PWM controller 401 may generate a first PWM signal by reading a corresponding image data bit value from the memory 403.

The PWM controller 401 may control the pulse width of the first PWM signal based on the bit value of the digital data and the signal width of the clock signal for each frame. For example, if the bit value of the image data is 1, the pulse output of the PWM signal is turned on as much as the signal width of the clock signal, and if the bit value of the image data is 0, the pulse output of the PWM signal is turned off as the signal width of the clock signal. have. That is, the on time of the pulse output of the PWM signal and the off time of the pulse output may be determined by the signal width (signal length) of the clock signal.

However, this is only an example, and the PWM controller 401 may control the pulse output of the PWM signal based on time information of the edge of the clock signal. In this case, the edge of the clock signal means that the clock signal transitions from a high level to a low level or from a low level to a high level. An edge transitioning from a high level to a low level may be a falling edge or a falling edge, and an edge transitioning from a low level to a high level is a rising edge. ) Or a rising edge.

According to various embodiments of the present disclosure, the PWM controller 401 may generate a control signal of a PWM signal based on at least one of a rising edge and/or a falling edge.

For example, if the bit value of the image data is 1, the pulse output of the PWM signal is turned on from the point when the clock signal edge (e.g., rising edge) occurs until the next edge (e.g., falling edge) occurs. If the bit value is 0, the pulse output of the PWM signal may be turned off from the time when the edge of the clock signal occurs until the next edge occurs.

The PWM controller 401 may include one or a plurality of logic circuits (eg, an OR gate circuit, etc.) implemented with one or a plurality of transistors.

The memory 403 may receive and store n bits of data applied through the data line DL from the data driver 125 during the data writing period for each frame in synchronization with the subframe start signal. In the case of a still image, image data previously stored in the memory 403 before an image update or refresh may be used for image display continuously for a plurality of frames.

Bit values (logical levels) of n-bit digital data may be input from the data driver 125 to the memory 403 in a predetermined order. The memory 403 can store at least 1-bit data. In one embodiment, the memory 403 may be an n-bit memory. In the memory 403, n bit values of n bit digital data may be recorded during the data writing period of the frame. The memory 403 may be implemented with one or a plurality of transistors. The memory 503 may be implemented as a random access memory (RAM), for example, SRAM or DRAM.

When n-bit digital data is applied to the memory 403 without conversion, since the memory 403 must have a capacity for storing n-bit digital data, it may be a limiting factor for miniaturization of pixels. When the memory 403 has a 1-bit capacity, since the pixel must be driven by a plurality of subframes, the driving frequency increases, and the current consumption due to the increase in the driving frequency increases, which may be a limiting factor in the case of battery-use products. . In addition, different times should be allocated for each subframe. In an embodiment of the present invention, by using a bit memory smaller than n bits for the memory 403, the memory capacity can be reduced, and thus the pixel size can be reduced. In addition, by using a bit memory smaller than n bits, the number of subframes can be reduced compared to a 1-bit memory, so that the driving frequency can be properly maintained.

The second pixel circuit 50 may control light emission and non-emission of the light emitting device ED in response to a control signal applied from the first pixel circuit 40 during one frame. The control signal may be a PWM signal. The second pixel circuit 50 may include a first transistor 501, a second transistor 503, and a level shifter 505 electrically connected to the current supply unit 127.

The first transistor 501 may output a driving current. The first transistor 501 has a gate connected to the current supply unit 127, a first terminal connected to a power voltage VDD supply source, and a second terminal connected to a first terminal of the second transistor 503. The gate of the first transistor 501 is connected to the gate of the first transistor 51 of the current supply unit 127 to form a current supply unit 127 and a current mirror circuit. Accordingly, while the first transistor 51 of the current supply unit 127 is turned on, the turned-on first transistor 501 may supply a driving current corresponding to the current Iref formed in the current supply unit 127. The driving current may be the same as the current Iref flowing through the current supply unit 127.

The second transistor 503 may transmit or block the driving current to the light emitting device ED according to the PWM signal. The second transistor 503 has a gate connected to the output terminal of the level shifter 505, a first terminal connected to a second terminal of the first transistor 501, and a second terminal connected to the light emitting device ED. .

The second transistor 503 may be turned on or off according to the voltage output from the level shift 505. The light emission time of the light emitting device ED may be adjusted according to the turn-on or turn-off time of the second transistor 503. The second transistor 503 is turned on when a gate-on level signal is applied to the gate, and transmits the driving current Iref output from the first transistor 501 to the light emitting device ED so that the light emitting device ED emits light. can do. The second transistor 503 is turned off when a gate-off level signal is applied to the gate and blocks the driving current Iref output from the first transistor 501 from being transmitted to the light emitting device ED. ) Can be made non-luminous. During one frame, the light emission time and the non-emission time of the light emitting device ED are controlled by the turn-on time and the turn-off time of the second transistor 503, so that the color depth of the pixel unit 110 can be expressed. have.

The level shifter 505 is connected to the output terminal of the PWM (Pulse Width Modulation) controller 401 of the first pixel circuit 40 and converts the voltage level of the first PWM signal output from the PWM controller 401 to a second It can generate a PWM signal. The level shifter 505 converts a gate-on voltage level signal capable of turning on the second transistor 503 and a gate-off level signal capable of turning off the second transistor 503 based on the first PWM signal. 2 PWM signals can be generated. When the first PWM signal output from the PWM controller 401 is sufficient to drive the second transistor 503, the level shifter 505 may be omitted.

The pulse voltage level of the second PWM signal output from the level shifter 505 may be higher than the pulse voltage level of the first PWM signal, and the level shifter 505 may include a booster circuit that boosts the input voltage. The level shifter 505 may be implemented with a plurality of transistors.

Turn-on time and turn-off time of the second transistor 503 during one frame may be determined according to the pulse width of the first PWM signal.

6 is an exemplary diagram illustrating a clock signal generated in parallel according to a time allocated for each bit in a conventional display device.

7A and 7B are simple block diagrams illustrating a parallel-to-serial converter according to an embodiment of the present invention.

The clock generator 129 may generate clock signals corresponding to a plurality of bits included in one frame data in parallel. The clock generator 129 may generate and output n clock signals during one frame. The n clock signals may be output corresponding to each bit of bit data. The signal width (length or ON time) of the clock signal may be determined according to a time allocated to each bit of n-bit digital data. The clock generator 129 may sequentially supply n clock signals to the clock line CL for each frame.

Meanwhile, referring to FIG. 6, a time set for each bit of n-bit digital data may be different. For example, the longest first time period (T / 2) assigned to the most significant bit (MSB), a second time (T / ² 2) a method that is assigned to the next higher bit (MSB-1), the least significant bit ( The shortest n-th time (T/2 ⁿ )) may be allocated to LSB). The sum of the times allocated to each bit of the n-bit digital data may be equal to or close to the time T allocated to one frame.

In this case, in a conventional display device, clock signals corresponding to each of the first to nth times may be sequentially supplied to the clock line CL in parallel. That is, each clock signal inevitably includes a transition process from a low level to a high level or a high level to a low level, and thus there is a problem that the consumption current increases.

On the other hand, referring to FIG. 7A, the display device 30 according to an embodiment of the present invention may convert a parallel clock signal into a serial clock signal through the parallel-serial converter 130. In this case, the parallel-to-serial converter 130 may be a device composed of a logic circuit including an OR gate. That is, when any one of a plurality of clock signals input in parallel is at a high level, the parallel-to-serial converter 130 may output a serial clock signal having a high level in a corresponding time interval.

The parallel-to-serial converter 130 may transmit a serial clock signal to the pixel PX of the pixel unit 110. Specifically, referring to FIG. 7B, n clock signals generated by the clock generating unit 129 may be converted into one serial clock signal through the parallel-serial converter 130. The serial clock signal may include information on an edge (a rising edge and/or a falling edge) included in each of the generated at least one clock signal.

In this case, the PWM controller 401 may generate the first PWM signal based on the input clock signal CK and the bit value of the image data read from the memory 403. The PWM controller 401 may control the pulse output of the PWM signal based on time information of the edge of the clock signal. The PWM controller 401 may generate a PWM signal by reading a bit value based on a timing when an edge of the clock signal occurs. The edge of the clock signal means that the clock signal transitions from high to low or from low to high. The edge transitioning from high to low may be a falling edge or a falling edge, and the edge transitioning from low to high is a rising edge or a rising edge. Can be

Specifically, in the data writing period DT (not shown), a bit value of n-bit data from the data driver 125 may be written to the memory 403 in the pixel PX. The PWM controller 401 reads the bit value of n-bit data from the memory 403 and controls the pulse width of the PWM signal based on the time interval width between edges of the clock signal CK and the bit value of the bit data. have.

For example, when the number of frame bits (n) is 4, in the light emission period (ET, not shown) of the frame, one clock signal synchronized with 4-bit data and serially converted 4 clock signals is a PWM controller ( 401), the PWM controller 401 may generate a PWM signal based on the bit value of the 4-bit data recorded in the memory 403 and the serial clock signal. The generated PWM signal may be transmitted to the second pixel circuit 50, and a light emitting diode (LED) may emit or non-emit light to correspond thereto.

2 and 7A show that the parallel-serial converter 130 is implemented as a separate configuration from the clock generation unit 129, this is only an example, and the parallel-serial converter 130 is a clock generation unit 129 ) May be included in the configuration.

In addition, in FIGS. 2 and 7A, it is shown that the parallel-to-serial converter 130 is implemented as a separate configuration from the pixel PX or the pixel unit 110, but this is only an example.

That is, in another embodiment of the present invention, the parallel-serial converter 130 may include the same components as the first pixel circuit 40 of the pixel PX, and a separate component among the driving circuits of the pixel PX. It may be included as. In the present disclosure, it is assumed that the parallel-to-serial converter 130 is implemented as a separate configuration from the pixel PX and the clock generation unit 129 of the pixel unit 110.

According to an embodiment of the present invention as described above, the connection between the pixel unit 110 and the driving unit 120 can be simplified by converting a plurality of clock signals into one serial clock signal, and further, the pixel circuit 40, 50) has the effect of reducing the number of pads used when separating.

In addition, according to the present invention, by converting a plurality of clock signals into one serial clock signal, it is possible to reduce a transition included in the clock signal, thereby reducing power consumption generated on the wiring.

8A and 8B are timing diagrams for explaining a method of driving a serial clock signal according to an embodiment of the present invention. In particular, FIG. 8A shows an example in which a PWM signal is generated by 5-bit data (odd number) per frame, and FIG. 8B shows an example in which a PWM signal is generated by 6-bit data (even number) per frame.

Referring to FIG. 8A, the pixel PX may be driven in the data writing period DT and the light emission period ET for each frame. Since the ON time of the light-emitting period ET mainly constitutes the frame time, hereinafter, the time of the frame and the time of the light-emitting period may be mixed and used.

In the light emission period (ET) of the frame, a plurality of clock signals CK1, CK3, CK5 may be generated by the clock generator 129 in synchronization with 5-bit data, and the parallel-serial converter 130 It can be converted to a serial clock signal (Serial CK). The clock generator 129 according to an embodiment of the present invention may generate only a clock signal corresponding to an odd-numbered bit among bits included in the bit data, but is not limited thereto.

Each of the plurality of clock signals CK1, CK3, and CK5 may be applied at the same time as the time allocated to the MSB, MSB-2, and LSB bits of 5-bit data. For example, the first clock signal CK1 is applied during the time allocated to the MSB (T/2), and the third clock signal CK3 is applied during the time allocated to the MSB-2 (T/2 ³ ). Is applied, and the fifth clock signal CK5 may be applied for a time period T/2 ⁵ allocated to the LSB.

However, this is only an example for the case of 5-bit data, and is not limited thereto. For example, in the case of m (odd) bit data, the clock generation unit 129 of the present invention is the same as the time allocated to the MSB, MSB-2, MSB-4, MSB-6 to LSB (2-bit interval) bits. A plurality of clock signals CK1, CK3, CK5 to CKm applied with time may be generated.

The serial clock signal (Serial CK) can be applied to the PWM controller 401, and the PWM controller 401 is based on the bit value of the 5-bit data recorded in the memory 403 and the serial clock signal (Serial CK). Can generate signals.

The PWM controller 401 reads the bit value of 5-bit data from the memory 403 and controls the pulse width of the PWM signal based on the time interval between edges of the serial clock signal (serial CK) and the bit value of the bit data. I can.

Specifically, the PWM controller 401 according to an embodiment of the present invention may classify a bit value of 5-bit data based on an edge of a serial clock signal (serial CK). That is, reading the bit value (1) corresponding to MSB based on the first edge (E1), reading the bit value (0) corresponding to MSB-1 based on the second edge (E2), A bit value (0) corresponding to MSB-2 is read based on the third edge (E3), and a bit value (1) corresponding to MSB-3 is read based on the fourth edge (E4), The bit value 1 corresponding to the LSB may be read based on the fifth edge E5. At this time, the first edge E1, the third edge E3, and the fifth edge E5 may be a rising edge or a rising edge, and the second edge E2 and the fourth edge E4 are It may be a falling edge or a falling edge. According to the above-described embodiment, the PWM controller 401 may read a bit value of an odd-numbered bit in a bit string when a rising edge is input, and read a bit value of an even-numbered bit in a bit string when a falling edge is input. .

Referring to FIG. 8B, similarly, the pixel PX may be driven in the data writing period DT and the light emission period ET for each frame. In the light emission period (ET) of the frame, a plurality of clock signals CK1, CK3, CK5 may be generated by the clock generator 129 in synchronization with 6-bit data, and the parallel-serial converter 130 It can be converted to a serial clock signal (Serial CK).

In this case, each of the plurality of clock signals CK1, CK3, and CK5 may be applied at the same time as the time allocated to the MSB, MSB-2, and MSB-4 bits of 6-bit data. For example, the first clock signal CK1 is applied during the time allocated to the MSB (T/2), and the third clock signal CK3 is applied during the time allocated to the MSB-2 (T/2 ³ ). Is applied, and the fifth clock signal CK5 may be applied for a time T/2 ⁵ allocated to the MSB-4.

However, this is only an example for the case of 6-bit data, and is not limited thereto. For example, in the case of m (even) bit data, the clock generation unit 129 of the present invention is the time allocated to the MSB, MSB-2, MSB-4, MSB-6 to LSB+1 (2-bit interval) bits. A plurality of clock signals CK1, CK3, CK5 to CKm applied at the same time as may be generated.

The serial clock signal (Serial CK) may be applied to the PWM controller 401, and the PWM controller 401 is based on the bit value of 6-bit data recorded in the memory 403 and the serial clock signal (Serial CK). Can generate signals.

The PWM controller 401 reads the bit value of 6-bit data from the memory 403 and controls the pulse width of the PWM signal based on the time interval between edges of the serial clock signal (serial CK) and the bit value of the bit data. I can.

Specifically, the PWM controller 401 according to an embodiment of the present invention may classify a bit value of 6-bit data based on an edge of a serial clock signal (serial CK). That is, the bit value corresponding to the MSB is read based on the first edge (E1), the bit value corresponding to the MSB-1 is read based on the second edge (E2), and the third edge (E3) A bit value corresponding to MSB-2 is read based on, and a bit value corresponding to MSB-3 is read based on the fourth edge (E4), and LSB+1 is based on the fifth edge (E5). It is possible to perform a bit value reading corresponding to. At this time, the first edge E1, the third edge E3, and the fifth edge E5 may be a rising edge or a rising edge, and the second edge E2 and the fourth edge E4 are It may be a falling edge or a falling edge.

On the other hand, since the bit value corresponding to the LSB is read based on the sixth edge (E6), the PWM controller 401 generates a PWM signal through ON Time to which a predetermined time is added from the serial clock signal (serial CK). shall. In this case, the predetermined time may be a time exceeding (T/2 ⁶ ), which is a time allocated to the LSB at least.

9 is a timing diagram illustrating a method of driving a serial clock signal according to an embodiment of the present invention.

The PWM controller 401 of the embodiment of FIG. 9 may set only a rising edge or a rising edge as a reference for reading a bit value of bit data.

In the light emission period (ET) of the frame, a plurality of clock signals CK1 to CK5 may be generated by the clock generator 129 in synchronization with 5-bit data, and a serial clock by the parallel-serial converter 130 It can be converted into a signal (Serial CK).

The PWM controller 401 according to an embodiment of the present invention reads a bit value corresponding to MSB based on the first edge E1, and reads a bit corresponding to MSB-1 based on the second edge E2. Performing a value reading, reading a bit value corresponding to MSB-2 based on the third edge E3, reading a bit value corresponding to MSB-3 based on the fourth edge E4, and A bit value corresponding to the LSB may be read based on the fifth edge E5. In this case, all of the first to fifth edges E1 to E5 may be a rising edge or a rising edge.

On the other hand, in the present embodiment, since only a rising edge or a rising edge serves as a reference for reading a bit value, the signal width of the clock signal may be independent of PWM generation. Accordingly, the signal widths of the plurality of clock signals CK1 to CK5 may be freely generated in a line that does not overlap between the clock signals.

As an example, the clock signals CK1 to CK5 may be generated in the form of an impulse generating only a rising edge or a rising edge. Through this embodiment, there is an effect that power consumption generated on the serial clock signal line CL can be greatly reduced.

As described above, the present invention has been described with reference to the embodiments shown in the drawings, but these are only exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

10: light emitting element array
20: driver circuit board
30: display device
110: pixel portion
120: drive unit
121: control unit
123: Gamma setting unit
125: data driver
127: current supply
130: parallel-to-serial converter

Claims (4)

A pixel portion in which a plurality of pixels including a light emitting element and a pixel circuit connected to the light emitting element are arranged;
a data driver generating a bit stream of n-bit data and outputting the bit stream to the pixel; And
Including; a clock generator for generating at least one clock signal corresponding to the bit of the bit string for each frame including a data writing period and a light emission period,
A parallel-to-serial converter converting the at least one clock signal into a serial clock signal;
The pixel circuit of the pixel,
A first pixel circuit for receiving and storing the bit string during the data writing period, and generating a control signal based on n bit values of the stored bit string and the serial clock signal during the light emission period; And
And a second pixel circuit for controlling light emission and non-emission of the light emitting element in response to the control signal during the light emission period, and
The at least one clock signal is each generated to include an edge at which the level is switched at the start of the time allotted to the bit of the corresponding bit string,
The serial clock signal includes the edge included in each of the at least one clock signal. The method of claim 1,
When an edge included in the serial clock signal is input, the first pixel circuit generates the control signal by reading a bit value of a bit corresponding to the input edge among the n bits. The method of claim 1,
The clock generator generates at least one clock signal corresponding to an odd-numbered bit among n bits of the bit string. The method of claim 3,
The edge includes a rising edge and a falling edge,
The first pixel circuit reads a bit value of an odd-numbered bit among n bits of the bit string when a rising edge of the edge is input, and when a falling edge of the edge is input, the even-numbered bit of n bits of the bit string is Display device for reading bit values.

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