KR101942466B1 - Pixel and Display comprising pixels - Google Patents

Abstract

According to embodiments of the present invention, disclosed are a pixel and a display device including the same. According to one embodiment of the present invention, the pixel comprises: a light emitting device; and a pixel circuit connected to the light emitting device. The pixel circuit includes a first pixel circuit controlling emission and non-emission of the light emitting device in response to a control signal applied to each of the plurality of sub-frames constituting one frame in a light emitting period and a second pixel circuit storing a bit value of image data in a data writing period and generating the control signal based on the bit value and a clock signal in the light emitting period.

Description

[0001] The present invention relates to a pixel and a display device including the same,

The embodiments relate to a pixel and a display device including the same.

Display devices utilizing light emitting diodes (LEDs) are gaining popularity in a wide range of applications, from small handheld electronic devices to large outdoor displays. The LED display device includes pixel circuits for driving the LEDs, thereby enabling precise voltage switching of each pixel.

An embodiment of the present invention is to provide a display device capable of reducing power consumption.

A pixel according to an embodiment of the present invention includes a light emitting element and a pixel circuit connected to the light emitting element, and the pixel circuit includes a plurality of sub- A first pixel circuit for controlling light emission and non-light emission of the light emitting element in response thereto; And a second pixel circuit for storing a bit value of the video data in the data writing period and generating the control signal based on the bit value and the clock signal in the light emitting period.

The first pixel circuit includes a first transistor for outputting a driving current; And a second transistor for transmitting or blocking the driving current to the light emitting element according to the control signal.

The first pixel circuit may further include a level shifter for converting a voltage level of the control signal.

The first transistor may constitute an external circuit of the pixel and a current mirror circuit.

The second pixel circuit includes: a memory for storing a bit value of the image data; And a PWM controller that reads the bit value from the memory and generates the control signal whose pulse width is adjusted in accordance with the length of the clock signal and the bit value.

A display device according to an embodiment of the present invention includes a pixel portion in which a plurality of pixels each including a light emitting element and a pixel circuit connected to the light emitting element are arranged; A current supplying unit supplying a driving current to the plurality of pixels; And a clock generating unit for supplying a clock signal to the plurality of pixels for every n subframes constituting one frame in a light emission period, A first pixel circuit for controlling the light emission and non-light emission of the light emitting element in response to a control signal being applied to the first pixel circuit; And a second pixel circuit for storing a bit value of the video data in the data writing period and generating the control signal based on the bit value and the clock signal in the light emitting period.

The first pixel circuit includes a first transistor for outputting a driving current; And a second transistor for transmitting or blocking the driving current to the light emitting element according to the control signal.

The first pixel circuit may further include a level shifter for converting a voltage level of the control signal.

The first transistor may constitute an external circuit of the pixel and a current mirror circuit.

The second pixel circuit includes: a memory for storing a bit value of the image data; And a PWM controller that reads the bit value from the memory and generates the control signal whose pulse width is adjusted in accordance with the length of the clock signal and the bit value.

The display device according to the embodiment of the present invention can reduce power consumption.

1 is a schematic view showing a manufacturing process of a display device according to an embodiment of the present invention.
2 and 3 are views schematically showing a display device according to an embodiment of the present invention.
4 is a circuit diagram showing a current supply unit according to an embodiment of the present invention.
5 is a circuit diagram showing a pixel PX according to an embodiment of the present invention.
6 is a diagram illustrating a connection relationship between a current supply unit and a pixel according to an exemplary embodiment of the present invention.
7 is a view for explaining driving of a pixel according to an embodiment of the present invention.
8 is a view for explaining driving of a pixel according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and methods of achieving them will be apparent with reference to the embodiments described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like or corresponding components throughout the drawings, and a duplicate description thereof will be omitted .

In the following embodiments, the terms first, second, and the like are used for the purpose of distinguishing one element from another element, not the limitative meaning. Further, in the following embodiments, the singular expressions include plural expressions unless the context clearly indicates otherwise.

In the following embodiments, when X and Y are connected, when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are connected directly . Here, X and Y may be objects (e.g., devices, elements, circuits, wires, electrodes, terminals, conductive films, layers, etc.). Therefore, the present invention is not limited to the predetermined connection relationship, for example, the connection relationship shown in the drawings or the detailed description, and may include connections other than those shown in the drawings or the detailed description.

In the case where X and Y are electrically connected, for example, a device (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, or the like) And one or more connections between X and Y may be included.

When X and Y are functionally connected, a circuit (for example, a logic circuit (OR gate, inverter, etc.) that enables a functional connection of X and Y, such as when a signal output from X is transferred to Y, , A signal generation circuit, a signal generation circuit, a signal generation circuit, a signal generation circuit, a signal generation circuit, a signal generation circuit, a signal generation circuit, a signal conversion circuit (AD conversion circuit, a gamma correction circuit, A case where one or more memory circuits (memories, etc.) are connected between X and Y may be included.

In the following embodiments, " ON " used in connection with the device state refers to the activated state of the device, and " OFF " refers to the deactivated state of the device. &Quot; on " used in connection with a signal received by a device refers to a signal that activates the device, and " off " may refer to a signal that deactivates the device. The device can be activated by either a high voltage or a low voltage. For example, a P-type transistor is activated by a low voltage and an N-type transistor is activated by a high voltage. Therefore, it should be understood that the "on" voltage for the P-type transistor and the N-type transistor is the opposite (low to high) voltage level.

In the following embodiments, terms such as inclusive or possessive are intended to mean that a feature, or element, described in the specification is present, and does not preclude the possibility that one or more other features or elements may be added.

1 is a schematic view showing a manufacturing process of a display device according to an embodiment of the present invention.

Referring to FIG. 1, a display device 30 according to an exemplary embodiment may include a light emitting device array 10 and a driving circuit substrate 20. The light emitting element array 10 may be coupled to the driving circuit substrate 20. [

The light emitting element array 10 may include a plurality of light emitting elements. The light emitting device may be a light emitting diode (LED). At least one light emitting device array 10 can be manufactured by growing a plurality of light emitting diodes on a semiconductor wafer SW. Therefore, the display device 30 can be manufactured by combining the light emitting element array 10 with the driving circuit substrate 20 without the need to transfer the light emitting diodes individually to the driving circuit substrate 20. [

Pixel circuits corresponding to the respective light emitting diodes on the light emitting element array 10 may be arranged on the driving circuit substrate 20. The light emitting diode on the light emitting element array 10 and the pixel circuit on the driving circuit substrate 20 are electrically connected to constitute the pixel PX.

2 and 3 are views schematically showing a display device according to an embodiment of the present invention.

Referring to FIGS. 2 and 3, the display device 30 may include a pixel portion 110 and a driving portion 120.

The pixel unit 110 may display an image using an n-bit digital image signal capable of displaying 1 to 2 ⁿ gray scales. The pixel unit 110 may include a plurality of pixels PX arranged in various patterns such as a matrix, a zigzag, or the like. The pixel PX emits one color and can emit, for example, one of red, blue, green, and white. The pixel PX may emit other colors than red, blue, green, and white.

The pixel PX may include a light emitting element. The light emitting element may be a self light emitting element. For example, the light emitting device may be a light emitting diode (LED). The light emitting device may be a light emitting diode (LED) having a micro to nano unit size. The light emitting element can emit a single peak wavelength or emit a plurality of peak wavelengths.

The pixel PX may further include a pixel circuit connected to the light emitting element. The pixel circuit may include at least one thin film transistor and at least one capacitor or the like. The pixel circuit can be implemented by a semiconductor laminated structure on a substrate.

The driving unit 120 may drive and control the pixel unit 110. The driving unit 120 may include a control unit 121, a gamma setting unit 123, a data driving unit 125, a current supplying unit 127, and a clock generating unit 129.

The controller 121 receives the image data of one frame from the outside (for example, a graphic controller) and extracts the grayscale for each pixel PX and converts the extracted grayscale into digital data of a predetermined number of bits . The controller 121 receives the correction value from the gamma setting unit 123 and performs gamma correction of the input image data DATA1 using the correction value to generate corrected image data DATA2. The control unit 121 can output the corrected video data DATA2 to the data driver 125. [ The control unit 121 may output the least significant bit (LSB) from the most significant bit (MSB) of the corrected video data DATA2 to the shift register 125 in a predetermined order.

The gamma setting unit 123 sets a gamma value using a gamma curve, sets a correction value of the image data according to the set gamma value, and outputs the set correction value to the control unit 121. [ The gamma setting unit 123 may be provided separately from the control unit 121 and may be included in the control unit 121. [

The data driver 125 can transmit the corrected video data DATA2 from the controller 121 to each pixel PX of the pixel unit 110. [ The data driver 125 may provide a bit value included in the corrected video data DATA2 to each pixel PX per frame. The bit value may have either a first logic level and a second logic level. The first logic level and the second logic level may be high level and low level, respectively. Alternatively, the first logic level and the second logic level may be low level and high level, respectively.

One frame may be composed of a plurality of subframes. When the display device 30 displays n-bit image data, one frame may be composed of eight sub-frames. The length of each subframe may be different. For example, the length of the subframe corresponding to the most significant bit (MSB) of the corrected video data DATA2 is the longest, and the length of the subframe corresponding to the least significant bit (LSB) is set to be the shortest. The order of MSB to LSB of the video data DATA2 may correspond to the order of the first subframe to the nth subframe, respectively. The order of expression of subframes can be set differently by the designer.

The data driver 125 may include a line buffer and a shift register circuit. The line buffer may be a 1-line buffer or a 2-line buffer. The data driver 125 may provide n-bit image data to each pixel on a line-by-line basis (row-by-row basis).

The current supply unit 127 can generate and supply a driving current for each pixel PX. The configuration of the current supply unit 127 will be described later with reference to FIG.

The clock generating unit 129 may generate a clock signal for each subframe for one frame and output it to the pixels PX. The length of the clock signal may be equal to the length of the corresponding subframe. The clock generating unit 129 can sequentially supply the clock signal to the clock line CL for each subframe. The clock generating unit 129 can generate the clock signal according to the determined sub-frame order. For example, when the four subframe generation order is 1-2-3-4, the clock generation unit 129 generates the first clock signal to the fourth clock signal in the order of the first subframe to the fourth subframe Can be output sequentially. When the four subframe output sequences are 1-3-2-4, the clock generation unit 129 generates the first clock signal (first clock signal) in the order of the first subframe, the third subframe, the second subframe, , The third clock signal, the second clock signal, and the fourth clock signal in this order.

Each component of the driver 120 may be formed in the form of a separate integrated circuit chip or an integrated circuit chip and may be mounted directly on a substrate on which the pixel portion 110 is formed or on a flexible printed circuit film Attached to the substrate in the form of a TCP (tape carrier package), or formed directly on the substrate. The controller 121, the gamma setting unit 123 and the data driver 125 are connected to the pixel unit 110 in the form of an integrated circuit chip and include a current supply unit 127 and a clock generation unit 129, May be formed directly on the substrate.

4 is a circuit diagram showing a current supply unit according to an embodiment of the present invention.

Referring to FIG. 4, the current supply unit 127 may include a first transistor 51, a second transistor 53, an operational amplifier 55, and a variable resistor 57.

The first transistor 51 has a gate connected to the pixel PX and a first terminal connected to the power supply voltage VDD source and a second terminal connected to the gate and the first terminal of the second transistor 55 .

The second transistor 53 has a gate connected to the output terminal of the operational amplifier 55 and a first terminal connected to the second terminal of the first transistor 51 and a second terminal connected to the second terminal of the operational amplifier 55 Connected to the input terminal (-).

The first input terminal (+) of the operational amplifier 55 is connected to the source of the reference voltage Vref and the second input terminal (-) is connected to the variable resistor 57. The output terminal of the operational amplifier 55 is connected to the gate of the second transistor 53. When the reference voltage Vref is applied to the first input terminal +, the second transistor 53 is turned on or off according to the voltage of the output terminal due to the voltage difference between the first input terminal (+) and the second input terminal (- Can be turned off.

The resistance value of the variable resistor 57 can be determined according to the control signal SC from the control unit 121. [ The output terminal voltage of the operational amplifier 55 is changed in accordance with the resistance value of the variable resistor 57 and the current Iref flowing along the first transistor 51 and the second transistor 53 turned on from the power source voltage VDD, Can be determined.

The current supply unit 127 can supply a driving current corresponding to the current Iref to the pixel PX by configuring a transistor and a current mirror in the pixel PX. The driving current can determine the total luminance (brightness) of the pixel portion 110.

In the above-described embodiment, the current supply unit 127 includes the first transistor 51 implemented as a P-type transistor and the second transistor 53 configured as an N-type transistor. However, The present invention is not limited thereto and the first transistor 51 and the second transistor 53 may be implemented by different types of transistors and an operational amplifier corresponding thereto may be configured to configure the current supply unit 127. [

5 is a circuit diagram showing a pixel PX according to an embodiment of the present invention.

Referring to FIG. 5, the pixel PX may include a pixel circuit including a light emitting element ED and a first pixel circuit 40 and a second pixel circuit 50 connected thereto. The first pixel circuit 40 may be a high voltage driving circuit and the second pixel circuit 50 may be a low voltage driving circuit. The second pixel circuit 50 may be implemented with a plurality of logic circuits.

The light emitting device ED selectively emits light for each subframe based on the bit value (logic level) of the image data supplied from the data driver 125 for one frame, so that the light emission time is adjusted within one frame, have.

The first pixel circuit 40 may adjust the emission and non-emission of the light emitting element ED in response to a control signal applied to each of the plurality of sub-frames during one frame. The control signal may be a PWM signal. The first pixel circuit 40 may include a first transistor 401, a second transistor 403 and a level shifter 405 electrically connected to the current supply unit 127.

The first transistor 401 can output a driving current. The first transistor 401 has a gate connected to the current supply 127 and a first terminal connected to the power supply voltage VDD and a second terminal connected to the first terminal of the second transistor 403. The gate of the first transistor 401 may be connected to the gate of the first transistor 51 of the current supply unit 127 to constitute a current mirror circuit with the current supply unit 127. The first transistor 51 of the current supply unit 127 is turned on and the first transistor 401 that is turned on can supply the driving current corresponding to the current Iref formed in the current supply unit 127. The drive current may be equal to the current Iref flowing in the current supply part 127. [

The second transistor 403 may transmit or block the driving current to the light emitting device ED according to the PWM signal. The second transistor 403 has a gate connected to the output terminal of the level shifter 405, a first terminal connected to the second terminal of the first transistor 401 and a second terminal connected to the light emitting element ED .

The second transistor 403 may be turned on or off according to the voltage output from the level shift 405. The light emission time of the light emitting device ED can be adjusted according to the turn-on or turn-off time of the second transistor 403. The second transistor 403 is turned on when a gate-on level signal (low level in the embodiment of FIG. 5) is applied to the gate and outputs the driving current Iref output from the first transistor 401 to the light emitting element ED So that the light emitting device ED can emit light. The second transistor 403 is turned off when a gate-off level signal (high level in the embodiment of FIG. 5) is applied to the gate so that the driving current Iref output from the first transistor 401 is applied to the light- So that the light emitting device ED can emit no light. The emission time and the non-emission time of the light emitting device ED are controlled by the turn-on time and the turn-off time of the second transistor 403 during one frame so that the color depth of the pixel unit 110 can be expressed have.

The level shifter 405 is connected to the output terminal of the PWM (Pulse Width Modulation) controller 501 of the second pixel circuit 50 and converts the voltage level of the first PWM signal output from the PWM controller 501, The PWM signal can be generated. The level shifter 405 converts the first PWM signal into a gate-on voltage level signal capable of turning on the second transistor 403 and a gate-off level signal capable of turning off the second transistor 403, Signal can be generated.

The pulse voltage level of the second PWM signal output by the level shifter 405 may be higher than the pulse voltage level of the first PWM signal and the level shifter 405 may include a boosting circuit for boosting the input voltage. The level shifter 405 may be implemented with a plurality of transistors.

The turn-on time and the turn-off time of the second transistor 403 can be determined for one frame according to the pulse width of the first PWM signal.

The second pixel circuit 50 stores the bit value of the video data applied from the data driver 125 in the data writing period for each frame and generates the first PWM signal based on the bit value and the clock signal in the light emitting period have. The second pixel circuit 50 may include a PWM controller 501 and a memory 503.

The PWM controller 501 can generate the first PWM signal based on the bit value of the video data read from the memory 503 and the clock signal CK input from the clock generating unit 120 in the light emitting period. The PWM controller 501 can generate the first PWM signal by reading the corresponding image data bit value from the memory 503 when the clock signal of the subframe unit is input from the clock generation unit 120. [

The PWM controller 501 can control the pulse width of the first PWM signal based on the bit value of the video data in the subframe unit and the signal width of the clock signal. For example, when the bit value of the video data is 1, the pulse output of the PWM signal is turned on by the signal width of the clock signal. If the bit value of the video data is 0, the pulse output of the PWM signal is turned off by the signal width of the clock signal have. That is, the ON time of the pulse output of the PWM signal and the OFF time of the pulse output can be determined by the signal width (signal length) of the clock signal. The PWM controller 501 may include one or a plurality of logic circuits (e.g., an OR gate circuit, etc.) implemented with one or a plurality of transistors.

The memory 503 may receive and store n-bit corrected image data (DATA2) applied through the data line (DL) from the data driver 125 during the data writing period in synchronization with the frame start signal. In the case of a still image, the image data previously stored in the memory 503 may be continuously used for image display for a plurality of frames until the image is updated or refreshed.

the most significant bit (MSB) to least significant bit (LSB) bit value (logical level) of the n-bit corrected video data DATA2 can be input from the data driver 125 to the memory 503 in a predetermined order. The memory 503 may store at least one bit of data. In one embodiment, the memory 503 may be an n-bit memory. The most significant bit (MSB) to least significant bit (LSB) of the corrected video data (DATA2) may be recorded in the memory (503) during the data writing period of the frame. In another embodiment, the memory 503 may be implemented with less than n bit memory, depending on the driving frequency. The memory 503 may be implemented with one or a plurality of transistors. The memory 503 may be implemented as a random access memory (RAM), e.g., SRAM or DRAM.

In the embodiment of FIG. 5, the current supply unit 127 is connected to one pixel PX, but the current supply unit 127 may be shared by the plurality of pixels PX. 6, the first transistor 51 of the current supply unit 127 is electrically connected to the first transistor 401 of each of the pixels PX of the pixel unit 110 A current mirror circuit can be constituted. In another embodiment, a current supply unit 127 is provided for each row, and the current supply unit 127 of each row can be shared by a plurality of pixels PX in the same row.

In the above-described embodiment, an example in which the pixel is composed of P-type transistors is shown. However, the present invention is not limited to this, and the pixel may be composed of N-type transistors, The level of the signal can be driven by the inverted signal.

7 is a view for explaining driving of a pixel according to an embodiment of the present invention.

7 is an example of pixel driving in the first row. Referring to FIG. 7, the pixel PX can be driven in the data writing period (1) and the light emitting period (2) for one frame. The light emission period (2) can be divided into the first sub-frame SF1 to the n-th sub-frame SFn.

The bit value of the video data (DATA) from the data driver 125 can be written into the memory 503 in the pixel PX in the data writing period (1).

The clock signal CK is applied to the PWM controller 501 in each subframe of the light emission period (2) and the PWM controller 501 compares the bit value of the video data (DATA) recorded in the memory 503 with the bit value of the clock signal CK) of the PWM signal.

The time lengths assigned to the first sub-frame SF1 through the nth sub-frame SFn may be different. For example, a first length (T / 2 ^ 0) is assigned to the first subframe SF1, a second length T / 2 ^ 1 is assigned to the second subframe SF2, A third length T / 2 ^ 2 may be allocated to the subframe SF3 and an nth length T / 2 ^ (n-1) may be allocated to the nth subframe SFn.

The video data DATA may be represented by n bits including the most significant bit (MSB) and the least significant bit (LSB). The order of the most significant bit (MSB) to the least significant bit (LSB) may correspond to the order of the first subframe (SF1) to the nth subframe (SFn).

The clock signal CK includes the first clock signal CK1 to the nth clock signal CKn and the first clock signal CK1 to the nth clock signal CKn include the first sub- n < / RTI > subframes SFn.

The length of the clock signal CK may be different for each subframe. For example, the first clock signal CK1 corresponding to the first sub-frame SF1 allocated to the most significant bit (MSB) of the image data (DATA) has a first length (T / 2 ^ 0) The second clock signal CK2 corresponding to the second sub-frame SF2 assigned to the next higher bit MSB-1 of the data DATA has the second length T / 2 ^ 1, The n-th clock signal CKn corresponding to the n-th sub-frame SFTn allocated to the least significant bit (LSB) of the n-th sub-frame may have an n-th length T / 2 ^ (n-1).

The PWM controller 501 reads the corresponding bit value of the video data DATA from the memory 503 for each of the first sub frame SF1 to the nth sub frame SFn and supplies the signal width of the clock signal CK The pulse width of the PWM signal can be controlled based on the bit value of the video data (DATA).

The PWM controller 501 can generate the PWM signal PWM based on the bit values of the clock signal CK and the image data DATA output from the first sub frame SF1 to the nth sub frame SFn have.

7 shows an example in which the video data DATA has n bit values of 101 .... 1. The PWM controller 501 can output a pulse having a pulse width of the first length T based on the bit value 1 of the MSB of the video data DATA and the first clock signal CK1. The PWM controller 501 can turn off the pulse output for the second length T / 2 based on the bit value 0 of the MSB-1 of the image data (DATA) and the second clock signal (CK2). The PWM controller 501 outputs a pulse having a pulse width of the nth length (T / 2 ^ (n-1)) on the basis of the bit value 1 of the LSB of the image data DATA and the nth clock signal CKn can do.

The light emitting device ED can emit light or not emit light in accordance with the pulse output of the PWM signal for one frame. The light emitting device ED can emit light for a time corresponding to the pulse width when the pulse output is turned on. The light emitting element ED can emit no light for a time period during which the pulse output is off.

8 is a view for explaining driving of a pixel according to another embodiment of the present invention.

8 is an example of pixel driving in the first row. Referring to FIG. 8, the pixel PX can be driven in a data writing period (1) and a light emitting period (2) for one frame. The light emission period (2) can be divided into the first sub-frame SF1 to the n-th sub-frame SFn. At this time, the order of expression of the first subframe SF1 to the nth subframe SFn may be different from the embodiment of Fig. 8 shows an embodiment in which the third sub-frame SF3 is expressed before the second sub-frame SF2. The bit order of the clock signal (CK) and the image data (DATA) may also be determined corresponding to the order of expression of the subframe. The order of expression of the subframes can be predetermined or changed.

Embodiments of the present invention may be implemented with a micro LED display device. Recently, as the need for a microdisplay device as a new display device increases, the development of micro LED on silicon or AMOLED on silicon, which forms an LED on silicon, is in an increasing trend. In the case of a portable display device, Respectively.

In the embodiment of the present invention, the memory is provided in the pixel and current can be driven, and power consumption can be improved since the driving unit only transmits the driving pulse to the pixel unit in the still image.

In the embodiment of the present invention, a desired gamma value can be set through digital processing, and brightness can be easily adjusted using a current mirror circuit while maintaining a set gamma value.

The embodiment of the present invention can realize a high-resolution display device with a circuit configuration based on a low-voltage transistor.

Although the present invention has been described with reference to the limited embodiments, various embodiments are possible within the scope of the present invention. It will also be understood that, although not described, equivalent means are also incorporated into the present invention. Therefore, the true scope of protection of the present invention should be defined by the following claims.

Claims (10)

A pixel including a light emitting element and a pixel circuit connected to the light emitting element,
Wherein the pixel circuit constituting the pixel includes:
A first pixel circuit for controlling light emission and non-light emission of the light emitting element in response to a control signal applied to each of a plurality of subframes constituting one frame in a light emission period; And
A control circuit for generating a control signal applied to the first pixel circuit in each of the plurality of subframes based on the bit value and the clock signal in the light emission period, And a second pixel circuit connected to the second pixel circuit. The display device according to claim 1, wherein the first pixel circuit comprises:
A first transistor for outputting a driving current; And
And a second transistor for transmitting or blocking the driving current to the light emitting element according to the control signal. The display device according to claim 2, wherein the first pixel circuit comprises:
And a level shifter for converting a voltage level of the control signal between the second transistor and the second pixel circuit. 3. The method of claim 2,
And the first transistor constitutes a current mirror circuit with an external circuit of the pixel. The display device according to claim 1, wherein the second pixel circuit comprises:
A memory for storing bit values of the image data; And
And a PWM controller for reading the bit value from the memory and generating the control signal whose pulse width is adjusted in accordance with the length of the clock signal and the bit value. A pixel portion in which a plurality of pixels each including a light emitting element and a pixel circuit connected to the light emitting element are arranged; And
And a driving unit for generating a driving current and a clock signal from the outside of the pixel unit and supplying the driving current and the clock signal to the pixel unit,
Wherein,
A current supplying unit supplying a driving current to the plurality of pixels; And
And a clock generating unit for supplying a clock signal to the plurality of pixels for every n subframes constituting one frame in the light emission period,
The pixel circuit of each of the plurality of pixels,
A first pixel circuit for controlling light emission and non-light emission of the light emitting element in response to a control signal applied to each of the n subframes during a light emission period; And
And a second pixel circuit for storing the bit value of the video data of the one frame in the data writing period and generating the control signal for each of the n subframes based on the bit value and the clock signal in the light emission period / RTI > The display device according to claim 6, wherein the first pixel circuit comprises:
A first transistor for outputting a driving current; And
And a second transistor for transmitting or blocking the driving current to the light emitting element according to the control signal. The display device according to claim 7, wherein the first pixel circuit comprises:
And a level shifter for converting a voltage level of the control signal between the second transistor and the second pixel circuit. 8. The method of claim 7,
Wherein the first transistor constitutes an external circuit of the pixel and a current mirror circuit. 7. The pixel circuit according to claim 6,
A memory for storing bit values of the image data; And
And a PWM controller that reads the bit value from the memory and generates the control signal whose pulse width is adjusted in accordance with the length of the clock signal and the bit value.

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