CN111179819A

CN111179819A - Pixel and micro LED display device comprising same

Info

Publication number: CN111179819A
Application number: CN202010109311.7A
Authority: CN
Inventors: 陈廷仰; 廖志洋
Original assignee: Yuchuang Semiconductor (guangzhou) Co Ltd
Current assignee: Yuchuang Semiconductor (guangzhou) Co Ltd
Priority date: 2020-02-22
Filing date: 2020-02-22
Publication date: 2020-05-19

Abstract

A pixel includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes: a memory which includes a light emitting element and a pixel circuit connected to the light emitting element, a plurality of sub-frames constituting one frame each including a data recording period and a light emitting period, the pixel circuit recording the data period in each sub-frame, and receiving and storing a corresponding bit sequence in a bit sequence of a plurality of n-bit data generated by combining m bits constituting a bit sequence of m-bit data with n bits smaller than m bits; and a controller including n bit values of the held corresponding bit sequence and generating a control signal based on n clock signals during the light emission period of each subframe. The micro LED display device not only saves energy, but also has good matching characteristic, and can minimize the time difference among the sub-frames of the micro LED display device so as to realize a small-size pixel circuit.

Description

Pixel and micro LED display device comprising same

Technical Field

The invention relates to a micro LED display device, in particular to a pixel and a micro LED display device comprising the pixel.

Background

As the information society develops, demands for micro LED Display devices are increasing, and various types of micro LED Display devices such as Liquid Crystal micro LED Display devices (Liquid Crystal Display devices), Plasma micro LED Display devices (Plasma Display devices), and Organic Light Emitting micro LED Display devices (Organic Light Emitting Display devices) are widely used. Recently, attention is being given to a high-resolution micro LED display device (hereinafter referred to as ˝ micro LED display device ˝) using micro light emitting diodes (μ LEDs).

In order to fully embody VR (visual Reality), AR (Augmented Reality), and MR (Mixed Reality) technologies, a more excellent property of micro LED display devices is required, and accordingly, development of micro LED on Silicon or AMOLEDon Silicon is on the increase, and particularly, a demand for minimizing a pixel size is increasing to realize high-resolution image quality.

Disclosure of Invention

The present invention is directed to a pixel and a micro LED display device including the same, so as to solve the problems of the related art.

In order to realize the purpose, the invention provides the following technical scheme:

a pixel includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes: a memory which includes a light emitting element and a pixel circuit connected to the light emitting element, a plurality of sub-frames constituting one frame each including a data recording period and a light emitting period, the pixel circuit recording the data period in each sub-frame, and receiving and storing a corresponding bit sequence in a bit sequence of a plurality of n-bit data generated by combining m bits constituting a bit sequence of m-bit data with n bits smaller than m bits; and a controller including n bit values of the held corresponding bit sequence and generating a control signal based on n clock signals during the light emission period of each subframe. The second pixel circuit includes: and a second pixel circuit for adjusting light emission and non-light emission of the light emitting element in response to the control signal during the light emission period of each sub-frame.

The number of bit sequences of the n-bit data is equal to the number of the subframes, the light emission time of each subframe is a combination of times allocated to each bit of the corresponding bit sequence, and the n-bit data is a combination of n bits among the m bits having the smallest difference in light emission time among the plurality of subframes.

In an embodiment, the n is (m/2) +1 or (m/2) -1, two bit columns of the n-bit data include at least one specific bit as a common bit in the bit columns of the m-bit data, and the time allocated to the common bit may be half of the time allocated to the specific bit in the bit columns of the m-bit data.

In one embodiment, n is m/2, the bit sequence of the n-bit data does not include bits at the same position in the m bits, and the time combinations allocated to the respective bits of the bit sequence of the n-bit data may be similar.

The first pixel circuit includes: a first transistor outputting a driving current; a second transistor for transmitting or disconnecting the driving current to the light emitting element according to the control signal; and a level shifter converting a voltage level of the control signal.

The micro LED display device according to an embodiment of the present invention may include: a light emitting element and a pixel portion including a pixel circuit connected to the light emitting element and having a plurality of pixels arranged; a data driving unit for generating a plurality of bit sequences of n-bit data by combining n bits smaller than m bits among m bits constituting a bit sequence of m-bit data, and outputting the corresponding bit sequences to the pixels in the bit sequences for outputting the plurality of n-bit data to each of a plurality of sub-frames constituting one frame; and a clock generating section for supplying a clock signal to the pixel corresponding to each bit of the bit sequence for each subframe including a data recording period and a light emitting period.

The pixel circuit of the pixel includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes: and receiving and storing the corresponding bit sequence during recording the data in each subframe, wherein n bit values of the stored corresponding bit sequence and a control signal are generated based on n clock signals during the light emission period of each subframe. The second pixel circuit includes: and a second pixel circuit for adjusting light emission and non-light emission of the light emitting element in response to the control signal during the light emission period of each sub-frame.

Compared with the prior art, the invention has the beneficial effects that: the micro LED display device not only saves energy, but also has good matching characteristic, and can minimize the time difference among the sub-frames of the micro LED display device so as to realize a small-size pixel circuit.

Drawings

FIG. 1 is a schematic view of a manufacturing process of a micro LED display device according to an embodiment of the present invention.

Fig. 2 and 3 are schematic diagrams of a micro LED display device according to an embodiment of the invention.

FIG. 4 is a diagram illustrating data partitioning according to an embodiment of the present invention.

Fig. 5 is a diagram illustrating an example of time allocation to bits according to an embodiment of the present invention.

Fig. 6 is a circuit diagram of a current supply unit according to an embodiment of the invention.

Fig. 7 is a schematic diagram of a Pixel (PX) circuit according to an embodiment of the invention.

Fig. 8 is a diagram illustrating pixel driving according to another embodiment of the present invention.

Fig. 9 is a diagram illustrating bit data division according to an embodiment of the present invention.

Fig. 10 is an explanatory diagram of clock signal driving times according to the embodiment of fig. 9.

Fig. 11 is a diagram illustrating bit data division according to another embodiment of the present invention.

Fig. 12 is an explanatory diagram of clock signal driving times according to the embodiment of fig. 11.

Fig. 13 is a diagram illustrating bit data division according to another embodiment of the present invention.

Fig. 14 is an explanatory diagram of clock signal driving times according to the embodiment of fig. 13.

Detailed Description

While the invention is susceptible to various modifications and alternative embodiments, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. The effects, features, and modes for achieving the objects of the present invention will be more apparent with reference to the accompanying drawings and embodiments described later. However, the embodiments of the present invention are not limited to the above embodiments, and may be embodied in various forms.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, to which the same or equivalent constituent elements are assigned the same reference numerals, and descriptions of overlapping contents are omitted.

In the following embodiments, the terms first, second, etc. are not limited to a certain meaning, but are used for the purpose of distinguishing a single constituent element from other constituent elements. In addition, in the following embodiments, expressions to the singular number will include a plurality of expressions unless the context clearly points to other meanings.

In the following embodiments, linking as described for X and Y may include: the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Here, X, Y may be an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like). Therefore, the predetermined connection relation is not limited to the connection relation mentioned in the drawings or the detailed description, and may include a case other than the connection relation mentioned in the drawings or the detailed description, for example.

In the case where X and Y are electrically connected, it may include: for example, more than 1 element (for example, a switch, a transistor, a capacitor, an inductor, a resistance unit, a diode, or the like) for electrically connecting X and Y is connected between X and Y.

The case where the X and Y functions are connected may include: as in the principle of transmitting a signal output from X to Y, circuits (for example, a logic circuit (OR gate, inverter, OR the like), a signal conversion circuit (an AD conversion circuit, a gamma correction circuit, OR the like), a potential level conversion circuit (a level shifter circuit OR the like), a current supply circuit, an amplification circuit (a circuit that amplifies a signal amplitude, a current amount, OR the like), a signal generation circuit, a memory circuit (a memory, OR the like) that can realize functional connection between X and Y are connected to each other by 1 OR more.

In the following embodiments, ˝ ON ˝ used in association with an element state refers to a state in which the element is activated, and ˝ OFF ˝ refers to a state in which the element is not activated. ˝ ON ˝, used in connection with signals received by the element, refers to signals that activate the element, and ˝ OFF ˝ refers to signals that deactivate the element. The element may be activated by a high voltage or a low voltage. For example, a P-type transistor may be activated by a low voltage and an N-type transistor may be activated by a high voltage. Thus, the voltage ˝ ON ˝ for a P-type transistor and an N-type transistor should be interpreted as opposite (low versus high) voltage levels.

In the following embodiments, terms including or including do not mean that a feature described in the specification or existence of a constituent element is present, and do not mean that possibility that one or more features or constituent elements can be added is excluded in advance.

As shown in fig. 1, a micro LED display device 30 according to an embodiment of the present invention may include: a light emitting element array 10 and a driving circuit substrate 20. The light emitting element array 10 may be combined with the driving circuit substrate 20.

The light emitting device array 10 may include a plurality of light emitting devices. The light emitting elements may be light emitting diodes, LEDs. A plurality of light emitting diodes may be grown on the semiconductor wafer SW to manufacture at least one light emitting device array 10. Therefore, the micro LED display device 30 can be manufactured by bonding the light emitting element array 10 and the driving circuit board 20 without transferring the light emitting diodes individually to the driving circuit board 20.

The pixel circuits each corresponding to the light emitting diode on the light emitting element array 10 may be arranged on the driving circuit substrate 20. The light emitting diodes on the light emitting element array 10 and the pixel circuits on the driving circuit substrate 20 may constitute pixels PX after being electrically connected.

As shown in fig. 2 and 3, the micro LED display device 30 may include a pixel part 110 and a driving part 120.

The pixel part 110 may display an image using an m-bit digital image signal capable of displaying 1 to 2m gray scales. The pixel part 110 may include: for example, a plurality of pixels PX arranged in various forms such as a matrix shape, a zigzag shape, and the like. The pixel PX emits one color, for example, one color among red, cyan, green, and white. The pixel PX may emit other colors in addition to red, cyan, green, and white.

The pixel PX may include a light emitting element. The light emitting element may be a sub light emitting element. For example, the light emitting elements may be light emitting diodes, LEDs. The light emitting element may be a micro or nano unit size light emitting diode LED. The light-emitting element may emit light of a single peak wavelength or may emit light of a plurality of peak wavelengths.

The pixel PX may further include a pixel circuit connected to the light emitting element. The pixel circuit may include: at least one thin film transistor and at least one capacitor, etc. The pixel circuit may be implemented in a semiconductor stacked structure on a substrate.

The pixels PX can operate in units of frames. The Frame may be configured with a plurality of sub-frames, each of which may include a data recording period and a light emitting period, the data recording period may be stored after applying a specific bit of digital data to the pixel PX, the specific bit of digital data stored during the light emitting period may be read in synchronization with a clock signal, the pixel PX may exhibit a color gradation after the digital data is converted into a PWM signal, and the light emitting time of the sub-Frame may be a sum of the digital data allocated to each bit.

The driving part 120 may drive and control the pixel part 110. The driving part 120 may include: a control section 121, a gamma setting section 123, a data driving section 125, a current supply section 127, and a clock generating section 129.

The control section 121 obtains the input image DATA1 for one frame from an external, e.g., graphic controller, and after obtaining a correction value from the gamma setting section 123, performs gamma correction on the input image DATA1 using the correction value to generate corrected image DATA 2.

Fig. 4 is an explanatory diagram of data division according to an embodiment of the present invention, and fig. 5 is a schematic diagram of an example of time allocation to bits according to an embodiment of the present invention.

As shown in fig. 4, the control unit 121 extracts a gradation from the corrected image DATA for one frame for each pixel PX, and converts the extracted gradation into digital DATA having a predetermined number of bits, for example, m bits.

The control unit 121 may divide the m-bit data into n-bit data smaller than p m pieces. Here, p may be the number of subframes. p may be smaller than n. The control unit 121 can generate a plurality of bit sequences of n-bit data by combining n bits smaller than m bits among m bits constituting a bit sequence of m-bit data. If one frame is composed of two subframes, the control unit 121 may generate two bit sequences of n-bit data from the bit sequence of m-bit data.

Details of the bit column division and allocation are described later.

The m-Bit data may be a Bit column including m Bit values within from the first Bit Most significan Bit, MSB to the least Significant Bit least significan Bit, LSB. The bit value may have any one of the first logic level and the second logic level. The first logical level and the second logical level may be a high level and a low level, respectively. Alternatively, the first logic level and the second logic level may be a low level and a high level, respectively.

As shown in fig. 5, the time set to each bit of the m-bit data may not be the same. For example, the longest first time T/2 is allocated to the first bit MSB and the shortest mth time T/2m is allocated to the least significant bit LSB in such a manner that the second time T/22 is allocated to the second bit MSB-1. The sum of the times allocated to the bits of the m-bit data may be the same as or similar to the time T each allocated to one frame.

In one embodiment, n may be m/2+1 or m/2-1. Two bit columns of the n-bit data include at least one specific bit as a common bit in the bit columns of the m-bit data. The time allocated to the common bits may be half of the time allocated to the specific bits in the bit train of the m-bit data. For example, when p is 2, the control unit 121 may divide 10-bit data into two 6-bit data or three 4-bit data. Two 6-bit data are included as a common bit in at least one of the first-bit MSB and the second-bit MSB-1 of 10 bits, respectively. The time allocated to the common bit of the two 6-bit data may be half of the time allocated to the first-bit MSB and/or the second-bit MSB-1 of the 10 bits. Two 4-bit data among the three 4-bit data may include at least one of the first bit MSB and the third bit MSB-2 of the respective 10 bits as a common bit. The time allocated to the common bit of the two 6-bit data may be half of the time allocated to the first-bit MSB and/or the second-bit MSB-1 of the 10 bits.

In another embodiment, n may be m/2. The bit sequence of the n-bit data does not include bits at the same position in the m bits, and the combination of the times allocated to the respective bits of the bit sequence of the n-bit data may be similar. For example, when p is 2, the control unit 121 may divide 10-bit data into two 5-bit data. At this time, the bits of the two 5-bit data are not repeated.

The controller 121 may output the divided p n-bit data pieces to the data driver 125 after assigning the divided data pieces to p subframes. The time length of the sub-frame may be the same as the sum of the times allocated to the bits of the n-bit data. The time allocated to each bit of the n-bit data may be the time allocated to the corresponding position at the bit column of the m-bit data or half thereof. The majority subframe time may or may not be the same. The controller 121 can generate a plurality of n-bit data by combining the bits of the m-bit data in order to minimize the time difference of the plurality of subframes, particularly, the light emission time difference of the plurality of subframes. The controller 121 may divide the time allocated to at least one of the first bit MSB, the second bit MSB-1, and the third bit MSB-2 of the m-bit data, which is the longest time, to generate a plurality of n-bit data.

The gamma setting unit 123 sets a gamma value using a gamma curve, sets a correction value for image data based on the preset gamma value, and outputs the correction value to the control unit 121. The gamma setting unit 123 may be provided separately from the control unit 121 and may be included in the control unit 121.

The data driver 125 receives the m-bit data in sub-frame units from the controller 121 and then transmits the data to each pixel PX of the pixel unit 110.

The data driving part 125 may include a line buffer and a shift register circuit. The line buffer may be a 1-line buffer or a 2-line buffer. The data driving section 125 supplies n-bit data to each pixel per sub-frame in line unit row units.

The current supply section 127 may generate and supply a driving current for each pixel PX. The configuration of the current supply unit 127 will be described later with reference to fig. 6.

The clock generator 129 may generate n clock signals per sub-frame and output the generated clock signals to the pixels PX in one frame period. The n clock signals may be output in a manner corresponding to each bit of the m-bit data. The clock signal width length or ON time is determined according to the time allocated to each bit of the m-bit data. The clock generation section 129 may sequentially supply n clock signals to the clock line CL every sub-frame.

The components of the driving unit 120 may be formed as an independent integrated circuit chip or a single integrated circuit chip, and then directly mounted on the substrate on which the pixel unit 110 is formed, or may be attached to a flexible printed circuit (flexible printed circuit) or attached to a substrate in a TCP (tape carrier package) manner, or may be directly formed in the substrate. In one embodiment, the control part 121, the gamma setting part 123, and the data driving part 125 may be connected to the pixel part 110 in an integrated circuit chip manner, and the current supply part 127 and the clock generating part 129 may be directly formed on a substrate.

As shown in fig. 6, the current supplier 127 may include: a first transistor 51, a second transistor 53, an Operational Amplifier55, and a variable resistor 57.

The first transistor 51 is connected to the gate pixel PX, has a first terminal connected to a power supply voltage VDD supply source, and has a second terminal connected to the gate and a first terminal of the second transistor 55.

The gate of the second transistor 53 is connected to the output of the operational amplifier55, the first terminal is connected to the second terminal of the first transistor 51, and the second terminal is connected to the second input of the operational amplifier 55.

The first input terminal + of the operational amplifier55 is connected to the supply source of the reference voltage Vref, and the second input terminal-is connected to the variable resistor 57. The output terminal of the operational amplifier55 is connected to the gate of the second transistor 53. When the standard voltage Vref is applied to the first input terminal +, the second transistor 53 is turned on or off according to the output terminal voltage of the voltage difference between the first input terminal + and the second input terminal-and the output terminal.

The variable resistor 57 may determine a resistance value according to a control signal SC from the control section 121. The output terminal voltage of the operational amplifier55 is changed according to the resistance value of the variable resistor 57, and a current Iref flowing through the first transistor 51 and the second transistor 53 after being turned on by the power supply voltage VDD is determined.

The current supply unit 127 mirrors the transistors and the current in the pixel PX, and supplies a drive current corresponding to the current Iref to the pixel PX. The driving current may determine the overall brightness of the pixel part 110.

In the above embodiment, the first transistor 51 in which the current supply unit 127 is formed of a P-type transistor and the second transistor 53 is formed of an N-type transistor are illustrated, but the embodiment of the present invention is not limited to this, and the current supply unit 127 may be formed by implementing the first transistor 51 and the second transistor 53 by other transistors and forming a corresponding operational amplifier.

Fig. 7 is a schematic diagram of a pixel PX circuit according to an embodiment of the invention.

As shown in fig. 7, the pixel PX may include: a pixel circuit including the light emitting element ED, and the first pixel circuit 40 and the second pixel circuit 50 connected thereto. The first pixel circuit 40 may be a low voltage driving circuit, and the second pixel circuit 50 may be a high voltage driving circuit. The first pixel circuit 40 may be implemented with a majority logic circuit.

The light emitting element ED selectively emits light or does not emit light based on the logical level of the bit value of the image data obtained from the data driving section 125 for each sub-frame in one frame period, and adjusts the light emitting period in one frame to display the gradation.

The first pixel circuit 40 stores bit values of n-bit data applied from the data driving section 125 during data recording for each subframe, and generates a first PWM signal based on the n-bit values and the n clock signals during light emission. The first pixel circuit 40 may include a PWM controller 401 and a memory 403.

The PWM controller 401 generates a first PWM signal based on the clock signal CK input from the clock generating section 120 and the bit value of the image data read from the memory 403 during the light emission period. The PWM controller 401 may generate the first PWM signal after reading the corresponding bit value of the image data from the memory 403 when the clock signal is input from the clock generating section 120.

The PWM controller 401 may control the pulse width of the first PWM signal based on the sub-frame unit image data bit value and the clock signal width. For example, when the image data bit value is 1, the PWM signal pulse corresponding to the clock signal width is turned on and when the image data bit value is 0, the PWM signal pulse corresponding to the clock signal width is turned off. That is, the on-time of the pulse output of the PWM signal and the off-time of the pulse output may be determined by the clock signal width signal length. The PWM controller 401 may include one OR more logic circuits, e.g., OR gate circuits, etc., comprised of one OR more transistors.

The memory 403 can receive and store n-bit data applied from the data driver 125 through the data lines DL in advance in the data recording period of each sub-frame in synchronization with the start signal of the sub-frame. For a fixed image, the image data previously held in the memory 403 may be continuously applied to image display during most frames before image upgrade or refresh.

The logical levels of the bit values of the n-bit data may be input from the data driver 125 to the memory 403 in a predetermined order. The memory 403 can hold at least 1 bit of data. In one embodiment, memory 403 may be an n-bit memory. The memory 403 may record n bit values of n-bit data during data recording of a subframe. The memory 403 may be formed with one or a plurality of transistors. The memory 503 may be formed of a random access memory RAM, for example, an SRAM or a DRAM.

When the memory 403 is supplied with m-bit data that has not been converted, the memory 403 may have a capacity necessary for storing the m-bit data, which may be a limiting factor in downsizing the pixel. If the memory 403 has 1 bit, the pixel needs to be driven by a plurality of sub-frames, which results in an increase in driving frequency, which increases power consumption, and thus may be a limiting factor for a product using a battery. In addition, each subframe is allocated with a different time. In contrast, the memory 403 in the embodiment of the present invention uses an n-bit memory smaller than m bits, thereby reducing the memory capacity and also reducing the pixel size. In addition, using an n-bit memory, the number of subframes can be reduced compared to a 1-bit memory, so that the driving frequency can be appropriately maintained.

The second pixel circuit 50 adjusts the light emitting and non-light emitting states of the light emitting element ED in response to the control signals applied to each of the plurality of sub-frames by the first pixel circuit 40 during one frame. The control signal may be a PWM signal. The second pixel circuit 50 may include a first transistor 501, a second transistor 503, and a level shifter 505 electrically connected to the current supply section 127.

The first transistor 501 may output a driving current. In the first transistor 501, a gate is connected to the current supply unit 127, a first terminal is connected to a power supply voltage VDD supply source, and a second terminal is connected to a first terminal of the second transistor 503. The gate of the first transistor 501 is connected to the gate of the first transistor 51 of the current supply section 127 to constitute the current supply section 127 and a current mirror circuit. Thus, when the first transistor 51 of the current supply unit 127 is turned on, a drive current corresponding to the current Iref formed in the current supply unit 127 is supplied to the turned-on first transistor 501. The driving current may be the same as the current Iref flowing through the current supply section 127.

The second transistor 503 can transmit or cut off the driving current to the light emitting element ED according to the PWM signal. The gate of the second transistor 503 is connected to the output terminal of the level shifter 505, the first terminal thereof is connected to the second terminal of the first transistor 501, and the second terminal thereof is connected to the light emitting element ED.

The second transistor 503 may be turned on or off according to a voltage output from the level shift 505. The light emission time of the light emitting element ED can be adjusted according to the on or off time of the second transistor 503. In the embodiment of fig. 7, when the on level signal is applied to the gate, the second transistor 503 transmits the driving current Iref output from the first transistor 501 to the light emitting element ED after being turned on at a low level, so that the light emitting element ED emits light. In the embodiment of fig. 7, when the off level signal is applied to the gate, the second transistor 503 is turned off at a high level, and then the driving current Iref outputted from the first transistor 501 is turned off to the light emitting element ED, so that the light emitting element ED emits no light. In one frame period, the light emission time and the non-light emission time of the light emitting element ED are controlled in accordance with the on time and the off time of the second transistor 503 to express the Color Depth (Color Depth) of the pixel portion 110.

The level shifter 505 is connected to an output terminal of the PWM (Pulse Width modulation) controller 401 of the first pixel circuit 40, and converts a voltage level of the first PWM signal output from the PWM controller 401 to generate a second PWM signal. The level shifter 505 may generate: the sum of the first PWM signal and the on-voltage level signal of the second transistor 503 is turned on, and is converted into a second PWM signal of an off-level signal capable of turning off the second transistor 503. If the first PWM signal output by the PWM controller 401 is sufficient to drive the second transistor 503, the level shifter 505 may be omitted.

The pulse voltage level of the second PWM signal output by the level shifter 505 may be higher than the pulse voltage level of the first PWM signal, and the level shifter 505 may include a boosting circuit that boosts the input voltage. The level shifter 505 may be formed of a plurality of transistors.

The on time and the off time of the second transistor 503 during one frame are determined according to the pulse width of the first PWM signal.

In the embodiment of fig. 7, the current supply section 127 is connected to one pixel PX, but the current supply section 127 may be shared by a plurality of pixels PX. For example, as shown in fig. 8, the first transistor 51 of the current supply unit 127 is electrically connected to the first transistor 501 of each of all the pixels PX of the pixel unit 110, thereby forming a current mirror circuit. In another embodiment, the current supply section 127 is provided for each row, and the current supply section 127 for each row may be shared by a plurality of pixels PX in the same row.

In the foregoing embodiment, the embodiment in which the pixel is formed of the P-type transistor is illustrated, but this is not limited to the embodiment of the present invention, and the pixel may be formed of an N-type transistor, in which case the pixel may be driven by a level-inversion signal of a signal applied to the P-type transistor.

Fig. 9 is an explanatory diagram of bit data division according to an embodiment of the present invention, and fig. 10 is an explanatory diagram of clock signal driving time according to an embodiment of the present invention. Fig. 10 is a clock signal driving time applied to the first row.

As shown in fig. 9 and 10, one frame is composed of two subframes, and a PWM signal is generated from two 6-bit data generated by dividing 10-bit data in each subframe.

As shown in fig. 9, 1 of the leftmost bit of the bit sequence 1011100110 of 10-bit data of the pixel PX is an MSB, and 0 of the rightmost bit is an LSB. The 10-bit data may be split into two 6-bit data multi-bit columns. By the majority bit combination, a time difference between the first subframe SF1 and the second subframe SF2, in particular, a difference between the emission time ET of the first subframe SF1 and the emission time ET of the second subframe SF2, may be minimized.

The first 6 bits of data is a combination 101110 of 10 bits of data MSB/MSB-1 MSB/MSB-2/MSB 7/MSB-8/LSB. The second 6 bits of data is a combination 101100 of 10 bits of data MSB/MSB-1 MSB/MSB-3/MSB-4/MSB-5/MSB-6. Here, "+" indicates that the relevant bit allocation corresponds to 1/2 of the time allocated from 10 bits of data. That is, the leftmost bit 1 of the first 6-bit data and the second 6-bit data means the first MSB1 of the 10-bit data, and is a common bit from the same position of the 10-bit data, and each allocation corresponds to half of the allocation time to the MSB. Similarly, the 0 of the second left bit of the first 6-bit data and the second 6-bit data is 0 of the second MSB-1 of the 10-bit data, and is a common bit from the same position of the 10-bit data, and each allocation corresponds to half of the time allocated to the MSB 1.

The first left 6-bit data is image data of the first subframe SF1, and the second right 6-bit data is image data of the second subframe SF 2.

As shown in fig. 10, the pixel PX may be driven with a data recording period DT and a light emitting period ET for each sub-frame of one frame. Since the ON Time of the emission period ET is the Time main body of the subframe, the following subframe Time and emission period may be used in combination. The time of the first subframe and the time of the second subframe, although different, may be approximated.

During the data recording period DT of the first sub-frame SF1, the bit value for storing the n-bit data from the data driving section 125 can be recorded in the memory 503 in the pixel PX. That is, the memory 503 may record the bit sequence 101110 of the first 6-bit data of fig. 9 in the pixel PX.

After the light emission time ET of the first sub-frame SF1 is synchronized with the 6-bit data, the first to sixth clock signals CK1 to CK6 may be applied to the PWM controller 501, and the PWM controller 501 generates the PWM signals based on the bit values of the 6-bit data recorded in the memory 503 and the first to sixth clock signals CK1 to CK 6.

The first to sixth clock signals CK1 to CK6 of the first sub-frame SF1 may be applied at the same time as the time each allocated to each bit of the 6-bit data. For example, the first clock signal CK1 is applied during a period in which half of time T/2 is allocated to MSB 1/2xT/2, the second clock signal CK2 is applied during a period in which half of time T/22 is allocated to MSB-1 and 1/2 xT/22, the third clock signal CK3 is applied during a period in which time T/23 is allocated to MSB-2, the fourth clock signal CK4 is applied during a period in which time T/28 is allocated to MSB-7, the fifth clock signal CK5 is applied during a period in which time T/29 is allocated to MSB-8, and the sixth clock signal CK6 is applied during a period in which time T/210 is allocated to LSB.

During the data recording period DT of the second sub-frame SF2, the bit value of the n-bit data from the data driving section 125 can be recorded in the memory 503 in the pixel PX. That is, the bit sequence 101100 of the second 6-bit data of fig. 9 may be recorded to the memory 503 in the pixel PX.

After the light emission time ET of the second sub-frame SF2 is synchronized with the 6-bit data, the first to sixth clock signals CK1 to CK6 may be applied to the PWM controller 501, and the PWM controller 501 generates the PWM signals based on the bit values of the 6-bit data recorded in the memory 503 and the first to sixth clock signals CK1 to CK 6.

The first to sixth clock signals CK1 to CK6 of the second sub-frame SF2 may be applied at the same time as the time each allocated to each bit of the 6-bit data. For example, the first clock signal CK1 is applied during a period in which half of time T/2 is allocated to MSB 1/2xT/2, the second clock signal CK2 is applied during a period in which half of time T/22 is allocated to MSB-1 and 1/2 xT/22, the third clock signal CK3 is applied during a period in which time T/24 is allocated to MSB-2, the fourth clock signal CK4 is applied during a period in which time T/25 is allocated to MSB-4, the fifth clock signal CK5 is applied during a period in which time T/26 is allocated to MSB-5, and the sixth clock signal CK6 is applied during a period in which time T/27 is allocated to MSB-6.

In each of the first sub-frame SF1 and the second sub-frame SF2, the PWM controller 501 reads the bit values of the data of 6 bits from the memory 503 and controls the pulse width of the PWM signal based on the signal width of the clock signal CK and the bit values of the bit data. The PWM controller 501 generates the PWM signal PWM based on the clock signal CK and the bit values of the bit data output to the first and second sub-frames SF1 and SF 2.

Fig. 11 is an explanatory diagram of bit data division according to another embodiment of the present invention, and fig. 12 is an explanatory diagram of clock signal driving time according to another embodiment of the present invention. Fig. 12 is a clock signal driving time applied to the first row.

As shown in fig. 11 and 12, one frame is composed of three subframes, and here, an example in which the PWM signal is generated by three 4-bit data generated by dividing 10-bit data in each subframe is illustrated.

As shown in fig. 11, 1 of the leftmost bit of the bit sequence 1011100110 of 10-bit data of the pixel PX is an MSB, and 0 of the rightmost bit is an LSB. The 10-bit data may be divided by three 4-bit data. The time difference between the first to third subframes SF1 to SF3, particularly, the light emitting time ET difference of the first to third subframes SF1 to SF3 can be minimized by bit data combination.

The first 4 bits of data is a combination 1110 of 10 bits of data MSB/MSB-2 MSB/4 LSB. The second 4 bits of data is a combination 1101 of 10 bits of data MSB/MSB-2 MSB-5 MSB 8. The third 4-bit data is a combination 0101 of 10-bit data MSB-1/MSB-3/MSB 6/MSB-7. Here, "+" indicates that the relevant bit allocation corresponds to 1/2 of the time allocated from 10 bits of data. That is, the leftmost bit 1 of the first 4-bit data and the second 4-bit data means the first MSB1 of the 10-bit data, and is a common bit from the same position of the 10-bit data, and each bit is allocated half of the time allocated to the MSB. Similarly, the 1 of the first 6-bit data and the second left-hand bit of the second 6-bit data refers to the 1 of the third bit MSB-2 of the 10-bit data, which is a common bit from the same position of the 10-bit data, and each is allocated half of the allocation time to the MSB-2.

The first left 4-bit data is image data of the first subframe SF1, the first middle 4-bit data is image data of the second subframe SF2, and the third right 4-bit data is image data of the third subframe SF 3.

As shown in fig. 12, the pixel PX may be driven with a data recording period DT and a light emitting period ET for each sub-frame of one frame. The time of the first subframe and the time of the second subframe, although different, may be approximated.

During the data recording period DT of the first sub-frame SF1, the bit value of the n-bit data from the data driving section 125 can be recorded in the memory 503 in the pixel PX. That is, the first bit sequence 1110 of the 4-bit data of fig. 11 may be recorded in the memory 503 in the pixel PX.

The first to fourth clock signals CK1 to CK4 are applied to the PWM controller 501 in synchronization with the 4-bit data at the light emission time ET of the first sub-frame SF1, and the PWM controller 501 may generate the PWM signal based on the bit values of the 4-bit data recorded in the memory 503 and the first to fourth clock signals CK1 to CK 4.

The first to fourth clock signals CK1 to CK4 of the first subframe SF1 may be applied at the same time as the time each allocated to each bit of the 4-bit data. For example, the first clock signal CK1 is applied during a period in which half of time T/2 1/2xT/2 is allocated to MSB, the second clock signal CK2 is applied during a period in which half of time T/23 is allocated to MSB-2, 1/2xT/23 is allocated to MSB-23, the third clock signal CK3 is applied during a period in which time T/25 is allocated to MSB-4, and the fourth clock signal CK4 is applied during a period in which time T/210 is allocated to LSB.

During the data recording period DT of the second sub-frame SF2, the bit value of the n-bit data from the data driving section 125 can be recorded in the memory 503 in the pixel PX. That is, the bit sequence 1101 of the second 4-bit data of fig. 11 can be recorded in the memory 503 in the pixel PX.

The first to fourth clock signals CK1 to CK4 are applied to the PWM controller 501 in synchronization with the 4-bit data at the light emitting time ET of the second sub-frame SF2, and the PWM controller 501 may generate the PWM signal based on the bit values of the 4-bit data recorded in the memory 503 and the first to fourth clock signals CK1 to CK 4.

The first to fourth clock signals CK1 to CK4 of the second subframe SF2 may be applied at the same time as the time each allocated to each bit of 4-bit data. For example, the first clock signal CK1 is applied during a period in which half of time T/2 1/2xT/2 is allocated to MSB, the second clock signal CK2 is applied during a period in which half of time T/23 is allocated to MSB-2, 1/2xT/23 is allocated to MSB-23, the third clock signal CK3 is applied during a period in which time T/26 is allocated to MSB-5, and the fourth clock signal CK4 is applied during a period in which time T/29 is allocated to MSB-8.

During the data recording period DT of the third sub-frame SF3, the bit value of the n-bit data from the data driving section 125 can be recorded in the memory 503 in the pixel PX. That is, the bit sequence 0101 of the third 4-bit data in fig. 11 may be recorded in the memory 503 in the pixel PX.

The first to fourth clock signals CK1 to CK4 are applied to the PWM controller 501 in synchronization with the 4-bit data at the light emitting time ET of the third subframe SF3, and the PWM controller 501 may generate the PWM signal based on the bit values of the 4-bit data recorded in the memory 503 and the first to fourth clock signals CK1 to CK 4.

The first to fourth clock signals CK1 to CK4 of the third subframe SF3 may be applied at the same time as the time each allocated to each bit of 4-bit data. For example, the first clock signal CK1 is applied during a period in which time T/22 is allocated to MSB-1, the second clock signal CK2 is applied during a period in which time T/24 is allocated to MSB-3, the third clock signal CK3 is applied during a period in which time T/27 is allocated to MSB-6, and the fourth clock signal CK4 is applied during a period in which time T/28 is allocated to MSB-7.

In each of the first to third sub-frames SF1 to SF3, the PWM controller 501 reads the bit value of the 4-bit data from the memory 503 and controls the pulse width of the PWM signal based on the signal width of the clock signal CK and the bit value of the bit data. The PWM controller 501 generates the PWM signal PWM based on the clock signal CK and the bit values of the bit data output from the first to third sub-frames (SF 1 to SF 3).

Fig. 13 is a diagram illustrating bit data division according to another embodiment of the present invention, and fig. 14 is a diagram illustrating clock signal driving timing according to another embodiment of the present invention. Fig. 14 is a clock signal driving time applied to the first row.

As shown in fig. 13 and 14, one frame is composed of two subframes, and a PWM signal is generated from two 5-bit data generated by dividing 10-bit data in each subframe.

As shown in fig. 13, 1 of the leftmost bit of the bit sequence 1011100110 of 10-bit data of the pixel PX is an MSB, and 0 of the rightmost bit is an LSB. The 10-bit data may be divided by two 5-bit data. By the plurality of bit combinations, a time difference of the first subframe SF1 and a time difference of the second subframe SF2, and particularly, a light emitting time ET of the first subframe SF1 and a light emitting time ET of the second subframe SF2 can be minimized.

The first 5 bits of data are 10 bits of data MSB/MSB-6/MSB-7/MSB8/LSB combined 10110. The second 5-bit data is a combination 01110 of 10-bit data MSB-1/MSB 2/MSB-3/MSB-4/MSB-5.

The first left 5-bit data is image data of the first subframe SF1, and the second right 5-bit data is image data of the second subframe SF 2.

As shown in fig. 14, the pixel PX may be driven with a data recording period DT and a light emitting period ET for each sub-frame of one frame. The ON Time of the emission period ET is a Time of a subframe, and the Time of the first subframe and the Time of the second subframe are different but may be similar.

During the data recording period DT of the first sub-frame SF1, the bit value of the n-bit data from the data driving section 125 can be recorded in the memory 503 in the pixel PX. That is, the bit sequence 10110 of the first 5-bit data of fig. 13 may be recorded in the memory 503 in the pixel PX.

At the light emission time ET of the first sub-frame SF1, the first to fifth clock signals CK1 to CK5 are applied to the PWM controller 501 in synchronization with the 5-bit data, and the PWM controller 501 generates the PWM signal based on the bit values of the 5-bit data recorded in the memory 503 and the first to fifth clock signals CK1 to CK 5.

The first to fifth clock signals CK1 to CK6 of the first sub-frame SF1 may be applied at the same time as the time each allocated to each bit of the 5-bit data. For example, the first clock signal CK1 is applied during a period in which the time T/2 is allocated to the MSB, the second clock signal CK2 is applied during a period in which the time T/27 is allocated to the MSB-6, the third clock signal CK3 is applied during a period in which the time T/28 is allocated to the MSB-6, the fourth clock signal CK4 is applied during a period in which the time T/28 is allocated to the MSB-7, and the fifth clock signal CK5 is applied during a period in which the time T/210 is allocated to the LSB.

During the data recording period DT of the second sub-frame SF2, the bit value of the n-bit data from the data driving section 125 can be recorded in the memory 503 in the pixel PX. That is, the bit sequence 01110 of the second 5-bit data of fig. 13 can be recorded in the memory 503 in the pixel PX.

At the light emission time ET of the second sub-frame SF2, the first to fifth clock signals CK1 to CK5 are applied to the PWM controller 501 in synchronization with the 5-bit data, and the PWM controller 501 generates the PWM signal based on the bit values of the 5-bit data recorded in the memory 503 and the first to fifth clock signals CK1 to CK 5.

The first to fifth clock signals CK1 to CK5 of the second subframe SF2 may each be applied at the same time as the time allocated to each bit of the 5-bit data. For example, the first clock signal CK1 is applied during a period in which time T/22 is allocated to MSB-1, the second clock signal CK2 is applied during a period in which time T/23 is allocated to MSB-2, the third clock signal CK3 is applied during a period in which time T/24 is allocated to MSB-3, the fourth clock signal CK4 is applied during a period in which time T/25 is allocated to MSB-4, and the fifth clock signal CK5 is applied during a period in which time T/26 is allocated to MSB-5.

In each of the first sub-frame SF1 and the second sub-frame SF2, the PWM controller 501 reads the bit value of the 5-bit data from the memory 503, and controls the pulse width of the PWM signal based on the signal width of the clock signal CK and the bit value of the bit data. The PWM controller 501 generates the PWM signal PWM based on the clock signal CK and the bit values of the bit data output to the first and second sub-frames SF1 and SF 2.

In the embodiments of fig. 9 to 14, when the bit value is 1, the PWM controller 501 may output a pulse having a width corresponding to the clock signal CK. When the bit value is 0, the PWM controller 501 does not output a pulse having a width corresponding to the clock signal CK. In another embodiment, the PWM controller 501 does not output a pulse having a width corresponding to the clock signal CK when the bit value is 1, and outputs a pulse having a width corresponding to the clock signal CK when the bit value is 0.

The light emitting element ED may emit or not emit light according to the PWM signal pulse output during one frame. The light emitting element ED may emit light for a time corresponding to the pulse width when the pulse output is turned on. The light emitting element ED may not emit light for a time equivalent to when the pulse output is turned off.

Embodiments of the present invention may be configured with a miniature LED display device.

The pixel of the embodiment of the present invention includes a pixel circuit that switches a current drive current source, and a switching signal can be generated by combining a time signal expressing a gray scale (gradation) and digital data.

The pixel of the embodiment of the invention can store digital data in a plurality of sub-frame divisions in one frame so as to reduce the number of memory bits required per pixel.

The embodiment of the invention has the memory in the pixel, so that the current drive can be carried out, and the drive part only needs to transmit a simple drive pulse to the pixel part in a fixed image, thereby effectively reducing the power consumption.

Embodiments of the present invention can use a high bias current at a low gradation by PWM driving, thereby ensuring excellent matching characteristics between pixels and realizing a high Color Depth (Color Depth) even in a small pixel size.

The embodiment of the invention can set the gamma value through digital batch processing, and can simply adjust the brightness by using the current mirror circuit under the condition of keeping the gamma value.

According to the embodiment of the invention, the high-resolution micro LED display device can be realized by forming the circuit mainly comprising the low-voltage transistor.

The present invention has been described with reference to one embodiment shown in the accompanying drawings, which are intended to be illustrative only, and it is to be understood that various other modifications and equivalent embodiments may be devised by those skilled in the art. Therefore, the true scope of the invention should be determined only by the claims.

Claims

1. A pixel includes a light emitting element and a pixel circuit connected to the light emitting element, wherein a plurality of sub-frames constituting one frame each include a data recording period and a light emitting period,

a memory for receiving and storing a corresponding bit sequence in a bit sequence of a plurality of n-bit data generated by combining m bits constituting a bit sequence of m-bit data with n bits smaller than m bits, and a controller for generating a control signal based on n clock signals and the n bit values of the stored corresponding bit sequence in the light emission period of each subframe, the pixel circuit including a first pixel circuit characterized by the above items; and

a second pixel circuit for adjusting the light emission and non-light emission of the light emitting element in response to the control signal during the light emission period of each sub-frame;

the number of bit columns of the n-bit data is the same as the number of the subframes;

the light emission time of each sub-frame is the sum of the time allocated to each bit of the corresponding bit sequence;

the n-bit data is a pixel combined with each of the n bits among the m bits having the smallest difference in light emission time among the plurality of subframes.

2. The pixel according to claim 1, wherein n is (m/2) +1 or (m/2) -1, two bit columns of the n-bit data include at least one specific bit as a common bit in the bit columns of the m-bit data, and wherein a time allocated to the common bit is a half of a pixel of the specific bit allocation time in the bit columns of the m-bit data.

3. The pixel according to claim 1, wherein n is m/2, the bit sequence of the n-bit data does not include bits at the same position in the m bits, and the bit sequence of the n-bit data is a pixel whose sum of the bit allocation times is approximate to each other.

4. The pixel according to claim 1, wherein the first pixel circuit, a first transistor which outputs a drive current; a second transistor for transmitting or disconnecting the driving current to the light emitting element according to the control signal; and a level shifter converting a voltage level of the control signal, including the pixels of the above items.

5. A micro LED display device is characterized in that a light emitting element and a pixel part which comprises a pixel circuit connected with the light emitting element and is provided with a plurality of pixels are arranged; a data driving unit for generating a plurality of bit sequences of n-bit data by combining n bits smaller than m bits among m bits constituting a bit sequence of m-bit data, and outputting the corresponding bit sequences to the pixels in the bit sequences for outputting the plurality of n-bit data to each of a plurality of sub-frames constituting one frame; and a clock generating section for supplying a clock signal to a pixel after each sub-frame corresponds to each bit of the corresponding bit sequence after a data recording period and a light emitting period, wherein the pixel circuit of the pixel receives and stores the corresponding bit sequence during the data recording period in each sub-frame, and the pixel circuit generates a control signal based on n bit values of the stored corresponding bit sequence and n clock signals during the light emitting period in each sub-frame; and a micro LED display device including a second pixel circuit for adjusting light emission and non-light emission of the light emitting element in response to the control signal in the light emission period of each sub-frame, wherein the number of bit sequences of the n-bit data is equal to the number of the sub-frames, the light emission time of each sub-frame is a combination of times allocated to each bit of the corresponding bit sequence, and the n-bit data is a combination of n bits among the m bits having the smallest difference in light emission time among the plurality of sub-frames.

6. The pixel according to claim 5, wherein n is (m/2) +1 or (m/2) -1, two bit columns of the n-bit data include at least one specific bit as a common bit in the bit columns of the m-bit data, wherein a time allocated to the common bit is a half micro LED display of the time allocated to the specific bit in the bit columns of the m-bit data.

7. The pixel according to claim 5, wherein n is m/2, the bit sequence of the n-bit data does not include bits at the same position in the m bits, and the bit sequence of the n-bit data is a micro LED display device in which the bit sequence and the bit allocation time are approximate to each other.