KR102582159B1 - Light Emitting Display - Google Patents

Abstract

The present invention provides a light emitting display device including a display panel, a data driver, and a scan driver. The display panel displays an image. The data driver supplies data voltage through the data line of the display panel. The scan driver supplies a scan signal through the scan line of the display panel. The display panel has subpixels that store data voltages in response to the Nth scan signal applied through the Nth scan line and the N-1th scan signal applied through the N-1th scan line.

Description

Light emitting display device {Light Emitting Display}

The present invention relates to a light emitting display device.

As information technology develops, the market for display devices, which are a connecting medium between users and information, is growing. Accordingly, the use of display devices such as light emitting display (LED), quantum dot display (QDD), and liquid crystal display (LCD) is increasing.

The display devices described above include a display panel including subpixels, a driver that outputs a driving signal to drive the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

The above display devices can display images by transmitting light or emitting light directly when driving signals, such as scan signals and data signals, are supplied to the subpixels formed on the display panel. .

Meanwhile, among the display devices described above, the light emitting display device has many advantages such as electrical and optical characteristics such as fast response speed, high brightness, and wide viewing angle, as well as mechanical characteristics that can be implemented in a flexible form. However, light emitting display devices still have room for improvement in terms of display panel composition, so continuous research in this regard is necessary.

The present invention to solve the problems of the above-described background technology reduces the number of scan lines when implementing a display panel based on an internal compensation circuit and also provides sufficient sampling time. Additionally, the present invention reduces the flicker occurrence rate, is advantageous for low-speed driving, or reduces circuit density. In addition, the present invention provides advantages in implementing mid-sized or higher models or high-resolution models in addition to narrow bezels of display panels.

As a means of solving the above-described problems, the present invention provides a light emitting display device including a display panel, a data driver, and a scan driver. The display panel displays an image. The data driver supplies data voltage through the data line of the display panel. The scan driver supplies a scan signal through the scan line of the display panel. The display panel has subpixels that store data voltages in response to the Nth scan signal applied through the Nth scan line and the N-1th scan signal applied through the N-1th scan line.

In another aspect, the present invention provides a light emitting display device including a display panel, a data driver, and a scan driver. The display panel displays an image. The data driver supplies data voltage through the data line of the display panel. The scan driver supplies a scan signal through the scan line of the display panel. The display panel has a subpixel that stores a data voltage during a section where the Nth scan signal applied through the Nth scan line and the N-1th scan signal applied through the N-1th scan line overlap.

The subpixel may include a 1A transistor that is turned on in response to the Nth scan signal of the Nth scan line, and a 1B transistor that is turned on in response to the N-1 scan signal of the N-1th scan line.

The 1A transistor and the 1B transistor may have a period in which they are turned on at the same time.

The turn-on time of the 1B transistor may be earlier than that of the 1A transistor.

The 1A transistor has its gate electrode connected to the N scan line and the first electrode connected to the first data line, and the 1B transistor has its gate electrode connected to the N-1 scan line and the second electrode of the 1A transistor. The first electrode may be connected.

The display panel further includes at least two switches connected to channels of the data driver, wherein the at least two switches have a gate electrode connected to the first selection signal line, a first electrode connected to the first channel of the data driver, and 1A data. A first switch with a second electrode connected to a line, a gate electrode connected to a second selection signal line, a first electrode connected to the first channel of the data driver, and a second switch with a second electrode connected to the 1B data line. It can be included.

The display panel includes a first subpixel connected to a 1A data line and an 11th subpixel connected to a 1B data line, and the first subpixel and the 11th subpixel may be adjacent to each other up and down or left and right on the display panel. .

The subpixel includes a 1A transistor whose gate electrode is connected to the N-th scan line and the first electrode connected to the first data line, and a gate electrode connected to the N-1th scan line and a first electrode connected to the second electrode of the 1A transistor. A 1B transistor with an electrode connected to it, a capacitor with one end connected to the second electrode of the 1B transistor, a driving transistor with a gate electrode connected to the other end of the capacitor and a first electrode connected to the first power line, and an N-1 scan. A second transistor with a gate electrode connected to the line, a first electrode connected to the other end of the capacitor, and a second electrode connected to the second electrode of the driving transistor, and a gate electrode connected to the light emitting signal line and a first electrode to one end of the capacitor. A third transistor connected to this and the second electrode connected to the reference line, a fourth transistor whose gate electrode is connected to the light emitting signal line and the first electrode connected to the second electrode of the driving transistor, and a gate to the N-1th scan line A fifth transistor in which electrodes are connected, the first electrode is connected to the reference line, the second electrode is connected to the second electrode of the fourth transistor, the anode electrode is connected to the second electrode of the fourth transistor, and the cathode is connected to the second power line. It may include a light emitting diode to which an electrode is connected.

The subpixel includes a 1A transistor whose gate electrode is connected to the N-th scan line and the first electrode connected to the first data line, and a gate electrode connected to the N-1th scan line and a first electrode connected to the second electrode of the 1A transistor. A 1B transistor with an electrode connected to it, a capacitor with one end connected to the second electrode of the 1B transistor, a driving transistor with a gate electrode connected to the other end of the capacitor and a first electrode connected to the first power line, and an N-1 scan. A 2A transistor with a gate electrode connected to the line and a first electrode connected to the other end of the capacitor, a gate electrode connected to the N-1 scan line, a first electrode connected to the second electrode of the 2A transistor, and a driving transistor. A 2B transistor with a second electrode connected to the second electrode, a third transistor with a gate electrode connected to the light emitting signal line, a first electrode connected to one end of a capacitor, and a second electrode connected to a reference line, and a third transistor with a gate electrode connected to the light emitting signal line. A fourth transistor whose gate electrode is connected to the second electrode of the driving transistor and whose first electrode is connected to the second electrode of the driving transistor, whose gate electrode is connected to the N-1 scan line and the first electrode connected to the reference line and the second electrode of the fourth transistor It may include a fifth transistor with a second electrode connected to the light emitting diode, an anode electrode connected to the second electrode of the fourth transistor, and a cathode electrode connected to the second power line.

The present invention has the effect of reducing the number of scan lines when implementing a display panel based on an internal compensation circuit and also providing sufficient sampling time. In addition, the present invention has the effect of lowering the flicker occurrence rate and increasing the area occupied by the capacitor compared to the previous one to be advantageous for low-speed driving, or lowering the density of the circuit to increase process yield. In addition, the present invention reduces the area occupied by the shift register, which not only enables a narrow bezel of the display panel, but also provides advantages when implementing mid-sized or higher models or high-resolution models.

1 is a schematic block diagram of a light emitting display device according to a first embodiment of the present invention.
2 is a schematic circuit diagram of a subpixel.
3 is an example cross-sectional view of a display panel.
Figure 4 is a first configuration example diagram of a device related to a gate-in-panel type scan driver.
Figure 5 is a second configuration example of a device related to a gate-in-panel type scan driver.
Figure 6 is a diagram showing an example of the arrangement of a shift register in a gate-in-panel scan driver.
Figure 7 is a diagram showing a subpixel with a compensation circuit according to the first embodiment of the present invention.
FIG. 8 is a diagram showing scan signals applied to the subpixel shown in FIG. 7 and node voltages at both ends of a capacitor.
Figure 9 is a diagram showing a subpixel with a compensation circuit according to a second embodiment of the present invention.
FIG. 10 is a diagram showing scan signals applied to the subpixel shown in FIG. 9 and node voltages at both ends of a capacitor.
Figure 11 is an example layout of a subpixel based on the second embodiment of the present invention.
Figure 12 is a diagram for explaining secondary effects according to the second embodiment of the present invention.
Figure 13 is a diagram showing subpixels and switches having a compensation circuit according to a third embodiment of the present invention.
FIG. 14 is a diagram showing selection signals applied to the switches shown in FIG. 13 and scan signals and data voltages applied to subpixels.
Figure 15 is a diagram showing subpixels and switches having a compensation circuit according to a fourth embodiment of the present invention.
FIG. 16 is a diagram showing selection signals applied to the switches shown in FIG. 15 and scan signals and data voltages applied to subpixels.
Figure 17 is an example layout of a subpixel based on the fourth embodiment of the present invention.
Figure 18 is a diagram for explaining secondary effects according to the fourth embodiment of the present invention.
19 to 21 are diagrams for explaining the advantages of the display panel implementation method of the third and fourth embodiments of the present invention.

Hereinafter, specific details for implementing the present invention will be described with reference to the attached drawings.

The light emitting display device according to the present invention is implemented in televisions, video players, personal computers (PCs), home theaters, smartphones, etc. Light emitting display devices are implemented based on inorganic light emitting diodes or organic light emitting diodes. However, below, for convenience of explanation, an implementation based on an organic light emitting diode will be described as an example.

In addition, the thin film transistor described below, excluding the gate electrode, may be called a source electrode and a drain electrode or a drain electrode and a source electrode depending on the type (N-type or P-type), so as not to limit this. It is explained in terms of the first electrode and the second electrode.

<First embodiment>

FIG. 1 is a schematic block diagram of a light emitting display device according to a first embodiment of the present invention, FIG. 2 is a schematic circuit diagram of a subpixel, FIG. 3 is an exemplary cross-section of a display panel, and FIG. 4 is a gate Figure 5 is a first configuration example diagram of a device related to an in-panel scan driver, Figure 5 is a second configuration example diagram of a device related to a gate-in-panel scan driver, and Figure 6 is an arrangement of a shift register in a gate-in-panel scan driver. This is a drawing showing an example.

As shown in FIG. 1, the light emitting display device according to the first embodiment of the present invention includes an image processing unit 110, a timing control unit 120, a data driver 130, a scan driver 140, and a power supply unit 180. and a display panel 150.

The image processing unit 110 outputs a data enable signal (DE) in addition to a data signal (DATA) supplied from the outside. In addition to the data enable signal DE, the image processor 110 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, but these signals are omitted for convenience of explanation.

The timing control unit 120 receives a data enable signal (DE) or a driving signal including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, as well as a data signal (DATA) from the image processing unit 110. The timing control unit 120 provides a gate timing control signal (GDC) for controlling the operation timing of the scan driver 140 and a data timing control signal (DDC) for controlling the operation timing of the data driver 130 based on the driving signal. etc. are printed.

The data driver 130 samples and latches the digital data signal (DATA) supplied from the timing control unit 120 in response to the data timing control signal (DDC) supplied from the timing control unit 120, and then sets the gamma reference voltage. Based on this, it is converted into analog data voltage and output. The data driver 130 outputs a data voltage through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an integrated circuit (IC).

The scan driver 140 outputs a scan signal in response to the gate timing control signal (GDC) supplied from the timing control unit 120. The scan driver 140 outputs a scan signal consisting of a scan high voltage and a scan low voltage through the scan lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or is formed in the display panel 150 using a gate in panel method.

The power supply unit 180 is connected to the first power line (EVDD) and the second power line (EVSS) disposed on the display panel 150. The power supply unit 180 outputs a first potential power (high potential voltage) and a second potential power (low potential voltage) through the first power line (EVDD) and the second power line (EVSS). The first potential power (high potential voltage) and the second potential power (low potential voltage) transmitted through the first power line (EVDD) and the second power line (EVSS) are connected to the subpixels (SP) of the display panel 150. ) is approved.

The display panel 150 displays images in response to power supplied from the power supply unit 180 and data voltages and scan signals supplied from the data driver 130 and the scan driver 140. The display panel 150 includes subpixels (SP) that operate to display images.

The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel, or include a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different light emission areas depending on light emission characteristics.

As shown in FIG. 2, one subpixel SP is electrically connected to the data line DL1, the scan line GL1, the first power line EVDD, and the second power line EVSS. One subpixel (SP) includes an organic light emitting diode (OLED) that emits light and a pixel circuit (CC) that drives it.

The pixel circuit (CC) includes a switching transistor for transmitting the data voltage, a capacitor for storing the data voltage, and a driving transistor for generating a driving current based on the data voltage stored in the capacitor. The pixel circuit (CC) may further include a compensation circuit to compensate for deterioration of the driving transistor or organic light emitting diode (OLED). Descriptions related to the pixel circuit (CC) having a compensation circuit will be provided starting from FIG. 7.

As shown in FIG. 3, subpixels are formed on the display area AA of the first substrate (or thin film transistor substrate) 150a based on the circuit described in FIG. 2. Subpixels formed on the display area AA are sealed by a protective film (or protective substrate) 150b. The display area (AA) is an area that displays an image, and NA excluding this area refers to a non-display area that does not display an image. The first substrate 150a may be selected from a material having rigidity or ductility, such as glass, silicon, or polyimide.

The subpixels may be arranged horizontally or vertically in the order of red (R), white (W), blue (B), and green (G) on the display area (AA). And the subpixels may be red (R), white (W), blue (B), and green (G) into one pixel (P). However, the arrangement order of subpixels may vary depending on the light emitting material, light emitting area, composition (or structure) of the compensation circuit, etc. Additionally, subpixels can be implemented in various forms, such as red (R), blue (B), and green (G) becoming one pixel (P).

As shown in FIG. 4, the gate-in-panel scan driver 140 may include a shift register 141 and a level shifter 145. The level shifter 145 generates and outputs a plurality of clock signals (GCLK) based on the signal output from the timing control unit 120. A plurality of clock signals (GCLK) are generated and output in the form of N (N is an integer greater than or equal to 2) phases with different phases, such as, for example, 2-phase, 4-phase, and 8-phase. The shift register 141 operates based on a plurality of clock signals (GCLK) output from the level shifter 145 and outputs scan signals (Scan 1 to Scan m).

While the level shifter 145 is formed in the form of an IC, the shift register 141 is formed in the form of a thin film on the display panel using a gate-in-panel method. That is, the part of the scan driver 140 formed on the display panel is the shift register 131. Depending on the size or implementation method of the light emitting display device, the level shifter 145 may be configured in the form of a separate IC as shown in FIG. 4, or may be included inside the power supply unit 180 as shown in FIG. 5.

As shown in FIG. 6, the shift registers 130a and 130b included in the gate-in-panel scan driver are disposed in the non-display area NA of the display panel 150. The shift registers 130a and 130b may be disposed one by one in the non-display area (NA) located on the left and right sides of the display area (AA), but are not limited to this. Meanwhile, in Figure 6(a), the shift registers 130a and 130b are arranged in the left and right non-display areas (NA) of the display panel 150 as an example. However, as shown in FIG. 6(b), the shift registers 130a and 130b may be disposed in the upper and lower non-display areas (NA) of the display panel 150.

FIG. 7 is a diagram showing a subpixel having a compensation circuit according to the first embodiment of the present invention, and FIG. 8 is a diagram showing scan signals applied to the subpixel shown in FIG. 7 and node voltages at both ends of a capacitor.

As shown in FIGS. 7 and 8, the subpixel according to the first embodiment of the present invention includes a 1A transistor (T1a), a 1B transistor (T1b), a 2A transistor (T2a), and a 2B transistor (T2b). , a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a driving transistor (DT), a capacitor (CST), and an organic light emitting diode (OLED).

The 1A transistor (T1a) has a gate electrode connected to the N scan line (SCAN N), a first electrode connected to the first data line (DL1), and a second electrode connected to the first electrode of the 1B transistor (T1b). connected. The 1A transistor T1a is turned on in response to the Nth scan signal (Scan N) applied through the Nth scan line (SCAN N). The turned-on 1A transistor (T1a) serves to transfer the data voltage applied through the first data line (DL1) to the 1B transistor (T1b).

The 1B transistor (T1b) has a gate electrode connected to the N-1 scan line (SCAN N-1), a first electrode connected to the second electrode of the 1A transistor (T1a), and one end (or The second electrode is connected to the third node (N3). The 1B transistor T1b is turned on in response to the N-1th scan signal (Scan N-1) applied through the N-1th scan line (SCAN N-1). The turned-on 1B transistor (T1b) serves to apply the data voltage transmitted through the 1A transistor (T1a) to one end of the capacitor (CST).

The 2A transistor (T2a) has a gate electrode connected to the N-1 scan line (SCAN N-1), a first electrode connected to the other end (or second node N2) of the capacitor (CST), and a 2B transistor ( The second electrode is connected to the first electrode of T2b). The 2A transistor T2a is turned on in response to the N-1th scan signal (Scan N-1) applied through the N-1th scan line (SCAN N-1). The turned-on 2A transistor (T2a), together with the 2B transistor (T2b), serves to put the driving transistor (DT) in a diode connection state.

The 2B transistor (T2b) has a gate electrode connected to the N-1 scan line (SCAN N-1), a first electrode connected to the second electrode of the 2A transistor (T2a), and a second electrode of the driving transistor (DT). The second electrode is connected to the electrode (or N1, which is the first node). The 2B transistor T2b is turned on in response to the N-1th scan signal (Scan N-1) applied through the N-1th scan line (SCAN N-1). The turned-on 2B transistor (T2b), together with the 2A transistor (T2a), serves to put the driving transistor (DT) in a diode connection state.

The third transistor (T3) has a gate electrode connected to the light emitting signal line (EM) and a first electrode connected to the second electrode of the 1B transistor (T1b) and one end (or third node, N3) of the capacitor (CST). The second electrode is connected to the Roego reference line (VREF). The third transistor T3 is turned on in response to the light emission signal Em applied through the light emission signal line EM. The turned-on third transistor (T3) serves to apply the initialization voltage (Vini) applied through the reference line (VREF) to the third node (N3).

The fourth transistor (T4) has a gate electrode connected to the light emitting signal line (EM), a first electrode connected to the second electrode (or first node N1) of the driving transistor (DT), and an organic light emitting diode (OLED). The second electrode is connected to the anode electrode (or N4, the fourth node). The fourth transistor T4 is turned on in response to the light emission signal Em applied through the light emission signal line EM. The turned-on fourth transistor (T4) serves to transfer the driving current generated from the driving transistor (DT) to the organic light emitting diode (OLED).

The fifth transistor (T5) has a gate electrode connected to the N-1 scan line (SCAN N-1), a first electrode connected to the reference line (VREF), and a second electrode connected to the anode electrode of the organic light emitting diode (OLED). This is connected. The fifth transistor T5 is turned on in response to the N-1th scan signal (Scan N-1) applied through the N-1th scan line (SCAN N-1). The turned-on fifth transistor (T5) serves to apply the initialization voltage (Vini) applied through the reference line (VREF) to the anode electrode of the organic light-emitting diode (OLED).

The driving transistor DT has a gate electrode connected to the other end (or second node N2) of the capacitor CST, a first electrode connected to the first power line EVDD, and a first electrode of the fourth transistor T4. (Or the second electrode is connected to the first node, N1). The driving transistor (DT) turns on in response to the data voltage stored in the capacitor (CST) and serves to generate a driving current.

The capacitor CST has one end connected to the first electrode (or third node N3) of the third transistor T3 and the other end connected to the gate electrode (or second node N2) of the driving transistor DT. The capacitor CST serves to store the data voltage transmitted through the 1A transistor T1a and the 1B transistor T1b.

The organic light emitting diode (OLED) has an anode connected to the second electrode (or fourth node, N4) of the fourth transistor (T4), and a cathode electrode connected to the second power line (EVSS). The organic light emitting diode (OLED) functions to emit light in response to the driving current transmitted through the fifth transistor (T5).

The subpixel according to the first embodiment of the present invention operates in the following order: an initialization period (Initial), a sampling period (Sampling), and a subsequent light emission period during a period when the light emission signal (Em) falls to logic low.

During the initialization period (Initial), the third node (N3) and the second node (N2) are initialized by the initialization voltage (Vini) applied through the reference line (VREF). During the sampling period (Sampling), charging corresponding to the applied data voltage (Vdata) occurs at the third node (N3). And at the second node (N2), sampling (Vdd+Vth) of the high potential voltage (Vdd) and the threshold voltage (Vth) of the driving transistor (DT) occurs. At this time, the driving transistor (DT) is in a diode connection state due to the turned-on 2A transistor (T2a) and 2B transistor (T2b). During the light emission period, the driving transistor (DT) generates a compensated driving current based on the initialization voltage (Vini) - data voltage (Vdata) + high potential voltage (Vdd) + threshold voltage (Vth). And organic light-emitting diodes (OLEDs) operate based on compensated driving current and emit light.

The 1A transistor T1a and the 1B transistor T1b are arranged in pairs at one end of the first data line DL1 and the capacitor CST. However, the 1A transistor (T1a) is turned on in response to the scan signal of the current line, while the 1B transistor (T1b) is turned on in response to the scan signal of the previous line.

The 1A transistor (T1a) and the 1B transistor (T1b) are connected to different scan lines, but the logic low section of the N-1th scan signal (Scan N-1) and the Nth scan signal (Scan N) is 1. As they overlap during the horizontal period (1H), they have a simultaneous turn-on period. However, since the 1B transistor (T1b) is connected to the N-1 scan signal (Scan N-1), the turn-on time is earlier than that of the 1A transistor (T1a).

The 2A transistor (T2a) and the 2B transistor (T2b) are arranged in a pair between the first node (N1) and the second node (N2) of the driving transistor (DT). The 2A transistor (T2a) and the 2B transistor (T2b) have a common gate structure sharing the N-1 scan line (SCAN N-1), so they are connected to the N-1 scan signal (Scan N-1). are turned on at the same time. The paired 2A transistor (T2a) and 2B transistor (T2b) can provide a function of suppressing the influence of leakage current (off current). Because of this, the reliability and stability of the driving transistor DT increases when driving.

The fifth transistor T5, which shares the N-1 scan line (SCAN N-1), is also turned on at the same time as the 2A transistor T2a and the 2B transistor T2b. An initialization voltage (Vini) is applied to the anode electrode of the organic light emitting diode (OLED) while the 2A transistor (T2a), the 2B transistor (T2b), and the 5th transistor (T5) are turned on.

The 1A transistor (T1a), 1B transistor (T1b), 2A transistor (T2a), 2B transistor (T2b), 3rd transistor (T3), 4th transistor (T4) included in the pixel circuit of the subpixel, The fifth transistor (T5) and driving transistor (DT) are made of P-type MOS transistors. The P-type MOS transistor turns on in response to a logic low scan signal, while it turns off in response to a logic high scan signal.

The subpixel is connected to the first scan line GL1 including the N-1th scan line (SCAN N-1), the Nth scan line (SCAN N), and the emission signal line (EM). The N-1th scan signal (Scan N-1) applied through the N-1th scan line (SCAN N-1) and the Nth scan signal (Scan N) applied through the Nth scan line (SCAN N) are It has overlapping sections. The light emission signal (Em) applied through the light emission signal line (EM) has a phase opposite to the Nth scan signal (Scan N). That is, when the Nth scan signal (Scan N) occurs at logic low, the light emitting signal (Em) occurs at logic high (or vice versa).

The Nth scan signal (Scan N) applied through the Nth scan line (SCAN N) corresponds to the scan signal of the current line for driving the subpixel located on the current horizontal line. On the other hand, the N-1th scan signal (Scan N-1) applied through the N-1th scan line (SCAN N-1) is the previous horizontal line for driving a subpixel located one line before the current horizontal line. Corresponds to the scan signal of

As can be seen from the above explanation, the subpixel has an Nth scan line (SCAN N) for driving itself and an N-1th scan line (SCAN N-1) for driving the subpixel of the previous horizontal line. It has a structure to use. Additionally, the subpixel has transistors T1a, T1b, T2a, and T2b that are connected to different scan lines but whose turn-on periods are designed to overlap.

Therefore, in the first embodiment of the present invention, since the subpixel has the above structure, internal compensation can be performed while reducing one scan line, and the density can be reduced when designing the circuit configuration and layout due to the reduction of the scan line. There is a possible effect.

<Second Embodiment>

FIG. 9 is a diagram illustrating a subpixel having a compensation circuit according to a second embodiment of the present invention, and FIG. 10 is a diagram illustrating scan signals applied to the subpixel shown in FIG. 9 and node voltages at both ends of a capacitor.

As shown in FIGS. 9 and 10, the subpixel according to the second embodiment of the present invention includes a 1A transistor (T1a), a 1B transistor (T1b), a 2nd transistor (T2), and a 3rd transistor (T3). , a fourth transistor (T4), a fifth transistor (T5), a driving transistor (DT), a capacitor (CST), and an organic light emitting diode (OLED).

The 1A transistor (T1a) has a gate electrode connected to the N scan line (SCAN N), a first electrode connected to the first data line (DL1), and a second electrode connected to the first electrode of the 1B transistor (T1b). connected. The 1A transistor T1a is turned on in response to the Nth scan signal (Scan N) applied through the Nth scan line (SCAN N). The turned-on 1A transistor (T1a) serves to transfer the data voltage applied through the first data line (DL1) to the 1B transistor (T1b).

The 1B transistor (T1b) has a gate electrode connected to the N-1 scan line (SCAN N-1), a first electrode connected to the second electrode of the 1A transistor (T1a), and one end (or The second electrode is connected to the third node (N3). The 1B transistor T1b is turned on in response to the N-1th scan signal (Scan N-1) applied through the N-1th scan line (SCAN N-1). The turned-on 1B transistor (T1b) serves to apply the data voltage transmitted through the 1A transistor (T1a) to one end of the capacitor (CST).

The second transistor (T2) has a gate electrode connected to the N-1 scan line (SCAN N-1), a first electrode connected to the other end (or second node N2) of the capacitor (CST), and a driving transistor (DT). ) The second electrode is connected to the second electrode (or the first node, N1). The second transistor T2 is turned on in response to the N-1th scan signal (Scan N-1) applied through the N-1th scan line (SCAN N-1). The turned-on second transistor (T2) serves to put the driving transistor (DT) in a diode connection state.

The third transistor (T3) has a gate electrode connected to the light emitting signal line (EM) and a first electrode connected to the second electrode of the 1B transistor (T1b) and one end (or third node, N3) of the capacitor (CST). The second electrode is connected to the Roego reference line (VREF). The third transistor T3 is turned on in response to the light emission signal Em applied through the light emission signal line EM. The turned-on third transistor (T3) serves to apply the initialization voltage (Vini) applied through the reference line (VREF) to the third node (N3).

The fourth transistor (T4) has a gate electrode connected to the light emitting signal line (EM), a first electrode connected to the second electrode (or first node N1) of the driving transistor (DT), and an organic light emitting diode (OLED). The second electrode is connected to the anode electrode (or N4, the fourth node). The fourth transistor T4 is turned on in response to the light emission signal Em applied through the light emission signal line EM. The turned-on fourth transistor (T4) serves to transfer the driving current generated from the driving transistor (DT) to the organic light emitting diode (OLED).

The fifth transistor (T5) has a gate electrode connected to the N-1 scan line (SCAN N-1), a first electrode connected to the reference line (VREF), and a second electrode connected to the anode electrode of the organic light emitting diode (OLED). This is connected. The fifth transistor T5 is turned on in response to the N-1th scan signal (Scan N-1) applied through the N-1th scan line (SCAN N-1). The turned-on fifth transistor (T5) serves to apply the initialization voltage (Vini) applied through the reference line (VREF) to the anode electrode of the organic light-emitting diode (OLED).

The driving transistor DT has a gate electrode connected to the other end (or second node N2) of the capacitor CST, a first electrode connected to the first power line EVDD, and a first electrode of the fourth transistor T4. (Or the second electrode is connected to the first node, N1). The driving transistor (DT) turns on in response to the data voltage stored in the capacitor (CST) and serves to generate a driving current.

The capacitor CST has one end connected to the first electrode (or third node N3) of the third transistor T3 and the other end connected to the gate electrode (or second node N2) of the driving transistor DT. The capacitor CST serves to store the data voltage transmitted through the 1A transistor T1a and the 1B transistor T1b.

The organic light emitting diode (OLED) has an anode connected to the second electrode (or fourth node, N4) of the fourth transistor (T4), and a cathode electrode connected to the second power line (EVSS). The organic light emitting diode (OLED) functions to emit light in response to the driving current transmitted through the fifth transistor (T5).

The subpixel according to the second embodiment of the present invention is different in that the transistor that plays the role of putting the driving transistor (DT) in the diode connection state is composed of one second transistor (T2), and the rest is the same as that of the first embodiment. Same as example.

Accordingly, the subpixel according to the second embodiment of the present invention also operates in the order of the initialization period (Initial), the sampling period (Sampling), and the subsequent light emission period during the period when the light emission signal (Em) falls to logic low.

Therefore, the second embodiment of the present invention can also perform internal compensation while reducing one scan line, and has the effect of lowering density when designing the circuit configuration and layout due to the reduction of the scan line.

FIG. 11 is an example diagram of a subpixel layout based on the second embodiment of the present invention, and FIG. 12 is a diagram for explaining secondary effects according to the second embodiment of the present invention.

As shown in FIG. 9, when designing the layout of a subpixel based on the second embodiment of the present invention, a specific scan line (SCAN N-1) of the previous line is used instead of a separate scan line. The transistors T1b, T2, and T5 can be operated.

As a result, the second embodiment of the present invention can reduce at least one scan line, and because of this, the area occupied by the capacitor (CST) can be expanded compared to the previous version by utilizing the extra space as shown in FIG. 11. If the area occupied by the capacitor (CST) is increased compared to before, the capacitance will increase, which can lower the flicker generation rate and also provide an advantage in low-speed operation. In contrast, the second embodiment of the present invention can increase process yield by lowering the density of the circuit even if the area occupied by the capacitor (CST) is not increased compared to the previous one.

Meanwhile, the layout of the subpixel proposed in FIG. 11 briefly shows the light emitting area (EMA) where the organic light emitting diode that emits light is located and the circuit area (DRA) where the pixel circuit is located.

According to the proposed subpixel layout, the N-1th scan line (SCAN N-1) and the Nth scan line (SCAN N) are arranged along the horizontal direction adjacent to the emission area (EMA). And the reference line (VREF), the first data line (DL1), and the first power line (EVDD) are arranged along the vertical direction intersecting the horizontal direction. Additionally, the emission signal line (EM) is arranged to be spaced apart from the N-1th scan line (SCAN N-1) and the Nth scan line (SCAN N), and a capacitor (CST) is placed between them. However, this is only an example and the second embodiment of the present invention is not limited thereto.

As can be seen from Figure 11, according to the second embodiment of the present invention, there are various expected effects, such as increasing the area occupied by the capacitor (CST) compared to the previous one or increasing the process yield by lowering the density of the circuit.

As shown in FIG. 12, according to the second embodiment of the present invention (FIG. 12(b)), the configuration of the shift register can also be simplified compared to the prior art (FIG. 12(a)). The prior art (FIG. 12 (a)) includes a first scan signal generating circuit (SCAN1) that generates a first scan signal to drive a subpixel with an internal compensation circuit, and a second scan signal that generates a second scan signal. The shift register is implemented in a form that includes a circuit (SCAN2) and a light emitting signal generation circuit (EM) that generates a light emitting signal.

However, as can be seen from the previous description, the second embodiment of the present invention (FIG. 12 (b)) includes a first scan signal generation circuit (SCAN1) that generates one scan signal as one scan line is deleted, and light emission. The configuration of the shift register can be simplified by including a light emitting signal generation circuit (EM) that generates a signal. As a result, the second embodiment of the present invention reduces the area occupied by the shift register, enabling a narrow bezel of the display panel, as well as providing an advantage when implementing (or driving) a mid-sized or higher model or a high-resolution model.

Above, in FIGS. 11 and 12, the description was made based on the second embodiment of the present invention, but this effect can be equally exhibited in the first embodiment of the present invention.

<Third Embodiment>

FIG. 13 is a diagram showing subpixels and switches having a compensation circuit according to a third embodiment of the present invention, and FIG. 14 is a diagram showing a selection signal applied to the switches shown in FIG. 13 and a scan signal applied to the subpixels. This is a diagram showing the voltages and data voltages.

According to the third embodiment of the present invention shown in FIGS. 13 and 14, the first subpixel (SP01) and the 11th subpixels (SP11) are implemented based on the circuit described in the first embodiment. . The first subpixel SP01 and the 11th subpixels SP11 correspond to subpixels adjacent to each other up and down or left and right on the display panel.

The first subpixel SP01 is connected to the 1A data line DL1a, and the 11th subpixels SP11 are connected to the 1B data line DL1b (or vice versa). The first switch (SW1) is located between the 1A data line (DL1a) and the first channel (CH1) of the data driver 130, and the first switch (SW1) is located between the 1B data line (DL1b) and the first channel (CH1) of the data driver 130. A second switch (SW2) is located between them. The first switch (SW1) and the second switch (SW2) may be disposed in a non-display area on the display panel that does not display images, but are not limited to this.

The first switch (SW1) has a gate electrode connected to the first selection signal line (MUX1), a first electrode connected to the first channel (CH1) of the data driver 130, and a second electrode connected to the 1A data line (DL1a). Electrodes are connected. The second switch (SW2) has a gate electrode connected to the second selection signal line (MUX2), a first electrode connected to the first channel (CH1) of the data driver 130, and a second switch to the 1B data line (DL1b). Electrodes are connected.

The first selection signal (Mux1) applied through the first selection signal line (MUX1) and the second selection signal (Mux2) applied through the second selection signal line (MUX2) have opposite phases. That is, when the first selection signal (Mux1) occurs at logic low, the second selection signal (Mux2) occurs at logic high (or vice versa). The first selection signal (Mux1) and the second selection signal (Mux2) are applied in a form in which logic high and logic low alternate at least every one horizontal period (1H). As a result, the first subpixel (SP01) and the 11th subpixels (SP11) time-divide the first and second data voltages (Vdata1, Vdata2) output from the first channel (CH1) of the data driver 130. It is approved in this way.

The subpixel described above through the first embodiment has a sampling period (Sampling) only for one horizontal period (1H) due to the nature of the driving method. However, if a structure for applying the data voltage in a time-division method is added (adding one more data line) like the sub-pixels according to the third embodiment, it is possible to have a sampling period (Sampling) for 2 horizontal periods (2H). In other words, the sampling (or sensing) time can be doubled.

<Example 4>

FIG. 15 is a diagram showing subpixels and switches having a compensation circuit according to a fourth embodiment of the present invention, and FIG. 16 is a diagram showing a selection signal applied to the switches shown in FIG. 15 and a scan signal applied to the subpixels. This is a diagram showing the voltages and data voltages.

According to the fourth embodiment of the present invention shown in FIGS. 15 and 16, the first subpixel (SP01) and the 11th subpixels (SP11) are implemented based on the circuit described in the second embodiment. . The first subpixel SP01 and the 11th subpixels SP11 correspond to subpixels adjacent to each other up and down or left and right on the display panel.

The first subpixel SP01 is connected to the 1A data line DL1a, and the 11th subpixels SP11 are connected to the 1B data line DL1b (or vice versa). The first switch (SW1) is located between the 1A data line (DL1a) and the first channel (CH1) of the data driver 130, and the first switch (SW1) is located between the 1B data line (DL1b) and the first channel (CH1) of the data driver 130. A second switch (SW2) is located between them.

The first switch (SW1) has a gate electrode connected to the first selection signal line (MUX1), a first electrode connected to the first channel (CH1) of the data driver 130, and a second electrode connected to the 1A data line (DL1a). Electrodes are connected. The second switch (SW2) has a gate electrode connected to the second selection signal line (MUX2), a first electrode connected to the first channel (CH1) of the data driver 130, and a second switch to the 1B data line (DL1b). Electrodes are connected.

The first selection signal (Mux1) applied through the first selection signal line (MUX1) and the second selection signal (Mux2) applied through the second selection signal line (MUX2) have opposite phases. That is, when the first selection signal (Mux1) occurs at logic low, the second selection signal (Mux2) occurs at logic high (or vice versa). The first selection signal (Mux1) and the second selection signal (Mux2) are applied in a form in which logic high and logic low alternate at least every one horizontal period (1H). As a result, the first subpixel (SP01) and the 11th subpixels (SP11) time-divide the first and second data voltages (Vdata1, Vdata2) output from the first channel (CH1) of the data driver 130. It is approved in this way.

The subpixel described above through the second embodiment has a sampling period (Sampling) only for one horizontal period (1H) due to the nature of the driving method. However, if a structure for applying the data voltage in a time-division method is added (adding one more data line) like the subpixels according to the fourth embodiment, it is possible to have a sampling period (Sampling) for 2 horizontal periods (2H). In other words, the sampling (or sensing) time can be doubled.

FIG. 17 is an example diagram of a subpixel layout based on the fourth embodiment of the present invention, and FIG. 18 is a diagram for explaining secondary effects according to the fourth embodiment of the present invention.

As shown in FIG. 15, when designing the layout of a subpixel based on the fourth embodiment of the present invention, a specific scan line (SCAN N-1) of the previous line is used instead of a separate scan line. The transistors T1b, T2, and T5 can be operated.

As a result, the fourth embodiment of the present invention can reduce at least one scan line, and because of this, the area occupied by the capacitor (CST) can be expanded compared to the previous version by utilizing the extra space as shown in FIG. 17. If the area occupied by the capacitor (CST) is increased compared to before, the capacitance will increase, which can lower the flicker generation rate and also provide an advantage in low-speed driving. In contrast, even if the area occupied by the capacitor (CST) is not increased compared to before, the process yield can be increased by lowering the density of the circuit.

Meanwhile, the layout of the subpixel proposed in FIG. 17 briefly shows the light emitting area (EMA) where the organic light emitting diode that emits light is located and the circuit area (DRA) where the pixel circuit is located.

According to the proposed subpixel layout, the N-1th scan line (SCAN N-1) and the Nth scan line (SCAN N) are arranged along the horizontal direction adjacent to the emission area (EMA). And the first power line (EVDD), reference line (VREF), 1A data line (DL1a), and 1B data line (DL1b) are arranged along the vertical direction crossing the horizontal direction. Also, the light emitting signal line (EM) is arranged to be spaced apart from the N-1th scan line (SCAN N-1) and the Nth scan line (SCAN N), and a capacitor (CST) is placed between them. However, this is only an example and the fourth embodiment of the present invention is not limited thereto.

As can be seen from Figure 17, according to the fourth embodiment of the present invention, there are various expected effects, such as increasing the area occupied by the capacitor (CST) compared to the previous one or increasing the process yield by lowering the density of the circuit.

As shown in FIG. 18, according to the fourth embodiment of the present invention (FIG. 18 (b)), the configuration of the shift register can also be simplified compared to the prior art (FIG. 18 (a)). The prior art (FIG. 18 (a)) includes a first scan signal generation circuit (SCAN1) that generates a first scan signal to drive a subpixel with an internal compensation circuit, and a second scan signal that generates a second scan signal. The shift register is implemented in a form that includes a circuit (SCAN2) and a light emitting signal generation circuit (EM) that generates a light emitting signal.

However, as can be seen from the previous description, the fourth embodiment of the present invention (FIG. 18 (b)) includes a first scan signal generation circuit (SCAN1) that generates one scan signal as one scan line is deleted, and light emission. The configuration of the shift register can be simplified by including a light emitting signal generation circuit (EM) that generates a signal. As a result, the fourth embodiment of the present invention reduces the area occupied by the shift register, enabling a narrow bezel of the display panel, as well as providing an advantage when implementing (or driving) a mid-sized or higher model or a high-resolution model.

17 and 18 have been described based on the fourth embodiment of the present invention, but the same effect can be achieved in the third embodiment of the present invention.

19 to 21 are diagrams for explaining the advantages of the display panel implementation method of the third and fourth embodiments of the present invention.

As shown in FIG. 19, the display panel 150 has data lines arranged in the horizontal direction (x) and scan lines arranged in the vertical direction (y), so that the horizontal direction (x) is longer than the vertical direction (y). It can be implemented in the form At this time, the data driver 130 is disposed in the horizontal direction (x), and the scan driver 140 (shift register in the case of the gate-in-panel method) is disposed in the vertical direction (y). In this case, the length of the data lines becomes longer than the scan lines.

When the display panel 150 is implemented in this way, the sensing time may be reduced (or insufficient) or the sampling time may be reduced due to an increase in the length and resolution of the data lines.

As shown in FIG. 20, in the case of a display panel implemented based on subpixels with a compensation circuit, when the sensing time or sampling time is reduced, the change in threshold voltage (Vth) of the driving transistor cannot be properly reflected. Expressing compensation or luminance may become difficult.

As shown in Figure 21 (a), the display panels of the first and second embodiments of the present invention may have a sampling time of 1 horizontal time (1H) due to the characteristics of the applied scan signal (Scan), and as shown in Figure 21 (b) Likewise, the display panels of the third and fourth embodiments of the present invention may have a sampling time of 2 horizontal hours (2H) due to the characteristics of the applied scan signal (Scan).

As can be seen through a simple comparison of Figures 21 (a) and 21 (b), the third and fourth embodiments of the present invention can write data voltages in a time division manner and also reduce the number of scan lines. and can also provide sufficient sampling time.

Therefore, the third and fourth embodiments of the present invention can solve the problem of reduction in sensing time or sampling time when applied to a display panel where the data lines are longer than the scan lines as shown in FIG. 19, and also improve compensation accuracy. The display quality can be improved by improving the display quality.

The present invention has the effect of reducing the number of scan lines and providing sufficient sampling time when implementing a display panel based on an internal compensation circuit. In addition, the present invention has the effect of lowering the flicker occurrence rate and increasing the area occupied by the capacitor compared to the previous one to be advantageous for low-speed driving, or lowering the density of the circuit to increase process yield. In addition, the present invention reduces the area occupied by the shift register, which not only enables a narrow bezel of the display panel, but also provides advantages when implementing mid-sized or higher models or high-resolution models.

Although embodiments of the present invention have been described with reference to the accompanying drawings, the technical configuration of the present invention described above can be modified by those skilled in the art in the technical field to which the present invention belongs in other specific forms without changing the technical idea or essential features of the present invention. You will understand that it can be done. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the claims described later rather than the detailed description above. In addition, the meaning and scope of the patent claims and all changes or modified forms derived from the equivalent concept should be construed as being included in the scope of the present invention.

130: data driver 140: scan driver
180: power supply unit 150: display panel
T1a: 1st transistor T1b: 1st transistor
T2a: 2A transistor T2b: 2B transistor
DT: Driving transistor CST: Capacitor
OLED: Organic light emitting diode SCAN N-1: N-1 scan line
SCAN N: Nth scan line EM: Light emitting signal line

Claims (10)

A display panel that displays images;
a data driver that supplies a data voltage through a data line of the display panel; and
A scan driver that supplies a scan signal through a scan line of the display panel,
The display panel is
A 1A transistor turned on in response to the Nth scan signal of the Nth scan line,
It includes a subpixel including a 1B transistor that is turned on in response to the N-1th scan signal of the N-1th scan line,
The subpixel is
A light emitting display device having a subpixel that stores the data voltage in response to the Nth scan signal applied through the Nth scan line and the N-1th scan signal applied through the N-1th scan line. A display panel that displays images;
a data driver that supplies a data voltage through a data line of the display panel; and
A scan driver that supplies a scan signal through a scan line of the display panel,
The display panel is
A 1A transistor turned on in response to the Nth scan signal of the Nth scan line,
It includes a subpixel including a 1B transistor that is turned on in response to the N-1th scan signal of the N-1th scan line,
The subpixel is
A light-emitting display having a subpixel that stores the data voltage during a period where the N-th scan signal applied through the N-th scan line and the N-1th scan signal applied through the N-1 scan line overlap. Device. delete According to claim 1 or 2,
The 1A transistor and the 1B transistor are
A light emitting display device that has a simultaneous turn-on period. According to claim 1 or 2,
The 1B transistor is
A light emitting display device whose turn-on time is earlier than that of the 1A transistor. According to claim 1 or 2,
The first A transistor has a gate electrode connected to the Nth scan line and a first electrode connected to the first data line,
A light emitting display device in which the gate electrode of the 1B transistor is connected to the N-1 scan line and the first electrode is connected to the second electrode of the 1A transistor. According to claim 1 or 2,
The display panel is
Further comprising at least two switches connected to channels of the data driver,
The at least two switches
a first switch with a gate electrode connected to a first selection signal line, a first electrode connected to a first channel of the data driver, and a second electrode connected to a 1A data line;
A light emitting display device comprising a second switch with a gate electrode connected to a second selection signal line, a first electrode connected to a first channel of the data driver, and a second electrode connected to a 1B data line. In clause 7,
The display panel is
A first subpixel connected to the 1A data line,
Includes an 11th subpixel connected to the 1B data line,
The first subpixel and the 11th subpixel are adjacent to each other vertically or horizontally on the display panel. According to claim 1 or 2,
The subpixel is
A 1A transistor with a gate electrode connected to the N scan line and a first electrode connected to the first data line;
a 1B transistor whose gate electrode is connected to the N-1 scan line and whose first electrode is connected to the second electrode of the 1A transistor;
A capacitor with one end connected to the second electrode of the 1B transistor,
a driving transistor with a gate electrode connected to the other end of the capacitor and a first electrode connected to a first power line;
a second transistor with a gate electrode connected to the N-1th scan line, a first electrode connected to the other end of the capacitor, and a second electrode connected to the second electrode of the driving transistor;
a third transistor having a gate electrode connected to a light emitting signal line, a first electrode connected to one end of the capacitor, and a second electrode connected to a reference line;
a fourth transistor whose gate electrode is connected to the light emitting signal line and whose first electrode is connected to the second electrode of the driving transistor;
a fifth transistor having a gate electrode connected to the N-1 scan line, a first electrode connected to the reference line, and a second electrode connected to the second electrode of the fourth transistor;
A light emitting display device including a light emitting diode with an anode electrode connected to a second electrode of the fourth transistor and a cathode electrode connected to a second power line. According to claim 1 or 2,
The subpixel is
A 1A transistor with a gate electrode connected to the N scan line and a first electrode connected to the first data line;
a 1B transistor whose gate electrode is connected to the N-1 scan line and whose first electrode is connected to the second electrode of the 1A transistor;
A capacitor with one end connected to the second electrode of the 1B transistor,
a driving transistor with a gate electrode connected to the other end of the capacitor and a first electrode connected to a first power line;
A 2A transistor with a gate electrode connected to the N-1 scan line and a first electrode connected to the other end of the capacitor;
a 2B transistor with a gate electrode connected to the N-1 scan line, a first electrode connected to the second electrode of the 2A transistor, and a second electrode connected to the second electrode of the driving transistor;
a third transistor having a gate electrode connected to a light emitting signal line, a first electrode connected to one end of the capacitor, and a second electrode connected to a reference line;
a fourth transistor whose gate electrode is connected to the light emitting signal line and whose first electrode is connected to the second electrode of the driving transistor;
a fifth transistor having a gate electrode connected to the N-1 scan line, a first electrode connected to the reference line, and a second electrode connected to the second electrode of the fourth transistor;
A light emitting display device including a light emitting diode with an anode electrode connected to a second electrode of the fourth transistor and a cathode electrode connected to a second power line.

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