KR102564336B1 - DISPLAY PANEL and LIQUID CRYSTAL DISPLAY DEVICE - Google Patents

Abstract

An embodiment of the present invention is a display panel having a structure in which heat generation of a data line driver can be solved while supplying a horizontal 1-dot-vertical 1-dot inversion data voltage to a plurality of sub-pixels, and among data lines. By including a data line driver including a dummy data output unit connected to the first data line, without changing the pixel arrangement structure of the display panel, a vertical line between data lines adjacent to each other and to which data voltages of the same polarity are supplied. Provided is a liquid crystal display device capable of reducing the visibility of a vertical stripe defect corresponding to

Description

Display panel and liquid crystal display {DISPLAY PANEL and LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a display panel and a liquid crystal display device.

BACKGROUND OF THE INVENTION As we enter the information age in earnest, a display field that visually displays electrical information signals is rapidly developing. Accordingly, research is being conducted to develop performance such as thinning, light weight, and low power consumption for various flat display devices.

Representative examples of such a flat panel display are a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an electroluminescent display device. (Electro Luminescence Display device: ELD), Electro-Wetting Display device (EWD), and Organic Light Emitting Display device (OLED).

These flat panel display devices include a flat display panel for realizing an image. The display panel includes a pair of substrates bonded to each other with a light emitting material or a polarizing material interposed therebetween.

Exemplarily, a display panel of a liquid crystal display device includes a liquid crystal layer injected between a pair of substrates. Then, an electric field corresponding to the image signal is applied to the liquid crystal layer of each pixel area to adjust light transmittance of the liquid crystal layer, thereby displaying an image. At this time, an electric field is generated between the pixel electrode and the common electrode. That is, an electric field is generated by supplying the data voltage to the pixel electrode and supplying the common voltage to the common electrode.

Meanwhile, in order to reduce DC afterimages and prevent deterioration of liquid crystals, the liquid crystal display supplies a data voltage whose polarity is reversed in a vertical or horizontal direction every 1 dot or 2 dots to a plurality of sub-pixels. At this time, the polarity of the data voltage supplied to each sub-pixel is inverted every cycle for displaying each frame. This is called an inversion method. Here, 1 dot means 1 sub-pixel.

Examples of such an inversion method include a horizontal 1-dot-vertical 1-dot inversion method and a horizontal 1-dot-vertical 2-dot inversion method.

In the horizontal 1-dot-vertical 1-dot inversion method, the polarity of data voltages supplied to horizontally and vertically adjacent sub-pixels is inverted in units of 1 dot.

The horizontal 1-dot - vertical 2-dot inversion method inverts the polarity of the data voltage supplied to horizontally adjacent sub-pixels in units of 1 dot, and inverts the polarity of the data voltage supplied to the vertically adjacent sub-pixels in units of 2 dots. Invert.

When the horizontal 1-dot-vertical 1-dot inversion method or the horizontal 1-dot-vertical 2-dot inversion method is applied, it is possible to prevent data voltages having the same polarity from being supplied for each location or color. As a result, the uniformity of the display characteristics can be prevented from deteriorating, and thus the deterioration of image quality can be prevented.

However, the data line driver supplies a data voltage whose polarity is reversed every 1 dot or 2 dots according to the horizontal 1-dot-vertical 1-dot inversion method or the horizontal 1-dot-vertical 2-dot inversion method. A toggle that reverses the polarity every 2 dots should be performed.

Therefore, the number of times the data line driver toggles during a period for displaying one frame is the total number of vertical lines corresponding to a plurality of sub-pixels or 1/2 times the total number of vertical lines. As a result, there is a problem in that a heating problem occurs in the data line driver.

SUMMARY OF THE INVENTION The present invention provides a display panel and a liquid crystal display device capable of solving a heating problem of a data line driver while supplying data voltages in a horizontal 1-dot-vertical 1-dot inversion method to a plurality of sub-pixels.

In addition, the present invention provides a display panel and a liquid crystal display device capable of reducing the visibility of a vertical line defect due to a vertical line between data lines adjacent to each other and supplied with data voltages of the same polarity.

In addition, the present invention provides a liquid crystal display device capable of reducing the visibility of vertical stripes without changing the pixel arrangement structure of the display panel.

The present invention relates to a liquid crystal display device including a display panel and a data line driver. In particular, the present invention provides a display panel having a pixel arrangement structure capable of solving a heating problem of a data line driver while supplying data voltages in a horizontal 1-dot-vertical 1-dot inversion method to a plurality of sub-pixels, and a display panel An object of the present invention is to provide a liquid crystal display device capable of reducing the visibility of a vertical line defect corresponding to a vertical line between data lines adjacent to each other and to which data voltages of the same polarity are supplied without changing a pixel arrangement structure.

A liquid crystal display device according to an example of the present invention includes gate lines in a first direction, data lines in a second direction crossing the first direction, and defined by the gate lines and the data lines. It includes a display panel including a plurality of sub-pixels corresponding to a plurality of pixel areas, and a data line driver supplying respective data voltages to the data lines. Here, the data line driver includes a dummy data output unit connected to the first data line, a first data output unit connected to the 8m+2 and 8m+3 data lines, and the 8m+4 and 8m+5 data lines. A second data output unit connected, a third data output unit connected to the 8m+6th and 8m+7th data lines, and a fourth connected to the 8m+8th and 8(m+1)+1th data lines. Includes data output unit.

The dummy data output unit supplies a data voltage having the same polarity as a data voltage supplied to a second data line adjacent to the first data line to the first data line.

Further, the data line driver may display the first data line, the 8m+2th data line, the 8m+4th data line, the 8m+7th data line, and the 8m+7th data line during a period for displaying any one frame. The (m+1)+1th data line is supplied with a first polarity data voltage, and the 8m+3rd data line, the 8m+5th data line, the 8m+6th data line and the 8m+8th data line are supplied. A data voltage of a second polarity different from the first polarity is supplied to the data lines, and each data supplied to the data lines during a period of displaying the next frame after the period of displaying one frame ends. Invert the polarity of the voltage.

The plurality of subpixels are composed of first, second, third, and fourth subpixels corresponding to four different colors, and between data lines adjacent to each other and supplied with data voltages of the same polarity, the first, second, third, and fourth subpixels are connected to each other. At least two subpixels having a low luminance ratio among the first, second, third, and fourth subpixels are alternately and repeatedly arranged.

Among the plurality of subpixels, subpixels connected to the 2n+1th gate line are connected to a data line on one side of the subpixels connected to the 2n+1th gate line, and the first, second, third and fourth subpixels are are repeatedly arranged side by side along the first direction in the order of, and among the plurality of subpixels, the subpixels connected to the 2n+2th gate line are connected to the data line on the other side of the subpixels connected to the 2n+2th gate line, , 3rd, 4th, 1st and 2nd sub-pixels are repeatedly arranged side by side along the first direction in this order.

Here, first and third subpixels having a low luminance ratio are alternately and repeatedly arranged in the second direction between adjacent data lines to which data voltages of the same polarity are supplied. Further, data voltages of polarities opposite to each other are supplied to data lines disposed on both sides of a vertical line in which the second and fourth sub-pixels having a high luminance ratio are alternately and repeatedly arranged in the second direction.

Alternatively, the display panel according to another example of the present invention includes gate lines in a first direction, data lines in a second direction crossing the first direction, and a plurality of lines defined by the gate lines and the data lines. It includes a plurality of sub-pixels corresponding to the pixel area. Here, the plurality of subpixels are composed of first, second, third, and fourth subpixels corresponding to four different colors. And, during the period for displaying any one frame, the data voltage of the first polarity is supplied to the 8m+1st, 8m+3rd, 8m+6th, and 8m+8th data lines among the data lines. and a data voltage of a second polarity opposite to the first polarity is supplied to the 8m+2nd, 8m+4th, 8m+5th and 8m+7th data lines, and displays any one of the frames. After the period of displaying the next frame, the polarity of each data voltage supplied to the data lines is reversed, and between data lines adjacent to each other and supplied with data voltages of the same polarity, the first frame is displayed. Among the first, second, third, and fourth subpixels, at least two subpixels having a low luminance ratio are alternately and repeatedly arranged in the second direction.

In this way, a vertical line disposed between data lines that are adjacent to each other and supplied with data voltages of the same polarity and may cause a vertical line defect is composed of sub-pixels having a relatively low luminance ratio, thereby lowering the visibility of the vertical stripe defect. can

According to each embodiment of the present invention, subpixels connected to the 2n+1 th gate line among the plurality of subpixels are connected to the data line disposed on one side of each subpixel, and the subpixels connected to the 2n+2 th gate line are It is connected to the data line arranged on the other side of each. The data line driver supplies data voltages of different polarities to adjacent data lines, and inverts the polarity of the data voltages supplied to each data line at each frame display cycle.

In this way, even if the data line driver supplies the data voltage of the column inversion method, the data voltage of one horizontal dot-one vertical dot inversion method can be supplied to the plurality of sub-pixels. Accordingly, the problem of heat generation in the data line driver can be solved while supplying the data voltage in the horizontal 1-dot-vertical 1-dot inversion scheme to the plurality of sub-pixels.

Further, according to an embodiment of the present invention, at least two sub-pixels having a low luminance ratio are alternately and repeatedly arranged on a vertical line between adjacent data lines to which data voltages of the same polarity are supplied. Further, data voltages of different polarities are supplied to data lines disposed on both sides of a vertical line in which subpixels having a high luminance ratio are alternately and repeatedly arranged.

Due to the pixel arrangement structure of the display panel, the visibility of vertical line defects due to vertical lines between adjacent data lines to which data voltages of the same polarity are supplied may be reduced.

In addition, according to another embodiment of the present invention, the data line driver includes a dummy data output unit connected to the first data line, a first data output unit connected to the 8m+2 and 8m+3 data lines, and an 8m+4 data line. 2nd data output unit connected to the 8th and 8m+5th data lines, 3rd data output unit connected to the 8m+6th and 8m+7th data lines, and 8m+8th and 8(m+1)+ and a fourth data output unit connected to the first data line.

The dummy data output unit supplies a data voltage having the same polarity as that supplied to a second data line adjacent to the first data line to the first data line.

In this way, data voltages of the same polarity are supplied to data lines disposed on both sides of a vertical line in which at least two sub-pixels having a low luminance ratio are alternately and repeatedly arranged. Instead, data voltages of different polarities may be supplied to data lines disposed on both sides of a vertical line in which two subpixels having a high luminance ratio are alternately and repeatedly arranged.

Therefore, since the visibility of the vertical stripe defect can be reduced without changing the pixel arrangement structure of the display panel, the high cost of preparing the display panel with the changed pixel arrangement structure can be reduced.

1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention.
2 is an example of a cross section of the display panel of FIG. 1 according to the first embodiment of the present invention.
3 is a diagram showing a sub-pixel arrangement of a display panel according to a first embodiment of the present invention.
4 is a diagram showing a sub-pixel arrangement of a display panel according to a second embodiment of the present invention.
5 is an example of a cross section of the display panel of FIG. 1 according to the second embodiment of the present invention.
6 and 7 are diagrams illustrating a display panel and a data line driver according to a first embodiment of the present invention.
8 and 9 are diagrams illustrating a sub-pixel arrangement and a data line driver of a display panel according to a third embodiment of the present invention.

Hereinafter, a liquid crystal display according to each embodiment of the present invention and a display panel provided therewith will be described in detail with reference to the accompanying drawings.

First, referring to FIGS. 1 to 3 , a liquid crystal display device according to a first embodiment of the present invention will be described.

1 is a block diagram showing a liquid crystal display device according to a first embodiment of the present invention. FIG. 2 is an example of a cross section of the display panel of FIG. 1 according to the first embodiment of the present invention, and FIG. 3 is a diagram showing a sub-pixel arrangement of the display panel according to the first embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display device 100 according to the first embodiment of the present invention includes a display panel 110, a data line driver 120, a gate line driver 130, and a timing controller 140. include Here, the data line driver 120 may be implemented as a circuit board on which a data driver chip is mounted. In addition, the gate line driver 130 may be implemented as a separate circuit board or may be implemented as a circuit embedded in the display panel 110 to simplify the device.

In addition, although not shown in FIG. 1, since the display panel 110 of the liquid crystal display device 100 does not include a self-light emitting element, the liquid crystal display device 100 is disposed below the display panel 110 and the display panel ( 110) may further include a backlight unit (not shown) for irradiating a surface light source.

The display panel 110 includes gate lines (GL[1], GL[2], ..., GL[2n+1], GL[2n+2], ...) in a first direction (horizontal direction in FIG. 1) ( n is an integer greater than or equal to 0) (hereinafter collectively referred to as "GL"), and the data lines DL[1], DL[2], DL[ 3], …, DL[8m+1], DL[8m+2], DL[8m+3], DL[8m+4], DL[8m+5], DL[8m+6], DL[8m +7], DL[8m+8], DL[8(m+1)+1], ...) (m is an integer greater than or equal to 0) (hereinafter collectively referred to as "DL").

Also, the display panel 110 further includes a plurality of subpixels P corresponding to a plurality of pixel areas defined by the gate lines GL and data lines DL that cross each other.

Each sub-pixel (P) includes a thin film transistor (TFT) connected between the gate line (GL) and the data line (DL), a liquid crystal cell capacitor (Clc) connected between the thin film transistor (TFT) and the common power supply (Vcom), and A storage capacitor Cst connected in parallel with the liquid crystal cell capacitor Clc is included.

The gate electrode of the thin film transistor TFT is connected to the gate line GL, one of the source electrode and the drain electrode is connected to the data line DL, and the other one is a pixel constituting the liquid crystal cell capacitor Clc. It is connected to electrode PE. When the thin film transistor TFT is turned on based on the gate signal of the gate line GL, the data voltage of the data line DL is supplied to the pixel electrode PE.

The liquid crystal cell capacitor Clc corresponds to a pixel region of each sub-pixel P and refers to a capacitor component of liquid crystals affected by an electric field between the pixel electrode PE and the common electrode CE.

Specifically, when the data voltage is supplied to the pixel electrode PE through the thin film transistor TFT and the common voltage of the common power source Vcom is applied to the common electrode CE, the pixel electrode PE and the common electrode CE ), and the tilt direction of the liquid crystals corresponding to the pixel area of each sub-pixel P is changed by the electric field. Accordingly, since the light transmittance of each sub-pixel P is adjusted, the luminance of each sub-pixel P is controlled.

The data line driver 120 supplies each data voltage to the data lines DL.

Specifically, the data line driver 120 supplies data voltages of different polarities to mutually adjacent data lines DL, and the polarity of the data voltages supplied to each data line DL every cycle for displaying each frame. invert

Also, the first, second, third, and fourth sub-pixels P1, P2, P3, and P4 corresponding to different colors are repeatedly arranged parallel to each other in a first direction (horizontal direction). Accordingly, in order to prevent data voltages of the same polarity from being supplied to subpixels corresponding to the same color, the data line driver 120 generates data voltages whose polarities are reversed in units of four data lines adjacent to each other in the first direction. supply

For example, the data line driver 120 may use the 8m+1, 8m+2, 8m+3, and 8m+4 data lines (DL[8m+1) during a period for displaying any one frame. ], DL[8m+2], DL[8m+3], DL[8m+4]) to supply positive polarity, negative polarity, positive polarity and negative polarity (+, -, +, -) data voltage , 8m+5th, 8m+6th, 8m+7th and 8m+8th data lines (DL[8m+5], DL[8m+6], DL[8m+7], DL[8m+8 ]) can be supplied with data voltages of negative polarity, positive polarity, negative polarity and positive polarity (-, +, -, +). And, during a period for displaying the next frame, the data line driver 120 inverts the polarity of the data voltage supplied to each data line DL, so that the 8m+1th to 8m+8th data lines DL[ 8m+1], DL[8m+2], DL[8m+3], DL[8m+4], DL[8m+5], DL[8m+6], DL[8m+7], DL[8m +8]), negative polarity, positive polarity, negative polarity, positive polarity, positive polarity, negative polarity, positive polarity and negative polarity (-, +, -, +, + , -, +, -) data voltage is supplied.

The gate line driver 130 sequentially supplies gate voltages to the gate lines GL during one vertical period in which one frame is displayed.

The timing controller 140 transmits data based on timing signals such as a horizontal sync signal (Hsync), a vertical sync signal (Vsync), a data enable signal (DE), and a dot clock (DCLK) supplied from a system (not shown). Each operation of the line driver 120 and the gate line driver 130 is controlled.

The timing controller 140 performs a latch operation of the digital image data (RGB) based on a source start pulse (SSP), a rising edge or a falling edge indicating a sampling start point of the digital image data (RGB). The data line driver through a source sampling clock (SSC) indicating the output of the data line driver 120, a source output enable signal (SOE) indicating the output of the data line driver 120, and a polarity control signal (POE) indicating the polarity of the data voltage. The operation of (120) can be controlled.

The timing controller 140 rearranges the digital image data RGB supplied from the system according to the resolution of the display panel 110 and supplies it to the data line driver 120 .

In addition, the timing controller 140 is a timing control signal for sequentially shifting the gate start pulse (GSP) indicating the start horizontal line where the scan starts during one vertical period and input to the shift register to sequentially shift the gate start pulse (GSP). The gate line driver ( 130) can be controlled.

As shown in FIG. 2 , the display panel 110 includes first and second substrates 111 and 112 bonded to each other and a liquid crystal layer 113 interposed between the first and second substrates 111 and 112 . ).

Further, the display panel 110 further includes a thin film transistor array disposed on the first substrate 111 and a color filter 116 disposed on any one of the first and second substrates 111 and 112. include In FIG. 2 , the color filter 116 is illustrated as being disposed on the second substrate 112, but this is merely an example and may be included in the thin film transistor array (TFT array) on the first substrate 111. there is.

The thin film transistor array (TFT array) defines a plurality of pixel areas (PA1, PA2, PA3, PA4) corresponding to a plurality of sub-pixels (P), and drives each of the plurality of sub-pixels (P) independently.

The thin film transistor array (TFT array) includes gate lines (GL in FIG. 1) and data lines (DL in FIG. 1) that cross each other to define a plurality of pixel areas (PA1, PA2, PA3, PA4), and a plurality of pixel areas. It includes a plurality of thin film transistors (TFTs) corresponding to (PA1, PA2, PA3, PA4).

That is, the gate line GL, the data line DL, and the plurality of thin film transistors TFT of FIG. 1 are disposed on the first substrate 111 .

The gate line GL and the data line DL are insulated from each other by a gate insulating layer (not shown) interposed therebetween.

In addition, the thin film transistor array (TFT array) is disposed on the first substrate 111, and is disposed on the interlayer insulating film 114 covering the plurality of thin film transistors (TFT) and the interlayer insulating film 114, and each pixel area ( A planarization film 115 disposed on the pixel electrode 1 and the common electrode 2 corresponding to PA1, PA2, PA3, and PA4, and the interlayer insulating film 114 and covering the pixel electrode PE and the common electrode CE. ) may be further included.

The pixel electrode PE is connected to the thin film transistor TFT through a contact hole passing through the interlayer insulating layer 114 .

The common electrode CE is disposed alternately with the pixel electrode PE on the interlayer insulating layer 114 and is spaced apart from the pixel electrode PE.

However, the arrangement of the pixel electrode PE and the common electrode CE is just an example, and the liquid crystals of the liquid crystal layer 113 are tilted to adjust the light transmittance of each pixel area PA1, PA2, PA3, and PA4. It goes without saying that the arrangement can be changed to any arrangement capable of forming an electric field.

As illustrated in FIG. 2 , the display panel 110 may further include a black matrix (BM), a color filter (CF), and an overcoat layer 117 disposed on the second substrate 112 .

The black matrix BM is disposed outside each pixel area PA1 , PA2 , PA3 , and PA4 and blocks light leakage from the outside of each pixel area PA1 , PA2 , PA3 , and PA4 .

The color filter CF is disposed in each of the pixel areas PA1 , PA2 , PA3 , and PA4 .

According to the first embodiment, the color filter CF includes the red filter 116R disposed in the first pixel area PA1 corresponding to the first pixel area P1 and the second subpixel P2 corresponding to the red filter 116R. A green filter 116G disposed in the second pixel area PA2 and a blue filter 116B disposed in the third pixel area PA3 corresponding to the third sub-pixel P3 may be included. In addition, the fourth pixel area PA4 corresponding to the fourth sub-pixel P4 emitting white may be an empty space without a separate pigment or an area filled with an overcoat layer 117 covering the color filter CF. can

The overcoat layer 117 is disposed on the second substrate 112 and covers the black matrix BM and the color filter CF.

According to the first embodiment, the plurality of subpixels P are first, second, third, and fourth subpixels P1 corresponding to different colors so that the display panel 110 can display a color image. , P2, P3, P4). Exemplarily, the first, second, third, and fourth subpixels P1, P2, P3, and P4 may correspond to red (R), green (G), blue (B), and white (W). there is.

As shown in FIG. 3 , in the first direction (horizontal direction) corresponding to the gate line GL, the first, second, third, and fourth subpixels P1, P2, P3, and P4 are parallel to each other. arranged repeatedly.

In addition, in order to prevent clustering of the same color in the vertical or diagonal direction, the first, second, third, and fourth sub-pixels P1, P2, P3, and P4 are shifted by 2 dots in units of one horizontal line. do.

Exemplarily, the subpixels P connected to odd-numbered gate lines GL[1], ... GL[2n+1], ... are first, second, third, and fourth subpixels P1, P2, P3, P4) may be repeatedly arranged side by side along the first direction (horizontal direction) in the order. Further, the subpixels P connected to the even gate lines GL[2], ...GL[2n+2], ... are the third, fourth, first, and second subpixels P3, P4, P1, P2) may be repeatedly arranged side by side along the first direction (horizontal direction) in the order.

Accordingly, a vertical line in which the first and third subpixels P1 and P3 are alternately and repeatedly arranged in the second direction (vertical direction), and the second and fourth subpixels P2 and P4 are arranged in the second direction (vertical direction). Vertical lines alternately and repeatedly arranged in the vertical direction) are repeatedly arranged adjacent to each other.

The subpixels P arranged side by side on each horizontal line are connected to the gate line GL corresponding to each horizontal line.

Also, the subpixels P arranged side by side on each vertical line are alternately connected to two data lines DL disposed on both sides of the subpixels in units of 1 dot. Accordingly, the subpixels P arranged in a zigzag pattern are connected to the data line DL therebetween.

For example, the sub-pixels P connected to odd-numbered gate lines GL[1], ... GL[2n+1], ... are data lines DL disposed on one side (left side of FIG. 3). can be connected to In addition, the subpixels P connected to the even gate lines GL[2], ... GL[2n], ... can be connected to the data lines DL disposed on the other side (right side of FIG. 3). there is.

In other words, in the vertical lines between the first and second data lines DL[1] and DL[2], sub-pixels connected to odd-numbered gate lines GL[1], ... GL[2n+1], ... The sub-pixels P are connected to the first data line DL[1] disposed on the left side of them and connected to the even-th gate lines GL[2], ... GL[2n], ... may be connected to the second data line DL[2] disposed to the right of these.

As mentioned above, the data line driver 120 supplies data voltages of different polarities to two adjacent data lines DL. Accordingly, data voltages of a horizontal 1-dot inversion method are supplied to the plurality of sub-pixels P.

Also, the first and third sub-pixels P1 and P3 or the second and fourth sub-pixels P2 and P4 parallel to the second direction are connected to the data line DL on one side different from each other in units of one dot. Accordingly, data voltages of different polarities are supplied to adjacent subpixels in the second direction. That is, data voltages of a vertical 1-dot inversion method are supplied to the plurality of sub-pixels P.

As described above, by changing the connection between the plurality of subpixels P and the data lines DL, the data line driver 120 inverts the polarity of the data voltage in units of one data line DL. Even when driven in this manner, data voltages of a horizontal 1-dot-vertical 1-dot inversion method may be supplied to the plurality of sub-pixels P.

Therefore, in the display panel 110 according to the first embodiment of the present invention, the data voltage of the horizontal 1-dot-vertical 1-dot inversion scheme is supplied to the plurality of sub-pixels P, while the data line driver 120 generates heat. problem can be solved.

However, as mentioned above, the plurality of sub-pixels P include first, second, third, and fourth pixels corresponding to red (R), green (G), blue (B), and white (W). It is composed of sub-pixels P1, P2, P3, and P4.

At this time, in order to prevent the data voltage of the same polarity from being supplied to the subpixels P emitting the same color in each horizontal line, the first, second, third, and fourth subpixels P1, P2, The polarity of the data voltage is inverted for each of the four data lines DL corresponding to P3 and P4).

Accordingly, at a position where the polarity of the data voltage is reversed, data lines adjacent to each other and supplied with data voltages of the same polarity are generated.

As such, data voltages of the same polarity are supplied to sub-pixels of vertical lines disposed between adjacent data lines to which data voltages of the same polarity are supplied.

That is, as shown in FIG. 3, the same polarity (in FIG. 3, negative The data voltage of polarity (-) is supplied. Therefore, data of the same polarity is provided in the sub-pixels arranged on the vertical line A between the 8m+4th data line (DL[8m+4]) and the 8m+5th data line (DL[8m+5]). voltage is supplied.

In addition, the same polarity is applied to the mutually adjacent 8m+8th data line (DL[8m+8]) and 8(m+1)+1st data line (DL[8(m+1)+1]) (FIG. 3 In , a data voltage of positive polarity (+) is supplied. Therefore, it is arranged on the vertical line (B) between the 8m+8th data line (DL[8m+8]) and the 8(m+1)+1st data line (DL[8(m+1)+1]). Data voltages of the same polarity are supplied to the sub-pixels.

However, vertical lines A and B composed of sub-pixels to which data voltages of the same polarity are supplied have different display characteristics from other vertical lines around which data voltages whose polarities are inverted in units of 1 dot are supplied.

Accordingly, when a field of view or an image moves in a horizontal direction, vertical lines A and B made up of only sub-pixels to which data voltages of the same polarity are supplied may be viewed as vertical lines due to display characteristics different from those of the surroundings. Such a vertical line defect is also referred to as a dori dori defect.

In particular, when the frame frequency exceeds 60 Hz, as the charging time decreases, it is difficult for each subpixel P to be completely charged with the data voltage. As a result, a difference in display characteristics between the vertical lines A and B supplied with the data voltages of the same polarity and other vertical lines around them increases. Accordingly, as the vertical line defect intensifies, the image quality may be greatly deteriorated.

Accordingly, the second embodiment of the present invention provides a display panel capable of reducing the visibility of vertical line defects caused by vertical lines A and B composed of sub-pixels to which data voltages of the same polarity are supplied.

4 is a diagram showing a sub-pixel arrangement of a display panel according to a second embodiment of the present invention, and FIG. 5 is an example of a cross-section of the display panel of FIG. 1 according to the second embodiment of the present invention.

As shown in FIG. 4, in the display panel 110' according to the second embodiment of the present invention, the luminance ratios of vertical lines C and D between adjacent data lines to which data voltages of the same polarity are supplied. It is the same as the first embodiment shown in FIGS. 1 to 3 except that the lower first and third sub-pixels P1 and P3 are alternately and repeatedly arranged in the second direction. Accordingly, redundant descriptions will be omitted below.

First, referring to the first embodiment, as shown in FIG. 3, due to the pixel arrangement structure of the display panel 110, the 8m+4th data line (DL[8m) adjacent to each other and supplied with data voltages of the same polarity. +4]) and the vertical line (A) between the 8m+5th data line (DL[8m+5]) (hereinafter referred to as "8m+4th vertical line") with a high luminance ratio of green (G) and Second and fourth sub-pixels P2 and P4 corresponding to white (W) are disposed. In addition, the 8m+8th data line (DL[8m+8]) and the 8(m+1)+1st data line (DL[8(m+1)+1) are adjacent to each other and supplied with data voltages of the same polarity. ]), the second and fourth sub-pixels P2 and P4 are also disposed in the vertical line B (hereinafter, referred to as "8m+8th vertical line").

In this specification, the luminance ratio means a ratio for realizing white by mixing red (R), green (G), blue (B), and white (W) colors. Illustratively, the luminance ratio may be set based on the CIE u'v' coordinate system established in 1978 by the Commission Internationale de l'Eclairage (CIE). In this case, the luminance ratio of red (R), green (G), blue (B), and white (W) may be 2:7:1:10.

As described above, the second and fourth sub-pixels P2 and P4 corresponding to green (G) and white (W) include the first and third sub-pixels P1 and P4 corresponding to red (R) and blue (B). The luminance ratio is higher than that of P3).

Therefore, as in the first embodiment, the 8m + 4th and 8m + 8th vertical lines (A, B) disposed between data lines adjacent to each other and supplied with data voltages of the same polarity have a second high luminance ratio. and when the fourth sub-pixels P2 and P4 are repeatedly arranged, the vertical lines A and B may be displayed brighter than other vertical lines around them. As a result, since the subpixels to which the data voltages of the same polarity are supplied are arranged in the second direction, the vertical lines A and B having different display characteristics from other vertical lines around them can be seen more clearly.

In order to solve this problem, as shown in FIG. 4, according to the second embodiment, 8m+4th and 8m+8th vertical lines disposed between adjacent data lines to which data voltages of the same polarity are supplied. The pixel arrangement structure of the display panel 110' is changed so that subpixels having a high luminance ratio are not arranged on the lines C and D.

Specifically, according to the second embodiment, the subpixels P connected to odd-numbered gate lines GL[1], ... GL[2n+1], ... are second, third, and second from the left end. 4 and the first sub-pixels P2', P3', P4', and P1' are repeatedly arranged side by side in the first direction (horizontal direction).

In addition, the subpixels P connected to the even gate lines GL[2], ... GL[2n + 2], ... are the fourth, first, second, and third subpixels from the left end ( P4', P1', P2', P3') are repeatedly arranged side by side along the first direction (horizontal direction) in order.

In other words, the display panel 110' according to the second embodiment has a pixel arrangement structure shifted to the right by 1 dot in each horizontal line compared to the pixel arrangement structure of the display panel 110 according to the first embodiment. It is done.

As shown in FIG. 5, the display panel 110' according to the second embodiment may be implemented by including a color filter CF having a filter arrangement different from that of the first embodiment.

For example, the color filters CF of the display panel 110' according to the second embodiment include a green filter 116G, a blue filter 116B, and a white filter 116W repeatedly arranged from the left end of odd-numbered horizontal lines. and a red filter 116R. And, although not shown in FIG. 5, referring to FIG. 4, the color filter CF of the display panel 110' includes a white filter 116W and a red filter 116R repeatedly arranged from the left end of an even-th horizontal line. , It may include a green filter (116G) and a blue filter (116B).

As described above, according to the second embodiment, the 8m + 4th and 8m + 8th vertical lines (C, D) disposed between data lines adjacent to each other and supplied with data voltages of the same polarity, luminance ratios First and third subpixels P1' and P3' corresponding to the low red (R) and blue (B) colors are disposed. Also, data voltages of different polarities are supplied to the data lines DL disposed on both sides of the vertical line in which the second and fourth sub-pixels P2' and P4' having a high luminance ratio are repeatedly arranged.

Therefore, the visibility of the 8m+4th and 8m+8th vertical lines (C, D) displayed differently from other surrounding vertical lines may be reduced. As a result, the visibility of the vertical stripe defect may be reduced.

However, according to the second embodiment, unlike the first embodiment, the display panel 110' having a changed sub-pixel arrangement needs to be separately prepared. To this end, manufacturing facilities must be changed, which requires high costs.

Accordingly, the third embodiment of the present invention provides a liquid crystal display device capable of reducing the visibility of vertical lines while using the display panel 110 according to the first embodiment as it is.

6 and 7 are diagrams illustrating a display panel and a data line driver according to a first embodiment of the present invention. 8 and 9 are diagrams illustrating a sub-pixel arrangement and a data line driver of a display panel according to a third embodiment of the present invention.

First, the display panel and the data line driver according to the first embodiment will be described with reference to FIGS. 6 and 7 .

As shown in FIG. 6, the data line driver 120 according to the first embodiment includes a plurality of data output units 121, 122, 123, and 124 connected to every two data lines.

That is, the data line driver 120 includes the first and second data lines DL[1] and DL[2] and the 8m+1 and 8m+2 data lines DL[8m+1] and DL[8m+2]. ]), and the second data output unit 122 connected to the 8m+3rd and 8m+4th data lines (DL[8m+3], DL[8m+4]) ), the third data output unit 123 connected to the 8m+5th and 8m+6th data lines (DL[8m+5], DL[8m+6]), and the 8m+7th and 8m+8th and a fourth data output unit 124 connected to the data lines DL[8m+7] and DL[8m+8].

Here, each of the first, second, third, and fourth data output units 121, 122, 123, and 124 includes a positive polarity data generation unit 121H, 122H, 123H, 124H) and negative polarity data generators 121L, 122L, 123L, and 124L that generate negative polarity (-) data voltages.

And, during a period for displaying any one frame, the first and second data output units 121 and 122 transmit positive polarity data to odd-numbered data lines DL[8m+1] and DL[8m+3]. A data voltage of positive polarity (+) is supplied by the generators 121H and 122H, and the negative polarity data generators 121L and 122L are supplied to even data lines DL[8m+2] and DL[8m+4]. ) to supply negative polarity (-) data voltage. In addition, the third and fourth data output units 123 and 124 generate negative polarity by the negative data generators 123L and 124L on odd-numbered data lines DL[8m+5] and DL[8m+7]. The (-) data voltage is supplied, and the positive (+) data voltage by the positive polarity data generating units 123H and 124H is supplied to even data lines (DL[8m+6], DL[8m+8]) supply

Further, the data line driver 120 inverts the polarity of each data voltage supplied to the data lines DL for a period of displaying the next frame after a period of displaying one frame ends.

Accordingly, as shown in FIG. 7, in the next frame, the first and second data output units 121 and 122 transmit negative polarities to odd-numbered data lines DL[8m+1] and DL[8m+3]. The data voltage of negative polarity (-) is supplied by the data generators 121L and 122L, and the positive polarity data generator 121H to the even data lines DL[8m+2] and DL[8m+4] 122H) to supply positive polarity (+) data voltage. In addition, the third and fourth data output units 123 and 124 generate positive polarity by the positive polarity data generating units 123H and 124H on odd-numbered data lines DL[8m+5] and DL[8m+7]. A (+) data voltage is supplied, and a negative (-) data voltage by the negative polarity data generating units 123L and 124L to even data lines (DL[8m+6], DL[8m+8]) supply

As mentioned above, due to the pixel arrangement structure of the display panel 110 according to the first embodiment, the 8m+4th and 8m+8th lines disposed between adjacent data lines to which data voltages of the same polarity are supplied. The second and fourth sub-pixels P2 and P4 having a high luminance ratio are repeatedly arranged on the vertical lines A and B. As a result, since the subpixels to which the data voltages of the same polarity are supplied are arranged in the second direction, the vertical lines A and B having different display characteristics from other vertical lines around them can be seen more clearly.

In order to solve this problem, as shown in FIG. 8, according to the third embodiment of the present invention, the second and fourth sub-pixels P2 and P4 having a high luminance ratio are alternately and repeatedly arranged in the second direction. Data voltages of the same polarity are not supplied to the data lines (DL [8m + 4], DL [8m + 5]) disposed on both sides of the 8m + 4th vertical line (A in FIGS. 6 and 7). , the data lines (DL[8m) disposed on both sides of the 8m+8th vertical line (B in FIGS. 6 and 7) in which the second and fourth subpixels P2 and P4 are alternately and repeatedly arranged in the second direction. +8] and DL[8(m+1)+1]), the connection between the data lines DL and the data line driver 220 is changed so that the data voltages of the same polarity are not supplied. As described above, since the liquid crystal display device according to the third embodiment of the present invention is the same as the first embodiment except for the data line driver 220, redundant description will be omitted below.

Specifically, according to the third embodiment, the data line driver 220 includes a dummy data output unit DM connected to the first data line DL[1] and first to th data lines connected to the other data lines. It includes 4 data output units (221, 222, 223, 224). Illustratively, as shown in FIG. 8 , the first data line DL[1] may be the leftmost one among the data lines DL.

More specifically, the data line driver 220 includes a dummy data output unit DM connected to the first data line DL[1], 8m+2 and 8m+3 data lines DL[8m+2], 1st data output unit 221 connected to DL[8m+3]), 2nd connected to 8m+4th and 8m+5th data lines (DL[8m+4], DL[8m+5]) The third data output unit 223 connected to the data output unit 222, the 8m+6th and 8m+7th data lines (DL[8m+6], DL[8m+7]) and the 8m+8th and and a fourth data output unit 224 connected to the 8(m+1)+1th data lines (DL[8m+8], DL[8(m+1)+1]).

Here, each of the dummy, first, second, third, and fourth data output units DM, 221, 222, 223, and 224 generates a positive (+) data voltage. 221H, 222H, 223H, 224H) and negative polarity data generators (DML, 221L, 222L, 223L, 224L) that generate negative (-) data voltages.

The dummy data output unit DM applies a data voltage having the same polarity as the data voltage supplied to the first data line DL[1] and the second data line DL[2] adjacent in the first direction to the first data line DL[ 1]).

For example, during a period for displaying any one frame, the first and second data output units 221 and 222 transmit positive polarity to even data lines DL[8m+2] and DL[8m+4]. A data voltage of positive polarity (+) is supplied by the data generators 221H and 222H, and the negative polarity data generator 221L to the odd-numbered data lines DL[8m+3] and DL[8m+5] 222L) supplies negative polarity (-) data voltage. In addition, the dummy data output unit (DM) and the third and fourth data output units 223 and 224 are negative polarity data generators (DL[8m+6] and DL[8m+8]) 223L, 224L) supply negative polarity (-) data voltage, and supply positive polarity to odd-numbered data lines (DL[1], DL[8m+7], DL[8(m+1)+1]) A data voltage of positive polarity (+) is supplied by the data generators 223H and 224H.

Also, the data line driver 220 inverts the polarity of the data voltage supplied to each data line DL during a period for displaying the next frame.

Therefore, as shown in FIG. 9, during the period for displaying the next frame, the first and second data output units 221 and 222 output even data lines DL[8m+2] and DL[8m+4]. ]) is supplied with a negative (-) data voltage by the negative data generators 221L and 222L, and positive data is supplied to odd-numbered data lines (DL[8m+3], DL[8m+5]). A data voltage of positive polarity (+) is supplied by the generators 221H and 222H. In addition, the dummy data output unit (DM) and the third and fourth data output units 223 and 224 are positive polarity data generators (DL[8m+6] and DL[8m+8]) 223H, 224H), supply the data voltage of positive polarity (+), and supply the negative polarity to the odd-numbered data lines (DL[1], DL[8m+7], DL[8(m+1)+1]) A data voltage of negative polarity (-) is supplied by the data generators 223L and 224L.

As described above, according to the third embodiment, the data line driver 220 further includes a dummy data output unit DM connected to the first data line DL[1]. The dummy data output unit DM supplies a data voltage having the same polarity as that of the second data line DL[2] to the first data line DL[1].

That is, when connecting the data lines DL and the data line driver 220, the first data line DL[1] is connected to the dummy data output unit DM. And, except for the first data line (DL[1]), the remaining data lines (DL[2], DL[3], ... DL[8m+2], DL[8m+3], DL[8m+4], DL[8m+5], DL[8m+6], DL[8m+7], DL[8m+8], DL[8(m+1)+1]) are the first to the 8th line units. It is connected to 4 data output units (221, 222, 223, 224).

In other words, compared to the data line driver 120 according to the first embodiment, the data line driver 220 according to the third embodiment is a dummy data output unit DM connected to the first data line DL[1]. ), the data lines other than the first data line DL[1] are shifted and connected by one line.

Thus, according to the third embodiment, vertical lines A and B in which the second and fourth subpixels P2 and P4 corresponding to green (G) and white (W) having a high luminance ratio are alternately and repeatedly arranged Data voltages of the same polarity are prevented from being supplied to the data lines disposed on both sides of each. That is, data voltages of different polarities are supplied to the data lines DL disposed on both sides of a vertical line in which the second and fourth sub-pixels P2 and P4 having a high luminance ratio are repeatedly arranged. And, instead of green (G) and white (W) with high luminance ratio, red (R) with low luminance ratio is applied to vertical lines (E, F, G) between data lines to which data voltages of the same polarity are supplied. and the first and third sub-pixels P1 and P3 corresponding to blue (B) are alternately and repeatedly arranged.

Therefore, without changing the pixel arrangement structure of the display panel 110, as in the second embodiment, the vertical lines A and B formed of the second and fourth sub-pixels P2 and P4 having a high luminance ratio are formed. A vertical stripe defect can be prevented. Accordingly, the high cost of preparing a display panel having a changed pixel arrangement structure can be reduced while the visibility of the vertical stripe defect can be reduced.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the technical spirit of the present invention. Conventionally in the art to which the present invention belongs It will be clear to those who have knowledge of

100: liquid crystal display device 110: display panel
120: data line driver 130: gate line driver
140: timing controller P: subpixel
GL: gate line DL: data line
PA1, PA2, PA3, PA4: first, second, third and fourth pixel areas
CF: color filter
P1, P2, P3, P4: first, second, third and fourth sub-pixels
R, G, B, W: red, green, blue and white
(+): data voltage of positive polarity
(-): data voltage of negative polarity
A, B, C, D, E, F: vertical lines
121, 122, 123, 124: first, second, third and fourth data output units
220: data line driving unit DM: dummy data output unit
221, 222, 223, 224: first, second, third and fourth data output units

Claims (11)

Gate lines in a first direction, data lines in a second direction crossing the first direction, and a plurality of subpixels corresponding to a plurality of pixel areas defined by the gate lines and the data lines a display panel comprising; and
a data line driver supplying respective data voltages to the data lines;
The data line driver
a dummy data output unit connected to the first data line;
a first data output unit connected to the 8m+2nd and 8m+3rd data lines;
a second data output unit connected to the 8m+4th and 8m+5th data lines;
a third data output unit connected to the 8m+6th and 8m+7th data lines; and
A liquid crystal display device including a fourth data output unit connected to the 8m+8th and 8(m+1)+1th data lines.
According to claim 1,
The dummy data output unit supplies a data voltage having the same polarity as a data voltage supplied to a second data line adjacent to the first data line to the first data line.
According to claim 1,
The data line driver, during a period for displaying any one frame,
A data voltage of a first polarity is supplied to the first data line, the 8m+2th data line, the 8m+4th data line, the 8m+7th data line, and the 8(m+1)+1th data line. do,
supplying a data voltage of a second polarity different from the first polarity to the 8m+3rd data line, the 8m+5th data line, the 8m+6th data line, and the 8m+8th data line;
and inverting the polarity of each data voltage supplied to the data lines during a period of displaying a next frame after the period of displaying one frame is over.
According to claim 1,
The plurality of subpixels are composed of first, second, third, and fourth subpixels corresponding to four different colors,
A liquid crystal display in which at least two subpixels having a low luminance ratio among the first, second, third, and fourth subpixels are alternately and repeatedly disposed between adjacent data lines to which data voltages of the same polarity are supplied. .
According to claim 1,
Among the plurality of subpixels, subpixels connected to the 2n+1th gate line are connected to a data line on one side of the subpixels connected to the 2n+1th gate line, and the first, second, third and fourth subpixels are are repeatedly arranged side by side along the first direction in the order of
Subpixels connected to the 2n+2th gate line among the plurality of subpixels are connected to the data line on the other side of the subpixels connected to the 2n+2th gate line, and the third, fourth, first and second subpixels A liquid crystal display device that is repeatedly arranged side by side along the first direction in order.
According to claim 1,
The plurality of subpixels are composed of first, second, third, and fourth subpixels corresponding to four different colors,
A liquid crystal display device in which first and third sub-pixels having a low luminance ratio are alternately and repeatedly arranged in the second direction between adjacent data lines to which data voltages of the same polarity are supplied.
According to claim 1,
The plurality of subpixels are composed of first, second, third, and fourth subpixels corresponding to four different colors,
Data voltages of polarities opposite to each other are supplied to data lines disposed on both sides of a vertical line in which the second and fourth sub-pixels having a high luminance ratio are alternately and repeatedly arranged in the second direction.
gate lines in a first direction;
data lines in a second direction crossing the first direction; and
a plurality of sub-pixels corresponding to a plurality of pixel areas defined by the gate line and the data line;
The plurality of subpixels are composed of first, second, third, and fourth subpixels corresponding to four different colors,
A data voltage of a first polarity is supplied to the 8m+1st, 8m+3rd, 8m+6th, and 8m+8th data lines among the data lines during a period for displaying any one frame; Data voltages of a second polarity opposite to the first polarity are supplied to the 8m+2nd, 8m+4th, 8m+5th, and 8m+7th data lines,
After the period of displaying one frame ends, the polarity of each data voltage supplied to the data lines is inverted during a period of displaying the next frame;
At least two subpixels having a low luminance ratio among the first, second, third, and fourth subpixels are alternately repeated in the second direction between adjacent data lines to which data voltages of the same polarity are supplied. Arranged display panel.
According to claim 8,
Among the plurality of subpixels, subpixels connected to the 2n+1th gate line are connected to a data line on one side of the subpixels connected to the 2n+1th gate line, and the first, second, third and fourth subpixels are are repeatedly arranged side by side along the first direction in the order of
Subpixels connected to the 2n+2th gate line among the plurality of subpixels are connected to the data line on the other side of the subpixels connected to the 2n+2th gate line, and the third, fourth, first and second subpixels Display panels that are sequentially and repeatedly arranged side by side along the first direction.
According to claim 8,
The display panel of claim 1 , wherein the first and third sub-pixels are alternately and repeatedly arranged in the second direction between data lines that are adjacent to each other and supplied with data voltages of the same polarity.
According to claim 8,
Data voltages of polarities opposite to each other are supplied to data lines disposed on both sides of a vertical line in which the second and fourth sub-pixels having the high luminance ratio are alternately and repeatedly arranged in the second direction.

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