KR102559092B1 - Current Sensing Device And Organic Light Emitting Display Device Including The Same, And Pixel Compensation Method Of Organic Light Emitting Display Device - Google Patents

Abstract

The pixel sensing device of the present invention includes a plurality of current integrators for sensing pixel current representing driving characteristics of pixels. Each of the current integrators includes an op amp having an inverting input terminal to which a negative input voltage is received by the pixel current, a non-inverting input terminal to which a positive input voltage is received by the pixel current, and an output terminal to which an integrated voltage corresponding to the pixel current is output, and a feedback capacitor connected between the inverting input terminal and the output terminal. The operational amplifier includes a pre-amplifier unit having the inverting input terminal and the non-inverting input terminal and lowering an amplifier input gain; and two gain amplifiers which receive the output of the preamplifier unit and increase an amplifier output gain higher than the amplifier input gain.

Description

Pixel sensing device, organic light emitting display device including the same, and pixel compensation method of the organic light emitting display device

The present invention relates to an organic light emitting display device, and more particularly, to a pixel sensing device, an organic light emitting display device including the same, and a pixel compensation method of the organic light emitting display device.

An active matrix type organic light emitting display device includes an organic light emitting diode (OLED) that emits light by itself, and has advantages of fast response speed, high luminous efficiency, luminance, and viewing angle.

An organic light emitting display device arranges pixels each including an OLED in a matrix form, and adjusts luminance of the pixels according to gray levels of image data. Each of the pixels includes a driving element that controls a driving current flowing through the OLED according to a voltage applied between the gate electrode and the source electrode, that is, a driving TFT (Thin Film Transistor). The driving characteristics of OLEDs and driving TFTs change due to temperature or deterioration. If the driving characteristics of the OLED and/or the driving TFT are different for each pixel, it is difficult to implement a desired image because the luminance between the pixels is different even if the same image data is written.

An external compensation technique is known to compensate for a change in driving characteristics for an OLED or driving TFT. External compensation technology senses a change in driving characteristics of an OLED or driving TFT and modulates image data based on the sensing result.

An organic light emitting display device uses a current integrator to sense a pixel current corresponding to a change in driving characteristics of an OLED or driving TFT. The current integrator includes an operational amplifier and a feedback capacitor connected between an inverting input terminal and an output terminal of the operational amplifier. When the pixel current is input to the inverting input terminal of the op amp, the amount of change in the pixel current can be known through the sensing voltage accumulated in the feedback capacitor for a predetermined time (sensing time). Since the input impedance of the op amp is not infinite, not all of the pixel current can be transferred to the feedback capacitor, and some of the pixel current may flow into the op amp and become leakage current.

With the trend of high resolution and high definition, the pixel current is getting smaller. As can be seen through the formula C (feedback capacitor capacity) * V (output voltage) = I (pixel current) * T (sensing time), the capacity of the feedback capacitor must be designed to be small in order to sense the microcurrent while maintaining the sensing time and output voltage (or sensing voltage) constant. However, if the capacitance of the feedback capacitor decreases, the impedance of the feedback capacitor may increase to the level of the input impedance of the op amp. In this case, instead of reducing the pixel current applied to the feedback capacitor, the leakage current flowing into the inside of the op amp increases, making accurate sensing of the pixel current impossible. If the sensing performance is degraded, driving characteristics of the OLED and/or driving TFT cannot be accurately compensated.

On the other hand, factors that decrease screen uniformity may further include process deviations according to panel positions in addition to changes in driving characteristics of OLEDs or driving TFTs. Process variations include variations in the deposition thickness of TFTs and pixel components according to panel positions. This means the capacitance deviation of the capacitor connected to the gate electrode of the driving TFT. If this capacitance deviation is not compensated for, compensation performance for the driving TFT may deteriorate.

Accordingly, the present invention provides a pixel sensing device capable of reducing leakage current by increasing the input impedance of an operational amplifier included in a current integrator and an organic light emitting display device including the same.

Furthermore, the present invention provides an organic light emitting display device and a pixel sensing method thereof capable of improving compensation performance by further compensating not only the variation in characteristics of the driving TFT but also the variation in capacitance connected to the gate electrode of the driving TFT.

The pixel sensing device of the present invention includes a plurality of current integrators for sensing pixel current representing driving characteristics of pixels. Each of the current integrators includes an op amp having an inverting input terminal to which a negative input voltage is received by the pixel current, a non-inverting input terminal to which a positive input voltage is received by the pixel current, and an output terminal to which an integrated voltage corresponding to the pixel current is output, and a feedback capacitor connected between the inverting input terminal and the output terminal. The operational amplifier includes a pre-amplifier unit having the inverting input terminal and the non-inverting input terminal and lowering an amplifier input gain; and two gain amplifiers which receive the output of the preamplifier unit and increase an amplifier output gain higher than the amplifier input gain.

The present invention implements very high input impedance by lowering the amplifier input gain through the pre-amplifier unit and increasing the gains of the gain amplifying units at the rear of the pre-amplifier unit. According to the present invention, the leakage current component flowing into the op amp of the pixel current is reduced, and the effective current component applied to the feedback capacitor is increased accordingly, so that the pixel current can be accurately sensed. If the sensing performance is improved, driving characteristics of the OLED and/or driving TFT can be accurately compensated.

According to the present invention, compensation performance can be remarkably improved by further compensating not only the characteristic variation of the driving TFT but also the variation of the capacitance connected to the gate electrode of the driving TFT.

1 is a diagram showing an organic light emitting display device according to an exemplary embodiment of the present invention.
2 is a diagram showing a connection configuration between a data driving circuit and a pixel array including a pixel sensing device according to the present invention.
3 is a diagram showing a connection configuration of pixels constituting a pixel array.
4 is a diagram showing another connection configuration of pixels constituting a pixel array.
FIG. 5 is a diagram briefly showing a conventional current integrator having a 2-stage op amp without a preamplifier unit as a comparative example of the present invention.
6 is a schematic diagram showing a current integrator having a 3-stage op amp including a pre-amplifier unit as one sensing unit for implementing the pixel sensing device of the present invention.
FIG. 7 is a diagram showing a comparison between specifications of the 2-stage amplifier of FIG. 5 and the 3-stage amplifier of FIG. 6 .
8 to 10 are diagrams for explaining the configuration and input impedance of the 2-stage amplifier of FIG. 5 .
11 and 12 are diagrams for explaining the configuration and input impedance of the 3-stage amplifier of FIG. 6 .
FIG. 13 is a diagram for explaining a schematic operation of the 3-stage amplifier of FIG. 6 .
FIG. 14 is a diagram for explaining sensing the driving TFT characteristics of a pixel and the total capacitance connected to the gate electrode of the driving TFT using a current integrator including the 3-stage amplifier of FIG. 6 .
15 is a flowchart illustrating a pixel compensation method of an organic light emitting display device according to an exemplary embodiment of the present invention.
16 is a driving waveform diagram for sensing driving TFT characteristics.
17 is a driving waveform diagram for sensing the total capacitance connected to the gate electrode of the driving TFT.

Advantages and features of this specification, and methods of achieving them, will become clear with reference to embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the present embodiments make the disclosure of the present specification complete, and those skilled in the art are provided to fully inform the scope of the invention, and the present specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, so this specification is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on ~', 'upon ~', 'under ~', 'next to', etc., one or more other parts may be located between the two parts unless 'directly' or 'directly' is used.

Although first, second, etc. may be used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

Like reference numbers designate substantially like elements throughout the specification.

In this specification, a pixel circuit formed on a substrate of a display panel may be implemented as a TFT of an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but is not limited thereto and may be implemented as a TFT of a p-type MOSFET structure. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit from the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), since electrons are carriers, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in the n-type TFT, the direction of the current flows from the drain to the source. In contrast, in the case of a p-type TFT (PMOS), since a carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since holes flow from the source to the drain side in the p-type TFT, current flows from the source to the drain side. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on the applied voltage.

Hereinafter, embodiments of the present specification will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be mainly described as an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical spirit of the present specification is not limited to an organic light emitting display device and may be applied to an inorganic light emitting display device including an inorganic light emitting material.

In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted.

1 is a diagram showing an organic light emitting display device according to an exemplary embodiment of the present invention. 2 is a diagram showing a connection configuration between a data driving circuit and a pixel array including a pixel sensing device according to the present invention. 3 and 4 are diagrams showing various connection configurations of pixels constituting a pixel array.

1 to 4 , an organic light emitting display device according to an exemplary embodiment of the present invention may include a display panel 10, a timing controller 11, a data driving circuit 12, and a gate driving circuit 13. The data driving circuit 12 includes the pixel sensing device 122 according to an embodiment of the present invention.

A plurality of data lines 14 and sensing lines 16 and a plurality of gate lines 15 intersect in the display panel 10, and sensing pixels P are arranged in a matrix form at each crossing area to form a pixel array. As shown in FIG. 4 , the gate lines 15 may include a plurality of first gate lines 15A supplied with a scan control signal SCAN and a plurality of second gate lines 15B supplied with a sensing control signal SEN. However, when the scan control signal SCAN and the sensing control signal SEN have the same phase, the first and second gate lines 15A and 15B may be unified into one gate line 15 as shown in FIG. 3 .

Each pixel P may be connected to one of the data lines 14 , one of the sensing lines 16 , and one of the gate lines 15 . The pixels P constituting the pixel array may include a red pixel for displaying red, a green pixel for displaying green, a blue pixel for displaying blue, and a white pixel for displaying white. Four pixels including a red pixel, a green pixel, a blue pixel, and a white pixel may constitute one pixel unit UPXL. However, the configuration of the pixel unit UPXL is not limited thereto. A plurality of pixels P constituting the same pixel unit UPXL may share one sensing line 16 . However, although not shown in the drawings, a plurality of pixels P constituting the same pixel unit UPXL may be independently connected to different sensing lines. Each of the pixels P receives a high potential pixel voltage EVDD and a low potential pixel voltage EVSS from a power generator (not shown).

The pixel P of the present invention may include an OLED, a driving TFT (DT), a storage capacitor (Cst), a first switch TFT (ST1), and a second switch TFT (ST2) as shown in FIGS. 3 and 4, but is not limited thereto. The TFTs may be implemented as P-type, N-type, or hybrid types in which P-type and N-type are mixed. In addition, the semiconductor layer of the TFT may include amorphous silicon, polysilicon, or oxide.

OLED is a light emitting device. The OLED includes an anode electrode connected to the source node Ns, a cathode electrode connected to an input terminal of the low potential pixel voltage EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

The driving TFT (DT) is a driving element that controls the magnitude of a source-drain current (hereinafter, referred to as Ids) of the driving TFT (DT) input to the OLED according to a gate-source voltage (hereinafter, referred to as Vgs). The driving TFT (DT) has a gate electrode connected to the gate node Ng, a drain electrode connected to the input terminal of the high-potential pixel voltage EVDD, and a source electrode connected to the source node Ns. The storage capacitor Cst is connected between the gate node Ng and the source node Ns to maintain Vgs of the driving TFT DT for a certain period of time. The first switch TFT ST1 switches the electrical connection between the data line 14 and the gate node Ng according to the scan control signal SCAN. The first switch TFT (ST1) has a gate electrode connected to the first gate line 15A, a first electrode connected to the data line 14, and a second electrode connected to the gate node Ng. The second switch TFT (ST2) switches an electrical connection between the source node (Ns) and the sensing line 16 according to the sensing control signal (SEN). The second switch TFT ST2 includes a gate electrode connected to the second gate line 15B, a first electrode connected to the sensing line 16, and a second electrode connected to the source node Ns.

Meanwhile, the first gate line 15A and the second gate line 15B may be unified into one gate line 15 (see FIG. 3 ). In this case, the scan control signal SCAN and the sensing control signal SEN may have the same phase.

An organic light emitting display device having such a pixel array employs an external compensation technology. The external compensation technology senses the driving characteristics of the OLED and/or the driving TFT (DT) included in the pixels P_ and corrects the input image data according to the sensed value. The driving characteristic of the OLED means the operating point voltage of the OLED. The driving characteristic of the driving TFT (DT) means the threshold voltage of the driving TFT and the electron mobility of the driving TFT.

In addition, the external compensation technology of the present invention further includes sensing the total amount of charge accumulated in the capacitors of each pixel P in response to the sensing data voltage and correcting the input image data DATA according to the sensed value. Here, the capacitors include a storage capacitor Cst connected to a gate electrode of a driving TFT DT included in each pixel P and a parasitic capacitor.

The total capacitance of the capacitors connected to the gate electrode of the driving TFT (DT) may vary between the pixels P according to the deposition thickness of the driving TFT. In this case, even if the same data voltage for sensing is applied to the pixels P, the total amount of charge accumulated in the capacitors in each pixel P may vary. The present invention further senses the capacitance difference between the pixels P and additionally corrects the input image data DATA according to the sensing result, thereby dramatically increasing compensation performance. The organic light emitting display device of the present invention performs an image display operation and an external compensation operation. The external compensation operation may be performed in a vertical blank period during video display, or in a power-on sequence period before video display starts, or in a power-off sequence period after video display ends. The vertical blank period is a period in which video data is not written, and is arranged between vertical active periods in which one frame of video data is written. The power-on sequence period refers to a period from when driving power is turned on until an image is displayed. The power-off sequence period refers to a period from when an image is displayed to when driving power is turned off.

The timing controller 11 generates a data control signal DDC for controlling the operating timing of the data driving circuit 12 and a gate control signal GDC for controlling the operating timing of the gate driving circuit 13 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The timing controller 11 temporally separates a period in which image display is performed and a period in which external compensation is performed, and control signals DDC and GDC for image display and control signals DDC and GDC for external compensation can be generated differently.

The gate control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), and the like. The gate start pulse GSP is applied to the gate stage generating the first scan signal and controls the gate stage to generate the first scan signal. The gate shift clock GSC is a clock signal commonly input to the gate stages and is a clock signal for shifting the gate start pulse GSP.

The data control signal DDC includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). The source start pulse SSP controls data sampling start timing of the data driving circuit 12 . The source sampling clock SSC is a clock signal that controls data sampling timing in each of the source drive ICs based on a rising or falling edge. The source output enable signal SOE controls output timing of the data driving circuit 12 . The data control signal DDC includes various signals for controlling the operation of the pixel sensing device 122 included in the data driving circuit 12 .

The timing controller 11 receives a digital sensing result value SD according to an external compensation operation from the data driving circuit 12 . The timing controller 11 corrects the input image data DATA based on the digital sensing result value SD to compensate for the deviation in degradation of the driving TFT between the pixels P or the deviation in degradation of the OLED between the pixels P. In addition, the timing controller 11 can compensate for the deviation of the deposition thickness of the driving TFT between the pixels P. The timing controller 11 transmits the corrected digital image data DATA to the data driving circuit 12 during an operation period for displaying an image.

The data driving circuit 12 includes at least one source driver integrated circuit (IC). This source driver IC includes a latch array (not shown), a plurality of digital-to-analog converters 121 (hereinafter referred to as DACs) connected to each data line 14, a pixel sensing device 122 connected to each sensing line 16 through a sensing channel, and an analog-to-digital converter (ADC).

The latch array latches the digital image data DATA input from the timing controller 11 based on the data control signal DDC and supplies it to the DAC. During an image display operation, the DAC may convert digital image data (DATA) input from the timing controller 11 into data voltages for image display and supply them to the data lines 14 . During an external compensation operation, the DAC may generate a data voltage for sensing of a certain level and supply it to the data lines 14 .

The pixel sensing device 122 includes a plurality of sensing units SU.

Each of the sensing units SU serves to sense the pixel current flowing in each pixel P through the sensing line 16 in response to the data voltage for sensing. In addition, each of the sensing units SU serves to sense the total amount of charge accumulated in the capacitors of each pixel P through the data line 14 in response to the data voltage for sensing.

Each of the sensing units SU may be implemented as a current sensing type including a current integrator. Each of the sensing units SU has a 3-stage op amp structure to increase the input impedance of the op amp included in the current integrator. The input impedance of a 3-stage op amp is proportional to the amplifier output gain and inversely proportional to the amplifier input gain. Therefore, the 3-stage op-amp configuration includes a pre-amplifier section (first amplifier stage) that relatively lowers the amplifier input gain, and two gain amplification sections (second and third amplifier stages) that increase the amplifier output gain than the amplifier input gain. The sensing units SU constituting the pixel sensing device of the present invention will be described in detail with reference to FIGS. 6 and 7 and FIGS. 11 and 12 .

The gate driving circuit 13 generates the scan control signal SCAN according to the image display operation and the external compensation operation based on the gate control signal GDC, and supplies it to the first gate lines 15A. The gate driving circuit 13 generates a sensing control signal SEN suitable for an image display operation and an external compensation operation based on the gate control signal GDC, and then supplies the sensing control signal SEN to the second gate lines 15B. Meanwhile, the gate driving circuit 13 may generate a scan control signal SCAN and a sensing control signal SEN of the same phase according to an image display operation and an external compensation operation based on the gate control signal GDC, and then supply them to the gate lines 15.

FIG. 5 is a diagram briefly showing a conventional current integrator having a 2-stage op amp without a preamplifier unit as a comparative example of the present invention. 6 is a schematic diagram showing a current integrator having a 3-stage op amp including a pre-amplifier unit as one sensing unit for implementing the pixel sensing device of the present invention. And, FIG. 7 is a diagram showing a comparison between specifications of the 2-stage amplifier of FIG. 5 and the 3-stage amplifier of FIG. 6 .

In the case of the conventional current integrator having a 2-stage operational amplifier (AMP) as shown in FIGS. 5 and 7 , since there is no preamplifier and the amplifier output gain is relatively low, the effective current component (Iint) applied to the feedback capacitor (Cfb) out of the pixel current (Ipix) is reduced. In addition, since the leakage current component Ileak flowing into the inside of the operational amplifier AMP increases instead of the effective current component Iint decreasing, accurate sensing of the pixel current Ipix becomes impossible. If the sensing performance is degraded, driving characteristics of the OLED and/or driving TFT cannot be accurately compensated.

On the other hand, in the case of the current integrator of the present invention having a 3-stage operational amplifier (AMP) as shown in FIGS. 6 and 7, since the amplifier input gain is lowered by the added pre-amplifier unit and the amplifier output gain is relatively high by the two gain amplification units with high amplification, the leakage current component (Ileak) flowing into the operational amplifier (AMP) among the pixel current (Ipix) is remarkably reduced, and the reduced effective current applied to the feedback capacitor (Cfb) Ingredient (Iint) is increased. Therefore, according to the present invention, it is possible to more accurately sense the pixel current Ipix compared to the conventional current integrator having a 2-stage operational amplifier.

8 to 10 are diagrams for explaining the configuration and input impedance of the 2-stage amplifier of FIG. 5 .

Referring to FIG. 8 , the current integrator according to the comparative example includes an operational amplifier (AMP) having an inverting input terminal 51 receiving a (-) input voltage (Vin-) from the pixel current, a non-inverting input terminal 52 receiving a (+) input voltage (Vin+) from the pixel current, and an output terminal 53 outputting an integrated voltage (Vout) corresponding to the pixel current, and a feedback capacitor connected between the inverting input terminal 51 and the output terminal 53. (Cfb). The (+) input voltage (Vin+) means Vcm in FIG. 6 .

The operational amplifier AMP includes a first gain stage STG1 for primary amplification of the amplifier output gain and a second gain stage STG2 for secondary amplification of the amplifier output gain.

The first gain stage STG1 is implemented with the first to fifth MOS transistors M1 to M5. The gate electrode of the first MOS transistor M1 is connected to the inverting input terminal 51, the drain electrode of the first MOS transistor M1 is connected to the first node Na1, and the source electrode of the first MOS transistor M1 is connected to the second node Na2. The gate electrode of the second MOS transistor M2 is connected to the non-inverting input terminal 52, the drain electrode of the second MOS transistor M2 is connected to the third node Na3, and the source electrode of the second MOS transistor M2 is connected to the second node Na2. The gate electrode and drain electrode of the third MOS transistor M3 are connected to the first node Na1, and the source electrode of the third MOS transistor M3 is connected to the high potential operating voltage source VDD. The gate electrode of the fourth MOS transistor M4 is connected to the first node Na1, the source electrode of the fourth MOS transistor M4 is connected to the high potential operating voltage source VDD, and the drain electrode of the fourth MOS transistor M4 is connected to the third node Na3. The gate electrode of the fifth MOS transistor M5 is connected to the bias voltage source Vb, the drain electrode of the fifth MOS transistor M5 is connected to the second node Na2, and the source electrode of the fifth MOS transistor M5 is connected to the low potential operating voltage source GND. Here, the first, second, and fifth MOS transistors M1 , M2 , and M5 are implemented as N-type, and the third and fourth MOS transistors M3 and M4 are implemented as P-type.

The second gain stage STG2 is implemented with the sixth and seventh MOS transistors M6 and M7. The gate electrode of the sixth MOS transistor M6 is connected to the third node Na3, the source electrode of the sixth MOS transistor M6 is connected to the high potential operating voltage source VDD, and the drain electrode of the sixth MOS transistor M6 is connected to the output terminal 53. The gate electrode of the seventh MOS transistor M7 is connected to the bias voltage source Vb, the drain electrode of the seventh MOS transistor M7 is connected to the output terminal 53, and the source electrode of the seventh MOS transistor M7 is connected to the low potential operating voltage source GND. Here, the sixth MOS transistor M6 is implemented as a P type, and the seventh MOS transistor M7 is implemented as an N type.

In the feedback structure of such an operational amplifier (AMP), small signal analysis of the first and third MOS transistors M1 and M3 affected by the (-) input voltage Vin- to obtain the input impedance can be expressed as shown in FIG. In FIG. 9 , Vx means a test voltage for calculating input impedance, and gm1Vx means a test voltage Vx in the first gain stage STG1 and a current generated by the first MOS transistor M1. gm1 means the transconductance of the first MOS transistor M1, gm3 means the transconductance of the third MOS transistor M3, Cgd means the parasitic capacitance between the gate and drain of the first MOS transistor M1, and Cgs means the parasitic capacitance between the gate and the source of the first MOS transistor M1.

Input impedance based on the first and third MOS transistors M1 and M3 of FIG. 9 may be modeled as in Equation 1. In Equation 1, Ix means a test current input from the test voltage source Vx to the first gain stage STG1.

[Equation 1]

Subsequently, the input impedance (Zin, closed) of the feedback circuit as shown in Equation 2 can be obtained from the entire small signal model of the feedback circuit as shown in FIG. 10 . In Equation 2, β is a feedback factor and means the magnitude of feedback from the amplifier output terminal 53 to the inverting input terminal 51, and S means the angular frequency. Also, Av means the amplifier output gain, and CF means the capacity of the feedback capacitor.

[Equation 2]

In order to reduce the leakage current component (Ileak) in FIG. 5 described above, the input impedance (Zin, closed) must be increased. However, as can be seen from Equation 2, the input impedance (Zin, closed) is determined according to the gm1/gm3 factor related to the amplifier input gain and βAv related to the amplifier output gain. Therefore, in order to increase the input impedance (Zin, closed), gm1/gm3 must be reduced and/or βAv must be increased. To decrease gm1/gm3, the amplifier input gain must be reduced, and to increase βAv, the amplifier output gain must be increased.

11 and 12 are diagrams for explaining the configuration and input impedance of the 3-stage amplifier of FIG. 6 .

Referring to FIG. 11, the current integrator according to an embodiment of the present invention has an inverting input terminal 51 receiving a (-) input voltage (Vin-) from the pixel current, a non-inverting input terminal 52 receiving a (+) input voltage (Vin+) from the pixel current, and an operational amplifier (AMP) having an output terminal 53 outputting an integrated voltage (Vout) corresponding to the pixel current, and between the inverting input terminal 51 and the output terminal 53. It includes a connected feedback capacitor (Cfb).

The operational amplifier AMP has a 3-stage configuration including first to third amplifier stages STG1 to STG3. The first amplifier stage STG1 of the operational amplifier AMP is a pre-amplifier unit and serves to lower the amplifier input gain. The second and third amplifier stages STG2 and STG3 of the operational amplifier AMP are first and second gain amplifiers, and serve to amplify the output gain of the amplifier far greater than the input gain of the amplifier.

The pre-amplifier unit STG1 has an inverting input terminal 61 and a non-inverting input terminal 62, and is implemented with first to fifth MOS transistors M1 to M5. The gate electrode of the first MOS transistor M1 is connected to the inverting input terminal 61, the drain electrode of the first MOS transistor M1 is connected to the first node Nb1, and the source electrode of the first MOS transistor M1 is connected to the second node Nb2. The gate electrode of the second MOS transistor M2 is connected to the non-inverting input terminal 62, the drain electrode of the second MOS transistor M2 is connected to the third node Nb3, and the source electrode of the second MOS transistor M2 is connected to the second node Nb2. The gate electrode and drain electrode of the third MOS transistor M3 are connected to the first node Nb1, and the source electrode of the third MOS transistor M3 is connected to the high potential operating voltage source VDD. The gate and drain electrodes of the fourth MOS transistor M4 are connected to the third node Nb3, and the source electrode of the fourth MOS transistor M4 is connected to the high potential operating voltage source VDD. The gate electrode of the fifth MOS transistor M5 is connected to the bias voltage source Vb, the drain electrode of the fifth MOS transistor M5 is connected to the second node Na2, and the source electrode of the fifth MOS transistor M5 is connected to the low potential operating voltage source GND. Here, the inverted output voltage Vo- of the preamplifier unit STG1 is applied to the first node Nb1, and the non-inverted output voltage Vo+ of the preamplifier unit STG1 is applied to the third node Nb3. Also, to secure operation stability, the first, second, and fifth MOS transistors M1, M2, and M5 are implemented as N-type, and the third and fourth MOS transistors M3 and M4 are implemented as P-type.

The first gain amplifier STG2 receives the outputs (Vo-, Vo+) of the pre-amplifier unit STG1 and increases the amplifier output gain by a first value through the MOS transistors M8 to M11 connected to the differential diode. The first gain amplifier STG2 amplifies the amplifier output gain much more than the first gain stage STG1 of FIG. 8 . Specifically, the amplification degree (gain) of the first gain stage STG1 of FIG. 8 is expressed in the form of g _m (r _o1 || r _o2 ), but the amplification degree (gain) of the first gain amplifier STG2 of the present invention can be expressed in the form of g _m7 r _o7 assuming gm11 = gm10. If the circuits of FIGS. 8 and 11 have the same gm and ro, g _m7 r _o7 is much larger than g _m (r _o1 || r _o2 ).

The first gain amplifier STG2 is implemented with sixth to twelfth MOS transistors M6 to M12. The gate electrode of the sixth MOS transistor M6 is connected to the third node Nb3, the drain electrode of the sixth MOS transistor M6 is connected to the fourth node Nb4, and the source electrode of the sixth MOS transistor M6 is connected to the fifth node Nb5. The gate electrode of the seventh MOS transistor M7 is connected to the first node Nb1, the drain electrode of the seventh MOS transistor M7 is connected to the sixth node Nb6, and the source electrode of the seventh MOS transistor M7 is connected to the fifth node Nb5. The gate electrode of the eighth MOS transistor M8 is connected to the sixth node Nb6, the source electrode of the eighth MOS transistor M8 is connected to the high potential operating voltage source VDD, and the drain electrode of the eighth MOS transistor M8 is connected to the fourth node Nb4. The gate and drain electrodes of the ninth MOS transistor M9 are connected to the fourth node Nb4, and the source electrode of the ninth MOS transistor M9 is connected to the high potential operating voltage source VDD. The gate electrode of the tenth MOS transistor M10 is connected to the fourth node Nb4, the source electrode of the tenth MOS transistor M10 is connected to the high potential operating voltage source VDD, and the drain electrode of the tenth MOS transistor M10 is connected to the sixth node Nb6. The gate electrode and the drain electrode of the eleventh MOS transistor M11 are connected to the sixth node Nb6, and the source electrode of the eleventh MOS transistor M11 is connected to the high potential operating voltage source VDD. The gate electrode of the twelfth MOS transistor M12 is connected to the bias voltage source Vb, the drain electrode of the twelfth MOS transistor M12 is connected to the fifth node Na5, and the source electrode of the twelfth MOS transistor M12 is connected to the low potential operating voltage source GND. Here, to secure operation stability, the sixth, seventh, and twelfth MOS transistors M6, M7, and M12 are implemented as N types, and the eighth to eleventh MOS transistors M8 to M11 are implemented as P types.

The second gain amplifier STG3 has an output terminal 63 and is connected to the first gain amplifier STG2 through the sixth node Nb6. The second gain amplifier STG3 increases the output gain of the amplifier by a second value, and the second value is lower than the first value of the first gain amplifier STG2. The second gain amplifier STG3 may have an amplification degree (gain) similar to that of the second gain stage STG2 of FIG. 8 .

The second gain amplifier STG3 is implemented with thirteenth and fourteenth MOS transistors M13 and M14. The gate electrode of the thirteenth MOS transistor M13 is connected to the sixth node Nb6, the source electrode of the thirteenth MOS transistor M13 is connected to the high potential operating voltage source VDD, and the drain electrode of the thirteenth MOS transistor M13 is connected to the output terminal 63. The gate electrode of the fourteenth MOS transistor M14 is connected to the bias voltage source Vb, the drain electrode of the fourteenth MOS transistor M14 is connected to the output terminal 63, and the source electrode of the fourteenth MOS transistor M14 is connected to the low potential operating voltage source GND. Here, the thirteenth MOS transistor M13 is implemented as a P type and the fourteenth MOS transistor M14 is implemented as an N type so as to ensure operational stability.

Since this operational amplifier AMP has a mutually symmetrical structure, a half circuit analysis method of dividing the tail current of the fifth and twelfth MOS transistors M5 and M12 in half for analysis can be applied. Therefore, in the feedback structure of the op amp (AMP) described above, the present invention can calculate the input impedance by applying the half-circuit analysis method based on the (-) input voltage (Vin-). A small signal analysis of an operational amplifier (AMP) according to the half circuit analysis method can be expressed as shown in FIG. 12 .

12, V1 means the inverted output voltage (Vo-) of the preamplifier unit (STG1), V2 means the voltage applied to the sixth node (Nb6), and Vx means the test voltage source for calculating the input impedance. gm1, gm3, gm10, gm11, and gm13 denote transconductances of the first, third, tenth, eleventh, and thirteenth MOS transistors M1, M3, M10, M11, and M13, respectively. gm1Vx denotes a test current input to the gate electrode of the first MOS transistor M1, gm7V1 denotes an operating current input to the gate electrode of the seventh MOS transistor M7, and gm13V2 denotes an operating current input to the gate electrode of the thirteenth MOS transistor M13. Cgd1 refers to the parasitic capacitance between the gate and drain of the first MOS transistor M1, and Cgs1 refers to the parasitic capacitance between the gate and the source of the first MOS transistor M1. Cgd7 means the parasitic capacitance between the gate and drain of the seventh MOS transistor M7, and Cgs7 means the parasitic capacitance between the gate and the source of the seventh MOS transistor M7. ro1 means the impedance seen from the drain electrode of the first MOS transistor M1, ro7 means the impedance seen from the drain electrode of the seventh MOS transistor M7, ro13 means the impedance seen from the drain electrode of the thirteenth MOS transistor M13, and ro14 means the impedance seen from the drain electrode of the fourteenth MOS transistor M14.

In the small signal modeling result of FIG. 12, the impedances (Zv1, Zv2) based on V1 and V2 are as shown in Equation 3. In Equation 3, Zv2 can be expressed by the impedance components (Cgs13, Cgd13, gm3V2, ro13, ro14) shown to the right of V2. And, Zv1 can be expressed by the impedance components (Cgs7, Cgd7, gm7V1, ro7, 1/(gm11-gm12), Zv2) seen from V1 to the right.

In Equation 3, ro13 ? ro14 means the impedance applied to the amplifier output terminal 63 of the second gain amplification unit STG3, and is seen at the drains of the 13th and 14th MOS transistors M13 and M14. It means parallel connection of impedances ro13 and ro14.

[Equation 3]

Re-expressing Vv1/Iv1 in Equation 3 is equivalent to Equation 4. Vv1/Iv1 is the calculated impedance excluding Cgs7 from Zv1. In Equation 4, S means each frequency.

[Equation 4]

The input impedance Zin based on the first, third, seventh, tenth, eleventh, thirteenth, and fourteenth MOS transistors M1, M3, M7, M10, M11, M13, and M14 of FIG. 12 may be modeled as in Equation 5.

[Equation 5]

Re-expressing Vin/Iin in Equation 5 is equivalent to Equation 6.

[Equation 6]

When Equation 6 is substituted into Equation 5, the input impedance Zin is expressed as Equation 7. In Equation 7, Av 1 means the amplifier input gain of the preamplifier unit STG1.

[Equation 7]

Therefore, the input impedance (Zin, closed) of the feedback circuit can be obtained from the entire small signal model of the feedback circuit as shown in Equation 8. In Equation 8, β is a feedback factor and means the magnitude of feedback from the amplifier output terminal 63 to the inverting input terminal 61, and S means the angular frequency. And, Av means the amplifier output gain, and is expressed as the product of the amplifier input gain (Av①) of the preamplifier unit (STG1), the gain (Av②) of the first gain amplifier unit (STG2), and the gain (Av③) of the second gain amplifier unit (STG3).

[Equation 8]

As can be clearly seen through Equation 8, the input impedance (Zin, closed) in the feedback circuit is inversely proportional to the amplifier input gain (Av①) and proportional to the amplifier output gain (Av). That is, the input impedance (Zin, closed) increases as the amplifier input gain (Av①) decreases and the amplifier output gain (Av) increases. The present invention implements a very high input impedance (Zin, closed) by lowering the amplifier input gain (Av①) through the preamplifier unit (STG1) and increasing the gains of the gain amplifiers (STG2, STG3) at the rear of the preamplifier unit (STG1). According to the present invention, the leakage current component Ileak flowing into the op amp AMP among the pixel current Ipix is reduced, and the effective current component Iint applied to the feedback capacitor Cfb increases accordingly, so that the pixel current Ipix can be accurately sensed. If the sensing performance is improved, driving characteristics of the OLED and/or driving TFT can be accurately compensated.

On the other hand, small-signal modeling of the second, fourth, sixth, eighth, ninth, thirteenth, and fourteenth MOS transistors M2, M4, M6, M8, M9, M13, and M14 may also be analyzed in the same way based on the (+) input voltage (Vin+) according to the half circuit analysis method.

FIG. 13 is a diagram for explaining a negative feedback operation of the 3-stage amplifier of FIG. 6 .

Referring to FIG. 13 , in the 3-stage amplifier (AMP) of the present invention, when the pixel current Ipix is applied through the sensing line, the gate voltage Vin- of the first MOS transistor M1 increases (that is, voltage ① increases). When the gate voltage (Vin-) of the first MOS transistor M1 increases, the drain voltage of the third MOS transistor M3 decreases (voltage decreases ②). When the drain voltage of the third MOS transistor M3 decreases, the gate voltage of the thirteenth MOS transistor M13 increases (ie, the voltage ③ increases), and the output voltage (integral voltage, Vout) decreases (ie, the voltage ④ decreases). When the output voltage Vout decreases, the gate voltage of the first MOS transistor M1 decreases (that is, voltage ⑤ decreases) due to negative feedback through the feedback capacitor Cfb. As such, the 3-stage amplifier (AMP) of the present invention senses the pixel current (Ipix) through the aforementioned negative feedback operation. Under the influence of ① voltage increase and ⑤ voltage decrease, the gate voltage Vin− of the first MOS transistor M1 becomes equal to the gate voltage Vin+ of the second MOS transistor M2. At this time, the output voltage Vout is lower than the gate voltage Vin+ of the second MOS transistor M2 due to the pixel current Ipix accumulated in the feedback capacitor Cfb.

FIG. 14 is a diagram for explaining sensing the driving TFT characteristics of a pixel and the total capacitance connected to the gate electrode of the driving TFT using a current integrator including the 3-stage amplifier of FIG. 6 .

Referring to FIG. 14 , the organic light emitting display device according to an embodiment of the present invention senses the pixel current of each pixel P and the total amount of charge accumulated in the capacitors of each pixel P using the current integrator CI including the aforementioned 3-stage amplifier AMP. In addition to the storage capacitor Cst, the capacitors may include a first parasitic capacitor Cgd connected between the gate electrode and the drain electrode of the driving TFT DT, a second parasitic capacitor Cgs connected between the gate electrode and the source electrode of the driving TFT DT, a third parasitic capacitor Cgs connected between the gate electrode and the source electrode of the first switch TFT ST1, and other parasitic capacitors.

The current integrator CI further includes a reset switch RST connected between the inverting input terminal (-) and the output terminal of the operational amplifier AMP. The reset switch RST may be connected in parallel with the feedback capacitor Cfb. The reset switch RST serves to initialize the voltage Vout of the output terminal of the operational amplifier AMP to the reference voltage Vpre of the non-inverting input terminal (+) prior to sensing. The reference voltage Vpre means Vcm in FIG. 6 .

The current integrator CI senses the pixel current flowing in each pixel P through the sensing lines 16 in response to the sensing data voltage Vdata-SEN, and senses the total charge accumulated in the capacitors Cst, Cgd, and Cgs of each pixel P through the data lines 14 in response to the sensing data voltage Vdata-SEN. The first sensing path (①) through the sensing line 16 and the second sensing path (②) through the data line 14 are selectively activated. That is, when the first sensing path ① is activated, the second sensing path ② is deactivated, and conversely, when the second sensing path ② is activated, the first sensing path ① is deactivated.

To this end, the organic light emitting display device of the present invention further includes a data supply switch (D-SW), a reference voltage supply switch (R-SW), a first sensing pass switch (SW1), and a second sensing pass switch (SW2). The data supply switch D-SW is connected between the output terminal of the sensing data voltage Vdata-SEN of the data driving circuit 12 and each data line 14 . The reference voltage supply switch R-SW is connected between the output terminal of the reference voltage VREF of the data driving circuit 12 and each sensing line 16 . The switch SW1 for the first sensing pass is connected between the inverting input terminal (-) of the operational amplifier AMP constituting the current integrator CI and each sensing line 16 . The second sensing pass switch SW2 is connected between the inverting input terminal (-) of the operational amplifier AMP and each data line 14 .

While the sensing unit SU of the present invention senses the pixel current of each pixel P, the data supply switch D-SW and the first sensing pass switch SW1 maintain an on state, and the reference voltage supply switch R-SW and the second sensing pass switch SW2 maintain an off state (see Tsen1 and Tsen2 in FIG. 16). In addition, while the sensing unit SU of the present invention senses the total amount of charge accumulated in the capacitors Cst, Cgd, and Cgs of each pixel P, the switch for the reference voltage supply (R-SW) and the switch for the second sensing pass (SW2) are maintained in an on state, and the switch for data supply (D-SW) and the switch for the first sensing pass (SW1) are maintained in an off state (see Tsen in FIG. 17).

Meanwhile, the sensing unit SU of the present invention may further include a sample and hold unit SH for sampling and holding the integrated voltage Vout of the current integrator CI. The sample and hold unit SH includes a sampling switch SAM and a holding switch HOLD connected in series between the current integrator CI and the analog-to-digital converter ADC, and a sampling capacitor Cs connected between a node between the switches SAM and HOLD and a ground voltage source GND.

15 is a flowchart illustrating a pixel compensation method of an organic light emitting display device according to an exemplary embodiment of the present invention. 16 is a driving waveform diagram for sensing driving TFT characteristics. 17 is a driving waveform diagram for sensing the total capacitance connected to the gate electrode of the driving TFT. A pixel compensation method of an organic light emitting display device according to an exemplary embodiment of the present invention will be described further with reference to FIG. 14 as follows. Referring to FIGS. The high gray pixel current flowing through the driving TFT (DT) is sensed (S1). The reason for sensing the pixel current twice is to find out both the change in the threshold voltage and the change in electron mobility of the driving TFT (DT).

In the first initialization period Tint1, the first switch TFT ST1 and the second switch TFT ST2 of the pixel P are turned on in response to the scan control signal SCAN, and the reset switch RST and sampling switch SAM of the sensing unit SU are turned on. Then, the data supply switch D-SW and the first sensing pass switch SW1 are turned on. Therefore, the gate-source voltage Vgs1 of the driving TFT DT is set as the difference between the sensing data voltage Vdata-SEN and the reference voltage Vpre, and the first pixel current corresponding to the gate-source voltage Vgs1 flows through the driving TFT DT.

In the first sensing period Tsen1, the first and second switch TFTs ST1 and ST2, the data supply switch D-SW, the first sensing pass switch SW1, and the sampling switch SAM maintain a turned-on state, and the reset switch RST is reversed to a turned-off state. Accordingly, the sensing unit SU integrates the first pixel current and outputs a first integrated voltage Vout that is lowered from the reference voltage Vpre. The first integral voltage Vout is sampled and stored in the sample and hold unit SH, and then output to the timing controller 11 as a first sensing result value through the analog-to-digital converter ADC.

In the second initialization period Tint2, the first switch TFT ST1 and the second switch TFT ST2 of the pixel P are turned on in response to the scan control signal SCAN, and the reset switch RST and sampling switch SAM of the sensing unit SU are turned on. Then, the data supply switch D-SW and the first sensing pass switch SW1 are turned on. Therefore, the gate-source voltage Vgs2 of the driving TFT DT is set as the difference between the sensing data voltage Vdata-SEN and the reference voltage Vpre, and the second pixel current corresponding to the gate-source voltage Vgs2 flows through the driving TFT DT.

In the second sensing period Tsen2, the first and second switch TFTs ST1 and ST2, the data supply switch D-SW, the first sensing pass switch SW1, and the sampling switch SAM maintain a turned-on state, and the reset switch RST is reversed to a turned-off state. Accordingly, the sensing unit SU integrates the second pixel current and outputs a second integrated voltage Vout that is lowered from the reference voltage Vpre. The second integral voltage Vout is sampled and stored in the sample and hold unit SH, and then output to the timing controller 11 as a second sensing result value through the analog-to-digital converter ADC.

The timing controller 11 compares the first and second sensing result values with the previous sensing result values to calculate a first compensation parameter for compensating for the change in threshold voltage and electron mobility of the driving TFT (DT) (S2).

The timing controller 11 firstly compensates the digital image data DATA to be written into the pixels P based on the first compensation parameter (S3).

14 to 15 and 17 , in the pixel compensation method of the organic light emitting display device according to an embodiment of the present invention, the total charge amount of the capacitors Cst, Cgd, and Cgs connected to the gate electrode of the driving TFT DT is sensed through a data writing period Twt, a boosting period Tbst, and a sensing period Tsen (S4).

In the data write period Twt, the first and second switch TFTs ST1 and ST2 and the data supply switch D-SW are turned on, and the reference voltage supply switch R-SW, the second sensing pass switch SW2 and the sampling switch SAM are turned off. Accordingly, the sensing data voltage Vdata-SEN is charged in the capacitors Cst, Cgd, and Cgs connected to the gate electrode of the driving TFT DT.

During the boosting period Tbst, the first and second switch TFTs ST1 and ST2 and the data supply switch D-SW are turned off, the reference voltage supply switch R-SW, the second sensing pass switch SW2 and the sampling switch SAM are turned on. Therefore, the gate-source voltage of the driving TFT (DT) is set as the difference between the sensing data voltage (Vdata-SEN) and the reference voltage (VREF), and the pixel current corresponding to the gate-source voltage flows through the driving TFT (DT). The gate electrode voltage DTG and the source electrode voltage DTS of the driving TFT DT are boosted by the pixel current while maintaining the gate-source voltage.

During the sensing period Tsen, the first and second switch TFTs ST1 and ST2 are turned on, the data supply switch D-SW remains turned off, and the reference voltage supply switch R-SW, the second sensing pass switch SW2 and the sampling switch SAM remain turned on. Accordingly, the sensing unit SU integrates the boosted gate electrode voltage DTG of the driving TFT DT and outputs an integrated voltage Vout that is lowered from the reference voltage Vpre. The integral voltage (Vout) is output to the timing controller 11 as a sensing result value through an analog-to-digital converter (ADC) after being sampled and stored in the sample and hold unit (SH).

The timing controller 11 calculates a second compensation parameter for compensating for a capacitance deviation connected to the gate electrode of the driving TFT (DT) by comparing the sensing result values with previous sensing result values (S5).

The timing controller 11 performs secondary compensation on the digital image data DATA to be written into the pixels P based on the second compensation parameter (S6).

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
14: data line 16: sensing line
15: gate line 122: pixel sensing device
STG1: pre-amp section STG2: first gain amplification section
STG3: 2nd gain amplifier D-SW: switch for data supply
SW1: switch for first sensing path SW2: switch for second sensing path
R-SW: switch for supplying reference voltage

Claims (16)

Including a plurality of current integrators for sensing the driving characteristics of the pixels,
Each of the current integrators includes an op amp having an inverting input terminal to which a (-) input voltage is received by the pixel current of the pixels, a non-inverting input terminal to which a (+) input voltage is received by the pixel current, and an output terminal to which an integrated voltage corresponding to the pixel current is output, and a feedback capacitor connected between the inverting input terminal and the output terminal;
The op amp,
a pre-amplifier unit having the inverting input terminal and the non-inverting input terminal and lowering an amplifier input gain; and
Includes two gain amplification units that receive the output of the preamplifier unit and increase an amplifier output gain higher than the amplifier input gain;
The two gain amplifiers,
a first gain amplification unit that receives the output of the preamplifier unit and increases the output gain of the amplifier by a first value through MOS transistors connected to differential diodes; and
A second gain amplifier having the output terminal and connected to the first gain amplifier unit to increase the output gain of the amplifier by a second value, wherein the second value is smaller than the first value;
The preamp section,
a first MOS transistor having a gate electrode connected to the inverting input terminal, a drain electrode connected to a first node, and a source electrode connected to a second node;
a second MOS transistor having a gate electrode connected to the non-inverting input terminal, a drain electrode connected to a third node, and a source electrode connected to the second node;
a third MOS transistor having a gate electrode and a drain electrode connected to the first node and a source electrode connected to a high-potential operating voltage source;
a fourth MOS transistor having a gate electrode and a drain electrode connected to the third node and a source electrode connected to the high-potential operating voltage source; and
A pixel sensing device including a fifth MOS transistor having a gate electrode connected to a bias voltage source, a drain electrode connected to the second node, and a source electrode connected to a low potential operating voltage source. delete delete According to claim 1,
An inverted voltage of the pre-amplifier unit is output through the first node, and a non-inverted voltage of the pre-amplifier unit is output through the third node;
The first, second and fifth MOS transistors are implemented as N-type,
The third and fourth MOS transistors are implemented as P-type pixel sensing devices. According to claim 1,
The first gain amplification unit,
a sixth MOS transistor having a gate electrode connected to the third node, a drain electrode connected to a fourth node, and a source electrode connected to a fifth node;
a seventh MOS transistor having a gate electrode connected to the first node, a drain electrode connected to a sixth node, and a source electrode connected to the fifth node;
an eighth MOS transistor having a gate electrode connected to the sixth node, a source electrode connected to the high potential operating voltage source, and a drain electrode connected to the fourth node;
a ninth MOS transistor having a gate electrode and a drain electrode connected to the fourth node and a source electrode connected to the high-potential operating voltage source;
a tenth MOS transistor having a gate electrode connected to the fourth node, a source electrode connected to the high potential operating voltage source, and a drain electrode connected to the sixth node;
an eleventh MOS transistor having a gate electrode and a drain electrode connected to the sixth node and a source electrode connected to the high-potential operating voltage source;
A pixel sensing device including a twelfth MOS transistor having a gate electrode connected to the bias voltage source, a drain electrode connected to the fifth node, and a source electrode connected to the low potential operating voltage source. According to claim 5,
The sixth, seventh, and twelfth MOS transistors are implemented as N-type,
The eighth, ninth, tenth, and eleventh MOS transistors are implemented as P-type pixel sensing devices. According to claim 5,
The second gain amplification unit,
a thirteenth MOS transistor having a gate electrode connected to the sixth node, a source electrode connected to the high potential operating voltage source, and a drain electrode connected to the output terminal; and
A pixel sensing device including a 14th MOS transistor having a gate electrode connected to the bias voltage source, a drain electrode connected to the output terminal, and a source electrode connected to the low potential operating voltage source. According to claim 1,
The input impedance of the operational amplifier is proportional to the output gain of the amplifier and inversely proportional to the input gain of the amplifier. According to claim 1,
Each of the current integrators,
Sensing the pixel current flowing through the driving TFT of each pixel in response to the sensing data voltage and sensing the total amount of charge accumulated in the capacitors of each pixel in response to the sensing data voltage;
The capacitors include a storage capacitor and a parasitic capacitor connected to the gate electrode of the driving TFT. a display panel having a plurality of pixels and sensing lines and data lines connected to the pixels;
a data driving circuit supplying data voltages for sensing to the data lines;
The pixel sensing device according to any one of claims 1 and 4 to 9, which senses a pixel current flowing in each pixel in response to the sensing data voltage through the sensing lines and senses a total charge accumulated in capacitors of each pixel in response to the sensing data voltage through the data lines; and
and a timing controller compensating for digital image data to be written on the display panel based on a sensing result of the pixel sensing device. According to claim 10,
wherein the capacitors include a storage capacitor connected to a gate electrode of a driving TFT included in each pixel and a parasitic capacitor. According to claim 11,
a switch for supplying data connected between an output terminal of the data voltage for sensing of the data driving circuit and each data line;
a switch for supplying a reference voltage connected between an output terminal of the reference voltage of the data driving circuit and each sensing line;
a switch for a first sensing pass connected between an inverting input terminal of an op amp included in the pixel sensing device and each sensing line; and
The organic light emitting display device further includes a switch for a second sensing path connected between the inverting input terminal of the op amp included in the pixel sensing device and each of the data lines. According to claim 12,
While the pixel sensing device senses the pixel current of each pixel, the data supply switch and the first sensing pass switch maintain an on state, and the reference voltage supply switch and the second sensing pass switch maintain an off state,
While the pixel sensing device senses the total amount of charge accumulated in the capacitors of each pixel, the switch for supplying the reference voltage and the switch for the second sensing pass maintain an on state, and the switch for supplying data and the switch for the first sensing pass maintain an off state. According to claim 10,
The timing controller,
Calculate a first compensation parameter corresponding to a first sensing result of the pixel sensing device for the pixel current, and first compensate the digital image data to be written in the display panel based on the first compensation parameter;
An organic light emitting display device that calculates a second compensation parameter corresponding to a second sensing result of the pixel sensing device for the total amount of charge, and performs secondary compensation for the digital image data to be written on the display panel based on the second compensation parameter. a number of pixels; a pixel sensing device according to any one of claims 1 and 4 to 9, connected to the pixels through sensing lines and data lines; a data driving circuit supplying data voltages for sensing to the data lines; and a timing controller for compensating digital image data to be written in the pixels based on a sensing result of the pixel sensing device.
sensing, by the pixel sensing device, a pixel current flowing in each pixel corresponding to the sensing data voltage through the sensing lines;
calculating a first compensation parameter corresponding to a first sensing result of the pixel current by the pixel sensing device in the timing controller, and firstly compensating the digital image data in the timing controller based on the first compensation parameter;
sensing a total amount of charge accumulated in capacitors of each pixel in response to the sensing data voltage through the data lines in the pixel sensing device; and
Calculating a second compensation parameter corresponding to a second sensing result of the pixel sensing device for the total amount of charge in the timing controller, and performing secondary compensation on the digital image data in the timing controller based on the second compensation parameter. According to claim 15,
wherein the capacitors include a storage capacitor connected to a gate electrode of a driving TFT included in each pixel and a parasitic capacitor.