KR102542132B1 - Array substrate for In-Plane switching mode liquid crystal display device - Google Patents

Abstract

The present invention relates to a transverse electric field type liquid crystal display device, and more particularly, to an array substrate for a transverse electric field type liquid crystal display device capable of reducing distortion of a common voltage.
A feature of the present invention is that the display area is divided into first to sixth areas from the non-display area toward the center, and the first to third pixel areas located in the first to third areas are connected to the common wiring and the first auxiliary The number of first common contact holes contacted by the common wiring is adjusted, and the fourth to sixth pixel regions located in the fourth to sixth regions further include a second auxiliary common wiring, and the number of the second auxiliary common wiring is adjusted. It is characterized in that the common electrode part has a low line resistance as it goes from the first region to the sixth region.
Through this, it is possible to prevent vertical and horizontal luminance differences, flicker, and afterimages from occurring due to in-plane deviation of the common voltage. In addition, it is possible to prevent an increase in the load of the common electrode portion in the center, so that the deterioration of image quality due to crosstalk can be prevented.

Description

Array substrate for In-Plane switching mode liquid crystal display device}

The present invention relates to a transverse electric field type liquid crystal display device, and more particularly, to an array substrate for a transverse electric field type liquid crystal display device capable of reducing distortion of a common voltage.

The liquid crystal display device (LCD), which is advantageous for displaying moving images and has a large contrast ratio, is actively used in TVs and monitors. It shows the principle of image realization by .

Such a liquid crystal display device has as an essential component a liquid crystal panel bonded by interposing a liquid crystal layer between two parallel substrates, and realizes a difference in transmittance by changing the arrangement direction of liquid crystal molecules with an electric field in the liquid crystal panel. do.

Recently, an active matrix liquid crystal display that drives liquid crystals with an electric field formed from up and down has been widely used because of its excellent resolution and ability to realize moving pictures.

Accordingly, various methods have been proposed to overcome the shortcoming of a narrow viewing angle, and among them, a liquid crystal driving method using a transverse electric field is attracting attention.

1 is a cross-sectional view schematically illustrating a liquid crystal panel of a general horizontal field type liquid crystal display device, and FIG. 2 is a schematic diagram showing that a ripple is generated due to line resistance of a common voltage of a general horizontal field type liquid crystal display device.

As shown, the lower substrate 1, which is an array substrate, and the upper substrate 3, which is a color filter substrate, are spaced apart from each other and face each other, and a liquid crystal layer 5 is interposed between the upper and lower substrates 1 and 3. has been

On the lower substrate 1, the common electrode 25 and the pixel electrode 23 are formed on the same plane, and the liquid crystal layer 5 generates a horizontal electric field (L) by the common electrode 25 and the pixel electrode 23. is operated by

As such, the horizontal electric field liquid crystal display device forms a common electrode 25 and a pixel electrode 23 on the lower substrate 1, and generates a horizontal electric field L between the two electrodes 23 and 25 so that the liquid crystal molecules By arranging them in parallel with the horizontal electric field L parallel to the substrates 1 and 3, the viewing angle of the liquid crystal display can be widened.

Meanwhile, since the line resistance of the common electrode 25 increases from the upper, lower and left and right regions of the panel toward the center of the panel, in-plane deviation of the common voltage Vcom is caused. Such in-plane deviation of the common voltage Vcom causes vertical and horizontal luminance differences, flicker, and afterimages.

In particular, as the line resistance of the common electrode 25 increases at the center, the load of the common voltage Vcom at the center of the panel increases. It is defined as an RC delay defined as a product of a line resistance and a parasitic capacitance, and when the RC delay is high, image quality deterioration due to crosstalk is caused.

Therefore, in order to reduce the RC delay, the line resistance of the common electrode 25 should be reduced, but the current structure of the common electrode 25 has limitations in reducing the line resistance.

As a result, the common voltage Vcom is not maintained at a constant value, but fluctuates due to the influence of the scan pulse SP or the data voltage Vdate as shown in FIG. 2 . This ripple phenomenon of the common voltage Vcom becomes a main factor inducing horizontal crosstalk when a specific data voltage Vdate is applied.

SUMMARY OF THE INVENTION The present invention is to solve the above problems, and a first object thereof is to minimize occurrence of in-plane deviation of a common voltage.

In addition, the second object is to reduce the line resistance of the common electrode in the central region of the panel, and through this, distortion of the common voltage is prevented and to provide a horizontal electric field type liquid crystal display device with excellent display quality. for the third purpose.

A fourth object is to shield an electric field generated between the data wiring and the pixel electrode.

In order to achieve the object as described above, the present invention provides a non-display area and a display area located inside the non-display area and defined by dividing the first to sixth areas sequentially from the non-display area toward the center. a substrate including a substrate, a first pixel region located in the first region and connected to a common wire and a common electrode in one of three pixel regions adjacent to each other through a first common contact hole; Located in Area 2, a common wire and a common electrode in two pixel areas among three pixel areas adjacent to each other are located in a second pixel area and a third area connected through a first common contact hole, respectively. In each of the three pixel areas, the common wire and common electrode are located in the third pixel area and the fourth area, which are connected through the first common contact hole, and are located in the three pixel areas adjacent to each other. In each of the three pixel areas, a common wire and a common electrode are connected through a first common contact hole, and are located in a fourth pixel area including a single vertical line common voltage pass structure and a fifth area, and adjacent to each other. In each of the three pixel areas, a common wire and a common electrode are connected through a first common contact hole, and are located in a fifth pixel area including a common voltage path structure of two vertical lines, and a common electrode in the sixth area. and a sixth pixel area including a common wiring and a common electrode connected to each other through a first common contact hole in three pixel areas among three pixel areas adjacent to each other and including a common voltage path structure of three vertical lines; , Provided is an array substrate for a transverse electric field type liquid crystal display device in which the line resistance of the common electrode part decreases from the first region to the sixth region.

As described above, according to the present invention, the display area is defined by being divided into first to sixth areas from the non-display area toward the center, and the first to third pixel areas located in the first to third areas have a common The number of first common contact holes through which the wiring and the first auxiliary common wiring are in contact is adjusted, and the fourth to sixth pixel regions located in the fourth to sixth regions further include a second auxiliary common wiring, By adjusting the number of common wires so that the common electrode portion has a lower line resistance from the first area to the sixth area, vertical and horizontal luminance differences, flicker, and afterimages occur due to in-plane deviation of the common voltage. There is a preventive effect.

In addition, it is possible to prevent an increase in the load of the common electrode portion in the center, so that there is an effect of preventing image quality deterioration due to crosstalk.

In particular, the 4th to 6th pixel areas located in the 4th to 6th areas corresponding to the center of the panel implement a common voltage pass structure of a vertical line through the second auxiliary common wiring, thereby forming a horizontal line at the center of the panel. There is an effect of preventing non-uniformity between the common voltage path structure of the vertical line and the common voltage path structure of the vertical line.

Through this, it is possible to further prevent an increase in the load of the common electrode portion in the vertical line, and thus, there is an effect of preventing deterioration in image quality due to crosstalk.

1 is a cross-sectional view schematically illustrating a liquid crystal panel of a general horizontal field type liquid crystal display device.
2 is a schematic diagram showing that ripple is generated due to line resistance of a common voltage of a general transversal field type liquid crystal display;
3 is a plan view schematically illustrating a horizontal electric field type liquid crystal display according to an embodiment of the present invention;
4A to 4F are plan views schematically illustrating an array substrate for a transverse electric field type liquid crystal display device according to an embodiment of the present invention.
Figure 5a is a cross-sectional view taken along the line I-I of Figure 4a.
Figure 5b is a cross-sectional view taken along the line II-II of Figure 4f.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

3 is a plan view schematically illustrating a horizontal electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

As shown, the horizontal field type liquid crystal display device 10 according to an embodiment of the present invention includes an array substrate 111 and a color filter substrate 112 with a liquid crystal layer (not shown) interposed therebetween. This face-to-face bonding liquid crystal panel 110 is an essential element.

At this time, the first substrate 111, called a lower substrate or an array substrate, includes a display area AA displaying an image and a non-display area NA where various circuits and wires are formed and are not used for displaying an image. do.

At this time, the non-display area NA is defined along the edge of the first substrate 111, and the display area AA is located inside the non-display area NA.

In the display area AA of the first substrate 111, a plurality of data lines 105 and a gate line 103 cross vertically and horizontally to define m×n pixel areas SP, and these two lines 103, 105) is provided with a thin film transistor (T) as a switching element.

In addition, a common wiring 107 (see FIG. 4A ) is formed passing through each pixel region SP and spaced apart from the gate wiring 103 .

At this time, it includes a common wire connection wire (125a, see FIG. 4a) receiving a common voltage from the common wire (107, see FIG. 4a), and is also connected to the common wire connection wire (125a, see FIG. 4a) and data wire ( 105) and parallel first and second auxiliary common wires 125b and 200 (see FIGS. 4A and 4D).

Here, the common wiring 107 (see FIG. 4A), the common wiring connection wiring 125a (see FIG. 4A), and the first auxiliary common wiring 125b (see FIG. 4A) form a mesh structure.

And inside each pixel region SP, a plurality of central common electrodes (125, see FIG. 4a) branched off from the common wiring connection wiring (125a, see FIG. 4a) and parallel to the first auxiliary common wiring (125b, see FIG. 4a). They are formed at regular intervals.

In addition, inside each pixel region SP, an auxiliary pixel wiring 123a (see FIG. 4A) connected to the thin film transistor T is formed parallel to a common wiring 107 (see FIG. 4A), and the auxiliary pixel wiring 123a , FIG. 4A), a plurality of pixel electrodes 125 (see FIG. 4A) are formed.

At this time, in the non-display area NA on one side of the first substrate 111 on which the gate wiring 103 and the data wiring 105 are disposed, a gate pad (not shown) is connected to the gate wiring 103 and the data wiring 105, respectively. ) and data pads (not shown) are formed, and the gate line 103 and the data line 105 are connected to an external printed circuit board (not shown).

The second substrate 112 facing the first substrate 111 and the liquid crystal layer (not shown) is called an upper substrate or a color filter substrate, and one side thereof has a first substrate 111 A lattice-shaped black matrix (not shown) is configured to cover non-display elements such as the data wiring 105, the gate wiring 103, and the thin film transistor T of ).

In addition, R (red), G (green), and B (blue) color filters (not shown) that are sequentially and repeatedly arranged to correspond to each pixel area SP are provided inside the lattice.

And, at the boundary between the two substrates 111 and 112 and the liquid crystal layer (not shown), first and second alignment films (not shown) that determine the initial molecular alignment direction of the liquid crystal are interposed, and the liquid crystal layer filled therebetween ( Seal patterns 102 are formed along the edges of both substrates 111 and 112 to prevent leakage of (not shown).

Also, first and second polarizers (not shown) that selectively transmit only specific light are attached to each outer surface of the liquid crystal panel 110 .

In addition, a backlight (not shown) is provided to supply light from the rear surface of the liquid crystal panel 110 so that the difference in transmittance indicated by the liquid crystal panel 110 is expressed to the outside.

Here, in the horizontal electric field type liquid crystal display device 100 according to an embodiment of the present invention, the display area AA has six areas A and B from the non-display area NA surrounding the edge of the display area AA toward the center. , C, D, E, F) characterized in that it is divided into definitions.

That is, the first to sixth areas A, B, C, D, E, and F are defined sequentially from the area closest to the non-display area NA toward the center, and each area A, B, C , D, E, and F) have common electrode portions having different line resistances.

Here, the common electrode unit includes a common wire (107, see FIG. 4a), a common wire connection wire (125a, see FIG. 4a), first and second auxiliary common wires (125b, 200, see FIGS. 4a and 4d), and a common electrode ( 125, see FIG. 4A), and the common electrode formed in the plurality of pixel areas SP located in the first area A most adjacent to the non-display area NA has a first line resistance. And, the common electrode portion formed in the plurality of pixel areas SP located in the second area B has a lower second line resistance than the first line resistance.

In addition, the common electrode portion formed in each pixel region SP from the third region C to the sixth region F is formed to have a low line resistance.

Through this, the horizontal electric field liquid crystal display device 100 according to an embodiment of the present invention can prevent vertical and horizontal luminance differences, flicker, and afterimages from occurring due to in-plane deviation of the common voltage. In addition, it is possible to prevent an increase in the load of the common electrode 125 (see FIG. 4A) at the center, and thus, it is possible to prevent deterioration in image quality due to crosstalk.

Looking more closely at this, in general, the line resistance of the common electrode (125, see FIG. 4A) increases from the upper, lower and left and right regions of the panel toward the center of the panel. In (100), by forming the common electrode portion to have a lower line resistance as it moves from the edge toward the center, occurrence of in-plane deviation of the common voltage can be prevented.

In this way, as the occurrence of in-plane deviation of the common voltage is prevented, it is possible to prevent vertical and horizontal luminance differences, flicker, and afterimages from occurring.

In addition, by forming the common electrode portion in the center of the panel to have a lower line resistance than other areas, it is possible to prevent an increase in the load of the common electrode portion in the center portion, resulting in deterioration in image quality due to crosstalk. can prevent doing so.

This will be examined in more detail with reference to FIGS. 4a to 4f and FIGS. 5a to 5b.

4A to 4F are plan views schematically showing an array substrate for a transverse field type liquid crystal display according to an embodiment of the present invention, and FIG. 5A is a cross-sectional view taken along the line I-I of FIG. 4A, and FIG. 5B is a It is a cross-sectional view cut along the cutting line II-II of 4f.

Here, FIG. 4A is a plan view schematically showing a first pixel area located in the first area A of FIG. 3, and FIG. 4B is a plan view schematically showing a second pixel area located in the second area B of FIG. FIG. 4C is a plan view schematically illustrating the third pixel area located in the third area (C) of FIG. 3, and FIG. 4D is a plan view showing the fourth area (E) in FIG. 3. FIG. 4E is a plan view schematically showing a pixel area, FIG. 4E is a plan view schematically showing a fifth pixel area located in the fifth area F of FIG. 3 , and FIG. 6 is a plan view schematically showing the pixel area G.

Meanwhile, in order to avoid redundant description, the same reference numerals will be assigned to the same parts that play the same role in FIGS. 4a to 4f and FIGS. 5a to 5b and will be described together.

And, for convenience of description, the portion where the thin film transistor T is to be formed in each of the pixel areas SP1, SP2, SP3, SP4, SP5, and SP6 is defined as a switching area TrA, and is located in the first area A. A pixel area located in the second area (B) is defined as a first pixel area (SP1), a pixel area located in the second area (B) is a second pixel area (SP2), and a pixel area located in the third area (C) is a third pixel area. The pixel area located in the area SP3 and the fourth area D is the fourth pixel area SP4, and the pixel area located in the fifth area E is the fifth pixel area SP5 and the sixth area F ) will be defined as a sixth pixel area SP6.

Also, three adjacent pixel areas SP1, SP2, SP3, SP4, SP5, and SP6 will be defined as one pixel P.

As shown, the array substrate 101 for a horizontal electric field liquid crystal display device according to an embodiment of the present invention crosses each other at the lower and upper portions with the gate insulating film 113 interposed therebetween, so that each pixel area SP1, SP2, SP3 , SP4, SP5, and SP6) are formed with a plurality of gate wires 103 and data wires 105.

In addition, a common wiring 107 is formed passing through each of the pixel regions SP1 , SP2 , SP3 , SP4 , SP5 , and SP6 and spaced apart from the gate wiring 103 .

Here, the gate wiring 103 and the common wiring 107 extend along a first direction, and the data wiring 105 extends along a second direction crossing the first direction.

In addition, each pixel region (SP1, SP2, SP3, SP4, SP5, SP6) is connected to a gate wire 103 and a data wire 105, and a gate electrode 111, a gate insulating film 113, and pure amorphous A semiconductor layer 115 composed of an active layer 115a of silicon and an ohmic contact layer 115b of impurity amorphous silicon, and a thin film transistor T composed of source and drain electrodes 117 and 118 spaced apart from each other are formed. .

At this time, in the drawing, the thin film transistor (T) shows as an example that the region constituting the channel forms a 'U' shape, but it can be transformed into various shapes.

Here, a common wiring connection wiring 125a connected to the common wiring 107 to receive a common voltage is formed inside each of the pixel regions SP1, SP2, SP3, SP4, SP5, and SP6, and the common wiring connection wiring ( 125a) and a first auxiliary common wire 125b parallel to the data wire 105 is formed.

Further, inside each pixel region (SP1, SP2, SP3, SP4, SP5, SP6), a plurality of common electrodes 125 branched from the common wiring connection wiring 125a and parallel to the first auxiliary common wiring 125b are constant. It is formed at intervals.

The common wiring connection wiring 125a extends along the first direction, and the first auxiliary common wiring 125b extends along the second direction, so that the common wiring 107 and the common wiring connection wiring 125a and the first auxiliary common wiring 125a The common wiring 125b has a mesh structure.

In addition, an auxiliary pixel wiring 123a connected to the drain electrode 118 of the thin film transistor T through the drain contact hole 118a is common in each of the pixel regions SP1, SP2, SP3, SP4, SP5, and SP6. A plurality of pixel electrodes 123 are formed parallel to the wiring 107 and branched from the auxiliary pixel wiring 123a.

The common electrode 125 and the pixel electrode 123 extend along the second direction and are spaced apart from each other and are alternately disposed.

Here, the common electrode 125, the first auxiliary common wire 125b, and the pixel electrode 123 formed in each pixel area SP1, SP2, SP3, SP4, SP5, and SP6 are formed in each pixel area SP1, SP2, SP3. , SP4, SP5, and SP6), when a virtual line CL is drawn parallel to the gate wiring 103, it has a structure symmetrically bent with respect to the virtual line CL.

That is, based on the imaginary line CL, each common electrode 125, the first auxiliary common wiring 125b, and the pixel electrode 123 rotate clockwise or counterclockwise from a direction perpendicular to the imaginary line CL. It is a structure bent at a certain angle in the direction.

Accordingly, the upper and lower portions of each pixel area SP1, SP2, SP3, SP4, SP5, and SP6 are directed toward the common electrode 125, the first auxiliary common wire 125b, and the pixel electrode 123 based on the central portion. By changing the , different domain areas are formed.

In this case, in the horizontal electric field type liquid crystal display (100 in FIG. 3), the movement of liquid crystals located in different domains within one pixel area (SP1, SP2, SP3, SP4, SP5, SP6) is different, and finally the liquid crystal molecules By changing the arrangement of the major axis of , the color shift phenomenon in a specific azimuth angle is reduced.

That is, for convenience of explanation, the area formed on the upper part with respect to the virtual line CL in each pixel area SP1, SP2, SP3, SP4, SP5, and SP6 is referred to as the first domain area D1, and the area formed on the lower part If the area is defined as the second domain area D2, the azimuth angle at which color shift occurs in the first domain area D1 and the azimuth angle at which color shift occurs in the second domain area D2 are different, so that each domain As the regions D1 and D2 compensate for the color shift phenomenon, the color shift phenomenon can be finally reduced.

In this case, the predetermined angle may be 7 degrees to 10 degrees, and the common electrode 125, the first auxiliary common wire 125b, and the pixel electrode 123 may be ± 7 degrees to a direction perpendicular to the imaginary line CL. If the structure is bent at an angle greater than ± 10 degrees, more reliable domain separation is possible within one pixel area (SP1, SP2, SP3, SP4, SP5, SP6), but the driving voltage is higher and the overall white luminance due to the characteristics of the V-T curve Since is reduced, the common electrode 125, the first auxiliary common wire 125b, and the pixel electrode 123 have an angle of about ±7 degrees to ±10 degrees with respect to the direction perpendicular to the imaginary line CL. It is preferable to have a folded structure.

Here, by having the common electrode 125, the first auxiliary common wire 125b, and the pixel electrode 123 bent, the data wire 105 also has each pixel area SP1, SP2, SP3, SP4, SP5, SP6 ), and the data wiring 105 is not separately formed for each pixel area (SP1, SP2, SP3, SP4, SP5, SP6), but the entire display area (AA in FIG. 3) Since it has a configuration connected to , the data line 105 forms a zigzag shape bent with respect to the center of each pixel area (SP1, SP2, SP3, SP4, SP5, SP6) in the display area (AA in FIG. 3). .

Here, the gate wiring 103, the gate electrode 111, and the common wiring 107 are all made of the same material on the same layer, such as aluminum (Al), molybdenum (Mo), nickel (Ni), or chromium (Cr). , copper (Cu) or an alloy thereof, and may have a single-layer or multi-layer structure.

At this time, it is preferable to form the gate wiring 103, the gate electrode 111, and the common wiring 107 with copper (Cu) or a copper alloy (Cu alloy). It has a low resistance value compared to transparent conductive materials such as indium-tin-oxide, and has relatively good low-resistance characteristics compared to molybdenum (Mo) or aluminum (Al).

In addition, the source and drain electrodes 117 and 118 and the data wiring 105 are located on the same layer with the gate wiring 103, the gate electrode 111, the common wiring 107 and the gate insulating film 113 interposed therebetween. It is made of the same material, but may be made of aluminum (Al), molybdenum (Mo), nickel (Ni), chromium (Cr), copper (Cu), or alloys thereof, and may have a single-layer or multi-layer structure. .

At this time, the source and drain electrodes 117 and 118 and the data wire 105 are also preferably formed of copper (Cu) or a copper alloy (Cu alloy).

Also, the common electrode 125 and the pixel electrode 123 may be formed of a transparent conductive material such as indium tin oxide or indium zinc oxide.

In addition, the auxiliary pixel wiring 123a, the common wiring connection wiring 125a, and the first auxiliary common wiring 125b are formed of the same material on the same layer as the pixel electrode 123 and the common electrode 125.

Here, the common electrode 125, the pixel electrode 123, the auxiliary pixel wiring 123a, the common wiring connection wiring 125a, and the first auxiliary common wiring 125b are the source and drain electrodes 117 and 118 and the data wiring Drain contact hole ( It comes into contact with the drain electrode 118 through 118a).

Also, the common electrode 125 is provided in the protective layer 121 through the first auxiliary common wire 125b and connects to the common wire 107 through the first common contact hole 107a exposing the common wire 107. come into contact

Here, as shown in FIG. 4A, the first area (FIG. 3) of the display area (AA in FIG. 3) located closest to the non-display area (NA in FIG. 3) defined along the edge of the substrate 101. The first pixel region SP1 positioned at A) of A) includes a first auxiliary common wire 125b formed in one of the three first pixel regions SP1 adjacent to each other in a horizontal line. It contacts the common wire 107 through the first common contact hole 107a and receives a common voltage.

And as shown in FIG. 4B, the second pixel area SP2 located in the second area (B in FIG. 3) located inside the first area (A in FIG. The first auxiliary common wires 125b formed in the two second pixel regions SP2 among the two second pixel regions SP2 contact the common wires 107 through the first common contact holes 107a, respectively, and thereby generate a common voltage. is applied, and as shown in FIG. 4C, the third pixel area SP3 located in the third area (C in FIG. 3) located inside the second area (B in FIG. 3) is adjacent to each other in a horizontal line. The first auxiliary common wires 125b formed in the three third pixel regions SP3 of the three third pixel regions SP3 contact the common wires 107 through the first common contact holes 107a, respectively. A common voltage is applied.

Accordingly, the pixel areas SP1, SP2, and SP3 located in the first to third areas (A, B, and C in FIG. 3) shown in FIGS. 4A to 4C have different common electrode line resistances. In particular, the line resistance of the common electrode part decreases from the first area (A in FIG. 3) to the third area (C in FIG. 3).

Here, the common electrode unit includes a common wire 107 , a common wire connecting wire 125a , first and second auxiliary common wires 125b and 200 , and a common electrode 125 .

Looking at this in more detail, the first pixel region SP1 located in the first region (A in FIG. 3) is the first pixel region SP1 formed in one of the three adjacent first pixel regions SP1. Since only 1 auxiliary common wire 125b comes into contact with the common wire 107 through the first common contact hole 107a, one pixel P defined by three first pixel regions SP1 has one 1 comes into contact with the common wire 107 through the common contact hole 107a.

Also, a second region (B in FIG. 3 ) in which the first auxiliary common wire 125b of each of the two second pixel regions SP2 among the three adjacent second pixel regions SP2 contacts the common wire 107. As one pixel P located in ) comes into contact with the common wire 107 through the two first common contact holes 107a, the pixel P located in the second area (B in FIG. 3) applies a larger amount of common voltage as the contact between the first auxiliary common wire 125b and the common wire 107 is further increased than that of the pixel P located in the first region (A in FIG. 3). You will receive.

Therefore, the line resistance of the common electrode part of the second pixel regions SP2 located in the second region (B of FIG. 3) is higher than that of the first pixel regions SP1 located in the first region (A of FIG. 3). it gets lower

In addition, the third pixel regions SP3 located in the third region (C in FIG. 3 ) include first auxiliary elements provided in three third pixel regions SP3 among three third pixel regions SP3 adjacent to each other. As the common wires 125b come into contact with the common wires 107, the pixels P located in the third area (C in FIG. 3) are connected to the common wires 107 through the three first common contact holes 107a. ) come into contact with

Therefore, the third pixel regions SP3 positioned in the third region (C in FIG. 3 ) have a higher amount of common voltage than the second pixel regions SP2 located in the second region (B in FIG. 3 ). is applied, the third pixel areas SP3 located in the third area (C in FIG. 3) are the first and second pixel areas (SP3 located in the first and second areas (A and B in FIG. 3)). Compared to SP1 and SP2), the line resistance of the common electrode part is less.

Here, if the line resistance of the common electrode of the first pixel regions SP1 located in the first region (A in FIG. 3) is defined as 100, the second pixel region ( SP2) has a common electrode line resistance of 80, and the third pixel regions SP3 located in the third region (FIG. 3C) have a common electrode line resistance of 60 lower than 80. .

At this time, since the first common contact hole 107a for connecting the first auxiliary common wire 125b and the common wire 107 is positioned above the common wire 107, it does not contribute to the lowering of the aperture ratio, and thus the lowering of the aperture ratio. Even without it, means for applying a common voltage to the common electrode 125 are increased.

That is, the horizontal electric field type liquid crystal display device ( 100 in FIG. 3 ) according to the embodiment of the present invention can lower the line resistance of the common electrode without reducing the aperture ratio.

And, as shown in FIGS. 4D to 4F, in the array substrate 101 for a transversal electric field type liquid crystal display device according to an embodiment of the present invention, in the fourth to sixth regions (D, E, and F in FIG. 3) The fourth to sixth pixel areas SP4, SP5, and SP6 are located in three fourth to sixth pixel areas SP4, SP5, and SP6 among three adjacent fourth to sixth pixel areas SP4, SP5, and SP6. As the first auxiliary common wiring 125b provided in SP5 and SP6 respectively contacts the common wiring 107, the pixels P located in the fourth to sixth regions (D, E, and F in FIG. 3) ) comes into contact with the common wire 107 through three first common contact holes 107a, respectively.

In addition, as shown in FIG. 4D, the fourth pixel areas SP4 positioned in the fourth area (D in FIG. 3) are one fourth pixel area among three fourth pixel areas SP4 adjacent to each other in a horizontal line. It is characterized in that the second auxiliary common wire 200 is further formed in the region SP4.

And, as shown in FIG. 4E, the fifth pixel areas SP5 located in the fifth area (E in FIG. 3) located inside the fourth area (D in FIG. 3) are adjacent to each other in a horizontal line. A second auxiliary common wire 200 is further provided in each of the two fifth pixel regions SP5 among the five fifth pixel regions SP5, and as shown in FIG. 4F, the sixth region (F in FIG. 3) The positioned sixth pixel regions SP6 further indicate that the second auxiliary common wire 200 is further provided in each of three sixth pixel regions SP6 among the three sixth pixel regions SP6 adjacent to each other in a horizontal line. to be characterized

The fourth to sixth pixel areas SP4, SP5, and SP6 located in the fourth to sixth areas (D, E, and F in FIG. 3) shown in FIGS. 4D to 4F are the first to third areas. The line resistance of the common electrode is lower than that of the first to third pixel regions SP1, SP2, and SP3 located in (A, B, and C of FIG. 3), especially from the fourth region (D of FIG. 3). The line resistance of the common electrode part decreases toward the sixth region (F in FIG. 3).

Looking at this in more detail, the first to third pixel areas SP1, SP2, and SP3 located in the first to third areas (A, B, and C in FIG. 3) shown in FIGS. 4A to 4C have a common inside. First and second outermost common wires 125c and 125d connected to the wire 107 and parallel to the data wire 105 are formed. The first and second outermost common wires 125c and 125d are They are positioned parallel to each other on the left and right sides of the first to third pixel regions SP1, SP2, and SP3, and the data lines 105 are common to the first outermost of the first to third pixel regions SP1, SP2, and SP3. It is positioned between the wiring 125c and the second outermost common wiring 125d of an adjacent pixel area.

Here, the first to third pixel regions SP1, SP2, and SP3 located in the first to third regions (A, B, and C of Fig. 3) of the present invention shown in Figs. The first and second outermost common wires 125c and 125d both branch from the common wire 107 and are made of the same material on the same layer as the common wire 107 .

The first and second outermost common wirings 125c and 125d are provided for repair of the data wiring 105 when the data wiring 105 is disconnected, and also around the data wiring 105. It plays a role in preventing light leakage from occurring.

At this time, the first to sixth pixel regions SP4, SP5, and SP6 located in the fourth to sixth regions (D, E, and F in Fig. 3) of the present invention shown in Figs. The second outermost common wire 125d located inside each of the first to third pixel regions SP1, SP2, and SP3 located in the third region (A, B, and C in FIG. 3) is omitted, and the second outermost common wiring 125d is omitted. 2 auxiliary common wiring 200 is located.

That is, the fourth to sixth pixel regions SP4, SP5, and SP6 located in the fourth to sixth regions (D, E, and F in FIG. 3) are internally connected to the common wire 107 and the data wire 105 ) is located on the left side of each of the fourth to sixth pixel regions SP4, SP5, and SP6, and the first outermost common wiring 125c parallel to A second auxiliary common wire 200 connected to the common wire 107 and parallel to the data wire 105 is positioned on the right side of the , and the data wire 105 is connected to each of the fourth to sixth pixel areas SP4 and SP5. , SP6) is located between the outermost first common wire 125c and the second auxiliary common wire 200 of an adjacent pixel area.

The second auxiliary common wire 200 positioned in the fourth to sixth pixel regions SP4, SP5, and SP6 located in the fourth to sixth regions (D, E, and F in FIG. 3) has source and drain electrodes. (117, 118) and data wiring 105 are made of the same material on the same layer, and in the vicinity where the common wiring 107 and the first auxiliary common wiring 125b are connected through the first common contact hole 107a. It is formed to have a wider width than other regions and includes a second common contact hole 200a corresponding to the first common contact hole 107a.

That is, the common electrode 125 located in each of the fourth to sixth pixel regions SP4, SP5, and SP6 located in the fourth to sixth regions (D, E, and F in FIG. 3) is a protective layer 121 The common wiring 107 exposed through the first common contact hole 107a provided in and the second common contact hole 200a provided in the second auxiliary common wiring 200 corresponding to the first common contact hole 107a. ) and the first auxiliary common wire 125b, the common voltage is applied from the common wire 107.

At this time, as the first auxiliary common wiring 125b contacts the second auxiliary common wiring 200 together with the common wiring 107, the line resistance of the common electrode part is reduced.

Here, the fourth pixel regions SP4 located in the fourth region (D in FIG. 3 ) share the second auxiliary common only within one fourth pixel region SP4 among three fourth pixel regions SP4 adjacent to each other. The fifth pixel regions SP5 provided with the wiring 200 and located in the fifth region (E in FIG. 3) are two fifth pixel regions SP5 among three fifth pixel regions SP5 adjacent to each other. As the second auxiliary common wire 200 is provided in the inside, the fifth pixel areas SP5 positioned in the fifth area (E in FIG. 3 ) are located in the fourth area (D in FIG. 3 ). The line resistance of the common voltage part is lower than that of the pixel regions SP4.

Also, the sixth pixel regions SP6 located in the sixth region (F in FIG. 3 ) have a second auxiliary common area within three sixth pixel regions SP6 among three sixth pixel regions SP6 adjacent to each other. As the wiring 200 is provided, the sixth pixel areas SP6 located in the sixth area (F in FIG. 3 ) are located in the fourth and fifth areas (D and E in FIG. 3 ). The line resistance of the common voltage part is lower than that of the 5 pixel regions SP4 and SP5, and the line resistance of the common voltage part is lower than that of the fifth pixel regions SP5 located in the fifth region (E in FIG. 3). will have

At this time, the line resistance of the common electrode part of the fourth to sixth pixel regions SP4, SP5, and SP6 located in the fourth to sixth regions (D, E, and F in FIG. 3) is Since the line resistance of the common electrode part is lower than that of the first to third pixel regions SP1, SP2, and SP3 located in A, B, and C of 3), the first pixel region located in the first region (A in FIG. 3) The line resistance of the common electrode of the first pixel regions SP1 is 100, the line resistance of the common electrode of the second pixel regions SP2 located in the second region (B in FIG. 3) is 80, and the line resistance of the third region (Fig. If the line resistance of the common electrode of the third pixel regions SP3 located in C) is 60, the line resistance of the common electrode of the fourth pixel regions SP4 located in the fourth region (D of FIG. 3) is 40, The line resistance of the common electrode of the fifth pixel regions SP2 positioned in the fifth region (E in FIG. 3) is 20, and the line resistance of the common electrode of the sixth pixel regions located in the sixth region (F in FIG. 3) is 20. will have 0.

Therefore, the horizontal electric field type liquid crystal display (100 in FIG. 3) according to an embodiment of the present invention moves from the first area (A in FIG. 3) closest to the non-display area (NA in FIG. 3) to the center of the panel. The line resistance of the common electrode part decreases as it goes to region 6 (F in FIG. 3).

Through this, the horizontal electric field liquid crystal display (100 in FIG. 3 ) according to the embodiment of the present invention can prevent vertical and horizontal luminance differences, flicker, and afterimages from occurring due to in-plane deviation of the common voltage.

In addition, by further lowering the line resistance of the common electrode portion in the center portion, it is possible to prevent an increase in the load of the common electrode portion in the center portion, thereby preventing deterioration in image quality due to crosstalk.

Here, the second auxiliary common wire 200 provided in the fourth to sixth pixel regions SP4, SP5, and SP6 located in the fourth to sixth regions (D, E, and F in FIG. 3) is It is provided to replace the second outermost common wire 125d provided in the first to third pixel regions SP1, SP2, and SP3 located in the to third regions (A, B, and C in FIG. 3), The second common contact hole 200a for connecting the second auxiliary common wire 200, the first auxiliary common wire 125b, and the common wire 107 is located above the common wire 107, thereby reducing the aperture ratio. Therefore, means for applying the common voltage to the common electrode 125 is increased without reducing the aperture ratio.

That is, the horizontal electric field type liquid crystal display device ( 100 in FIG. 3 ) according to the embodiment of the present invention can lower the line resistance of the common electrode without reducing the aperture ratio.

In particular, the horizontal electric field type liquid crystal display (100 in FIG. 3) according to an embodiment of the present invention is located in the fourth to sixth regions (D, E, and F in FIG. 3) shown in FIGS. 4E to 4F. The second auxiliary common wiring 200 provided in the through sixth pixel regions SP4, SP5, and SP6 completes the common voltage path structure of the vertical line.

That is, the pixel regions SP4, SP5, and SP6 located in the fourth to sixth regions (D, E, and F in FIG. 3) have a common voltage path structure through the common wire 107 as a horizontal line. As a vertical line, a common voltage pass structure is formed through the second auxiliary common wire 200 .

Here, a transparent conductive material such as indium-tin-oxide has relatively higher resistance than a metal material such as copper (Cu) or a copper alloy, so a common voltage passes through the common wiring 107. Non-uniformity of the common voltage path of the vertical line having the common voltage path structure is generated through the common voltage path structure of the horizontal line having the structure and the first auxiliary common wire 125b.

That is, since the line resistance of the first auxiliary common wire 125b and the common electrode 125 made of a transparent conductive material of the vertical line is high, the vertical line generates a load of the common voltage.

In addition, as the common wiring 107 is made of copper (Cu) or copper alloy (Cu alloy), which has a low resistance value compared to transparent conductive materials and has a low resistance characteristic that is better than that of molybdenum (Mo) and aluminum (Al), , the non-uniformity between the common voltage path structure of the horizontal line and the common voltage path structure of the vertical line is larger.

In particular, the non-uniformity between the common voltage path structure of the horizontal line and the common voltage path structure of the vertical line occurs more clearly in the center of the panel where the load of the common voltage is most severe.

In order to prevent such non-uniformity of the common voltage path from occurring, in addition to the first auxiliary common pattern 125b and the common electrode 125 made of a transparent conductive material even in a vertical line, copper (Cu) or a copper alloy (Cu alloy) and It is preferable to form a common voltage path through the common wiring 107 made of the same metal material, but since the common wiring 107 is formed on the same layer as the gate wiring 103, the position where the gate wiring 103 is formed In the region corresponding to , the common wiring 107 is cut and formed.

That is, the common wiring 107 maintains a state in which they are all connected in a horizontal line, but maintains a state in which they are separated in a vertical line by the gate wiring 103 .

Here, the horizontal electric field liquid crystal display (100 in FIG. 3) according to an embodiment of the present invention has a pixel area (SP4) located in the fourth to sixth areas (D, E, and F in FIG. 3) corresponding to the center of the panel. , SP5, SP6) further form a second auxiliary common wiring 200 made of the same material on the same layer as the source and drain electrodes 117 and 118 and the data wiring 105, and the second auxiliary common wiring 200 By forming to be connected to the common wire 107, a common voltage path structure made of a metal material such as copper (Cu) or a copper alloy is formed by the second auxiliary common wire 200 even in a vertical line. do.

Through this, it is possible to prevent path unevenness of the common voltage of the vertical line and the horizontal line from occurring at the center of the panel, and through this, it is possible to further prevent the load of the common electrode unit from increasing in the vertical line. The deviation can be more drastically reduced, and the load of the common electrode part can be greatly reduced.

Accordingly, it is possible to prevent deterioration in image quality due to crosstalk caused by the load of the common electrode unit.

As described above, the horizontal electric field type liquid crystal display device (100 in FIG. 3) according to an embodiment of the present invention moves the display area (AA in FIG. 3) from the non-display area (NA in FIG. 3) toward the center in the first to third directions. 1st to 3rd pixel areas defined by being divided into 6 areas (A, B, C, D, E, F in FIG. 3) and located in the 1st to 3rd areas (A, B, C in FIG. 3) (SP1, SP2, and SP3) control the number of first common contact holes 107a through which the common wire 107 and the first auxiliary common wire 125b are in contact, and the fourth to sixth areas (see FIG. 3) The fourth to sixth pixel regions SP4, SP5, and SP6 located in D, E, and F further include second auxiliary common wires 200, and by adjusting the number of second auxiliary common wires 200, It is characterized in that the common electrode portion has a low line resistance as it goes from the first area (A in FIG. 3) to the sixth area (F in FIG. 3).

Through this, the horizontal electric field liquid crystal display (100 in FIG. 3 ) according to the embodiment of the present invention can prevent vertical and horizontal luminance differences, flicker, and afterimages from occurring due to in-plane deviation of the common voltage. In addition, it is possible to prevent an increase in the load of the common electrode portion in the center, so that the deterioration of image quality due to crosstalk can be prevented.

In particular, the fourth to sixth pixel regions SP4, SP5, and SP6 located in the fourth to sixth regions corresponding to the center of the panel (D, E, and F in FIG. 3) are connected to the second auxiliary common wiring 200. By embodying the common voltage path structure of the vertical line through , it is possible to prevent the occurrence of non-uniformity between the common voltage path structure of the horizontal line and the common voltage path structure of the vertical line at the center of the panel.

Through this, it is possible to further prevent an increase in the load of the common electrode part due to a vertical line, and thus, it is possible to prevent deterioration in image quality due to crosstalk.

The present invention is not limited to the above embodiments, and can be practiced with various changes without departing from the spirit of the present invention.

101: array substrate
103: gate wiring, 105: data wiring, 107: common wiring (107a: first common contact hole)
111: gate electrode, 117, 118: source and drain electrodes (118a: drain contact hole)
123: pixel electrode (123a: auxiliary pixel wiring)
125: common electrode (125a: common wiring connection wiring, 125b: first auxiliary common wiring, 125c, 125d: first and second outermost common wiring)
200: second auxiliary common wiring (200a: first common contact hole)

Claims (17)

a substrate including a non-display area and a display area positioned inside the non-display area;
a plurality of areas disposed in the display area, including pixels each including a plurality of pixel areas, and sequentially divided from the non-display area toward the center;
a light emitting element formed in each pixel region and including a common electrode;
a common wiring electrically connected to the common electrode through a first common contact hole;
It includes a first auxiliary common wire connected to the common wire, and the number of first common contact holes formed in the pixel increases from the area disposed outside the display area to the area disposed in the center. and
The first auxiliary common wire formed in the pixel increases in number from the area disposed outside the display area to the area disposed in the center of the display area.
According to claim 1,
The pixel area is defined by gate wires and data wires crossing each other with a gate insulating film interposed therebetween;
The common wiring is disposed parallel to and spaced apart from the gate wiring,
A horizontal electric field type liquid crystal display further comprising a common wiring connecting wire extending in the first direction and receiving a common voltage from the common wiring, and a second auxiliary common wiring connected to the common wiring connecting wiring and extending parallel to the data wiring. Array board for device.
According to claim 2,
The first auxiliary common wiring extends parallel to the data wiring on the same layer as the array substrate for a horizontal electric field type liquid crystal display device.
delete According to claim 3,
The first auxiliary common wiring is connected to the common wiring and the second auxiliary common wiring through a second common contact hole corresponding to the first common contact hole.
delete delete According to claim 2,
A protective layer is further positioned above the gate insulating film, and the first common contact hole is provided in the gate insulating film and the protective layer. According to claim 5,
A protective layer is further positioned above the gate insulating layer, the second common contact hole is provided in the gate insulating layer, the first auxiliary common wire, and the protective layer, and the second auxiliary common wire is connected to the first auxiliary common wire. and an array substrate for a transverse electric field type liquid crystal display connected to the common wiring.
According to claim 5,
The second common contact hole is positioned above the common wiring, and the array substrate for a horizontal electric field type liquid crystal display device.
According to claim 2,
Each pixel area includes a thin film transistor connected to the gate line and the data line,
An array substrate for a transverse electric field type liquid crystal display device in which a pixel electrode connected to the thin film transistor is positioned alternately with the common electrode. The method of claim 2, wherein the plurality of areas are composed of first to sixth areas from the outside to the inside of the display area,
An array substrate for a transverse field type liquid crystal display device, wherein the number of the first common contact holes increases from the first area to the third area.
According to claim 12,
In the first region, the first common contact hole is formed in one pixel region among three adjacent pixel regions of the pixel;
In the second region, the first common contact hole is formed in two pixel regions among three pixel regions adjacent to the pixel;
In the third region, the first common contact hole is formed in three adjacent pixel regions of the pixel.
The method of claim 12, wherein the first common auxiliary wiring,
The same number in the first area and the third area,
An array substrate for a transverse electric field type liquid crystal display device, the number of which increases from the fourth area to the sixth area.
According to claim 14,
In the fourth region, the first common auxiliary wire is formed in one pixel region among three adjacent pixel regions of the pixel;
In the fifth region, the first common auxiliary wiring is formed in two pixel regions among three adjacent pixel regions of the pixel;
In the third region, the first common auxiliary wire is formed in three adjacent pixel regions of the pixel.
According to claim 12,
In the first to third pixel regions respectively disposed in the first to third regions, first and second outermost common wirings diverging from the common wire and located at the outermost periphery of each pixel region parallel to the data wire. Including,
A first outermost common wire is positioned on one side of one pixel area among three fourth pixel areas disposed adjacent to each other disposed in the fourth area, and the first auxiliary common wire is positioned on the other side,
In two of the three fifth pixel areas disposed adjacent to each other disposed in the fifth area, a first outermost common wiring is positioned on one side and the first auxiliary common wiring is positioned on the other side, respectively;
A transversal field type liquid crystal in which a first outermost common wiring is positioned on one side and the first auxiliary common wiring is positioned on the other side in each of three pixel areas among the three sixth pixel areas disposed in the sixth area. Array substrate for display devices.
17. The method of claim 16,
The first and second outermost common wirings are made of the same material on the same layer as the gate wiring,
The first auxiliary common wiring is made of copper (Cu) or a copper alloy (Cu alloy).

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