KR102510439B1 - Power supply unit and display device including the same - Google Patents

Abstract

By controlling the operation of the sub power supply unit in the main power supply unit, a power supply device capable of stably performing shut-down control at the time of outputting voltages and when an abnormal operation occurs is provided. The power supply device includes a main power supply unit and a sub power supply unit that generate a plurality of operating voltages, and a control circuit that controls their operations.

Description

Power supply unit and display device including the same {Power supply unit and display device including the same}

The present invention relates to a power supply device, and particularly to a power supply device capable of controlling its operation when an external boost circuit is added for stable power supply in a large area display device and a display device including the same. it's about

Flat Panel Displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and laptop computers. Flat panel displays include Liquid Crystal Displays (LCDs), Plasma Display Panels (PDPs), Organic Light Emitting Displays (OLEDs), etc. Recently, electrophoretic displays ( EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among them, the liquid crystal display device displays an image using electrical and optical characteristics of liquid crystal. Liquid crystals have different anisotropic properties such as refractive index and permittivity depending on the long axis direction and the short axis direction of the molecules, and the molecular arrangement and optical properties can be easily controlled. A liquid crystal display using this displays an image by adjusting the transmittance of light passing through a polarizing plate by changing the arrangement direction of liquid crystal molecules according to the magnitude of the electric field.

Such a liquid crystal display device includes a liquid crystal panel, a backlight unit, and a power supply for supplying an operating voltage to them together with driving circuits.

The power supply is composed of one integrated circuit (IC), and as shown in FIG. 1, it generates and outputs a plurality of operating voltages, such as VCC, VDD, RST, VGH, and VGL, from the input voltage Vin. .

A plurality of operating voltages generated and output from the power supply are sequentially output in a predetermined order according to the control of the controller, and are output in the order of VCC, RST, VGL, VDD, and VGH.

In a typical liquid crystal display device, a single power supply device is provided, and a plurality of operating voltages are generated therefrom. However, in the case of generating a plurality of operating voltages using a single power supply in a recent liquid crystal display having a large area and high resolution liquid crystal panel, the load on the power supply increases, resulting in a problem in the output efficiency of the operating voltages. occurs Accordingly, in recent large-area liquid crystal display devices, a separate external boost circuit is additionally provided, and by using this, only VDD is output exclusively, thereby reducing the load on the power supply.

However, in a conventional liquid crystal display device, a power supply device and an external boost circuit are independently designed as separate components. Therefore, the output order of the plurality of operating voltages output from the power supply device and the external boost circuit is not interlocked and controlled.

As shown in FIG. 2, in the conventional liquid crystal display device, the power supply is delayed from the input voltage (Vin) according to predetermined delay times (DLY0, DLY1) according to the enable signal (EN) output from the controller to VCC , RST and VGL in order to generate and output operating voltages. In addition, the external boost circuit generates and outputs VDD from the input voltage Vin.

However, according to the operation sequence of the liquid crystal display, VDD should be output next to VGL output from the power supply. However, since the power supply device and the external boost circuit are not interlocked in the conventional liquid crystal display device, the output order of VDD generated by the external boost cannot be controlled.

Further, in a conventional liquid crystal display device, when either one of the power supply device or the external boost circuit becomes inoperable, the output of the power supply device or the external boost circuit cannot be controlled accordingly.

Due to this, in the conventional liquid crystal display device, driving circuits are damaged or an abnormal operation is performed, thereby degrading the operation reliability of the liquid crystal display device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply capable of stably controlling shut-down at the time of outputting voltages and when an abnormal operation occurs by controlling the operation of a sub power supply unit in a main power supply unit, and a display device including the same.

The power supply device of the present invention for achieving the above object includes a first power supply unit and a second power supply unit generating a plurality of operating voltages, and a control circuit for controlling their operations.

The control circuit outputs a first sequence control signal and a second sequence control signal according to the magnitude of the feedback voltage.

The first power unit generates a plurality of first operating voltages according to the first sequence control signal and sequentially outputs them.

The second power supply unit generates and outputs a second operating voltage according to the second sequence control signal, and generates and outputs a feedback voltage from the second operating voltage.

In the power supply device of the present invention, the control circuit provided in the main power supply unit can monitor the voltage output from the sub power supply unit to control the operation of the main power supply unit and the sub power supply unit.

Accordingly, it is possible to accurately control output timings of voltages output from each of the main power supply unit and the sub power supply unit. Also, when an abnormal operation occurs in either of the main power supply unit and the sub power supply unit, by stably shutting down both the main power supply unit and the sub power supply unit, it is possible to prevent an abnormal operation from occurring in the display device.

1 is a diagram schematically showing the configuration of a power supply unit in a conventional liquid crystal display device.
2 is a waveform diagram showing the operation of a power supply unit and an external boost circuit in a conventional liquid crystal display device.
3 is a diagram showing the configuration of a display device according to an exemplary embodiment of the present invention.
4 is a diagram showing the configuration of the power supply unit shown in FIG. 3;
FIG. 5 is a diagram illustrating a control circuit shown in FIG. 4 .
FIG. 6 is a diagram illustrating a boost circuit and a feedback circuit shown in FIG. 4 .
7 is a diagram showing a waveform diagram when the power supply unit of the present invention is normally operated.
8 is a diagram showing a waveform diagram when the power supply unit of the present invention is abnormally operated.

Hereinafter, a power supply device and a display device including the power supply device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram showing the configuration of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , the display device 100 of this embodiment includes a display panel 110, driving circuits, and a power supply 150 supplying a plurality of voltages (VCC, RST, VDD, VGH, VGL) to them. can include

The display panel 110 may be a large-area liquid crystal panel composed of two substrates bonded to each other with a liquid crystal layer (not shown) therebetween. The display panel 110 may include a plurality of gate lines GL and data lines DL that intersect each other, and pixels P formed at each crossing area thereof. Each pixel P may include a thin film transistor T, a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto.

The driving circuits may include a gate driver 120 , a data driver 130 and a timing controller 140 .

The gate driver 120 may generate gate signals according to the gate control signal GCS provided from the timing controller 140 and sequentially output them to the plurality of gate lines GL of the display panel 110 . The gate driver 120 may generate a gate signal according to a gate high voltage (VGH) and a gate low voltage (VGL) generated and output from the power supply 150 to be described later. The gate driver 120 is configured and disposed on at least one side of the display panel 110 in the form of a Cip On Film (COF) or configured in the form of a Gate In Panel (GIP) within the display panel 110. can be placed.

The data driver 130 may sample and latch the image data RGB′ according to the data control signal DCS provided from the timing controller 140 and convert the data into parallel data. The data driver 130 may generate positive/negative polarity analog data signals using positive/negative polarity gamma reference voltages (not shown) for the converted parallel data. Such a data signal may be output through a plurality of data lines DL when the gate line GL is enabled by the gate signal. The data driver 130 may invert the polarity of the positive/negative data signal according to the polarity control signal in the data control signal DCS.

Meanwhile, although not shown in the drawings, the driving circuit may further include a gamma reference voltage generator (not shown). The gamma reference voltage generator may generate positive/negative polarity gamma reference voltages by dividing the gamma reference voltage VDD output from the power supply unit 150 .

Meanwhile, the gamma reference voltage generator may generate positive/negative polarity gamma reference voltages by using the half-gamma reference voltage (HVDD) together with the gamma reference voltage (VDD). The reference voltage HVDD can be output together with the gamma reference voltage VDD.

The gamma reference voltage generator divides the gamma reference voltage (VDD) to generate positive polarity gamma reference voltages between the gamma reference voltage (VDD) and the half-gamma reference voltage (HVDD), and divides the half-gamma reference voltage (HVDD). Thus, negative gamma reference voltages between the half-gamma reference voltage HVDD and the ground voltage GND may be generated.

The timing controller 140 controls the gate from timing signals such as a control signal CNT provided from an external system (not shown), for example, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE. The signal GCS and the data control signal DCS may be generated and output. The gate control signal GCS may be output to the gate driver 120 and the data control signal DCS may be output to the data driver 140 .

Here, the gate control signal GCS may include a gate start pulse GSP, a gate shift clock signal GSC, and a gate output enable signal GOE. In addition, the data control signal (DCS) includes a source clock pulse signal (SCLK), a source start pulse signal (SSP), a carry signal (CR), a source output enable signal (SOE), a scan direction control signal (UP), and a bit inversion. A control signal REV and a polarity inversion control signal POL may be included.

In addition, the timing control unit 140 may convert the image signal RGB provided from an external system into image data RGB' that the data driver 130 can process and output.

The power supply unit 150 receives a plurality of operating voltages, for example, a logic voltage (VCC), a reset voltage (RST), a gamma reference voltage (VDD), a gate high voltage (VGH), and a gate voltage from an input voltage (Vin) provided from an external system. A plurality of operating voltages including the low voltage VGL may be generated and output.

The power supply unit 150 may sequentially generate and output a plurality of operating voltages according to a preset output sequence. For example, the power supply unit 150 outputs each operating voltage in order of a logic voltage (VCC), a reset voltage (RST), a gate low voltage (VGL), a gamma reference voltage (VDD), and a gate high voltage (VGH). can

The logic voltage VCC output from the power supply unit 150 is a voltage for operating the above-described driving circuits, that is, the timing controller 140, the gate driver 120, and the data driver 130, and is approximately 1.8V or It may have a magnitude of 3.3V. Also, the reset voltage RST is a voltage for resetting the timing controller 140 and may have a magnitude of approximately 1.8V or 3.3V. The gamma reference voltage VDD is a voltage for generating positive/negative polarity gamma voltages in the gamma reference voltage generator, and may have a magnitude of approximately 16V. The gate high voltage (VGH) and the gate low voltage (VGL) are voltages for generating a gate signal in the gate driver 120, and may have magnitudes of about 30V and -5V, respectively.

Meanwhile, the input voltage Vin input to the power supply unit 150 may have a magnitude of approximately 12V. When the power of the display device 100 is turned on, the input voltage Vin rises from 0V to 12V to operate the power supply unit 150, and when the power of the display device 100 is turned off, it falls from 12V to 0V. Thus, the operation of the power supply unit 150 may be stopped.

The power supply unit 150 is a main power supply unit for generating a plurality of operating voltages, such as a logic voltage (VCC), a reset voltage (RST), a gate high voltage (VGH), and a gate low voltage (VGL), respectively, for example, A first power supply unit and a sub power supply unit for generating only an operating voltage such as the gamma reference voltage (VDD), for example, a second power supply unit may be included.

4 is a diagram showing the configuration of the power supply unit shown in FIG. 3;

Referring to FIGS. 3 and 4 , the power supply unit 150 may include a first power supply unit 160 and a second power supply unit 170 . The first power supply unit 160 may be a main power supply unit composed of power ICs, and the second power supply unit 170 may be a sub power supply unit composed of boost ICs.

The first power supply unit 160 may generate a plurality of operating voltages including a logic voltage VCC, a reset voltage RST, a gate high voltage VGH and a gate low voltage VGL from the input voltage Vin. there is. The second power supply unit 170 may generate an operating voltage such as the gamma reference voltage VDD from the input voltage Vin.

The power supply unit 150 may include a control circuit 165 . The control circuit 165 generates a sequence control signal, for example, an internal sequence control signal En0 and an external sequence control signal En1, according to the feedback voltage FV provided from the feedback circuit 175 of the second power supply unit 170. can be printed out. As shown in the drawing, this control circuit 165 may be included in the first power supply unit 160 or configured independently of the first power supply unit 160 .

The first power supply unit 160 controls the logic voltage VCC, the reset voltage RST, the gate high voltage VGH and the gate low voltage VGL according to the internal sequence control signal En0 output from the control circuit 165. Generation and output timing can be controlled. The second power supply unit 170 may control the generation and output timing of the gamma reference voltage VDD according to the external sequence control signal En1 output from the control circuit 165 .

As shown in FIG. 5, the control circuit 165 includes a comparator 167 that compares the feedback voltage FV and the reference voltage Vref, and a switching element 168 that performs a switching operation according to the comparison result of the comparator 167. ) may be included.

The control circuit 165 outputs a high level internal sequence control signal En0 and an external sequence control signal En1 according to the switching operation of the switching element 168, or a low level internal sequence control signal En0. A control signal En0 and an external sequence control signal En1 may be output. Here, the control circuit 165 may output a high level external sequence control signal En1 after outputting the high level internal sequence control signal En0. Also, the control circuit 165 can simultaneously output the internal sequence control signal En0 and the external sequence control signal En1 of low level.

The operation of the control circuit 165 is as follows.

First, the feedback voltage FV from the feedback circuit 175 of the second power supply unit 170 may be input to one input terminal of the comparator 167 of the control circuit 165 . At this time, the reference voltage Vref may be input to the other input terminal of the comparator 167 .

The comparator 167 may output a signal capable of controlling the operation of the switching element 168, that is, a comparison result, according to a level difference between the feedback voltage FV and the reference voltage Vref.

In this case, when the feedback voltage FV is the same as or almost similar to the reference voltage Vref, the comparator 167 may output a low level comparison result. The switching element 168 is turned off according to the low-level comparison result, and accordingly, the control circuit 165 can output the high-level internal sequence control signal En0 and external sequence control signal En1.

When the high-level internal sequence control signal En0 and the external sequence control signal En1 are output from the control circuit 165, the first power supply unit 160 and the second power supply unit 170 operate normally to generate a plurality of voltages. and output the generated voltages in a predetermined order.

For example, the first power supply unit 160 sequentially generates a logic voltage VCC, a reset voltage RST, a gate low voltage VGL, and a gate high voltage VGH according to the high level internal sequence control signal En0. can be output as

Also, the second power supply unit 170 may generate and output the gamma reference voltage VDD according to the high level external sequence control signal En1. The gamma reference voltage VDD may be output after the gate low voltage VGL is output.

On the other hand, when the feedback voltage FV has a significantly smaller magnitude than the reference voltage Vref, the comparator 167 may output a high level comparison result. The switching element 168 is turned on according to the high level comparison result, and accordingly, the control circuit 165 can output the low level internal sequence control signal En0 and external sequence control signal En1.

When the internal sequence control signal En0 and the external sequence control signal En1 of low level are output from the control circuit 165, both the first power supply unit 160 and the second power supply unit 170 are shut down. ), the operation may be stopped. Therefore, multiple voltages are not output from the power supply unit 150 . Here, since the low-level internal sequence control signal En0 and the external sequence control signal En1 are simultaneously output, the first power supply unit 160 and the second power supply unit 170 may be simultaneously shut down.

As such, the control circuit 165 of the present embodiment outputs the internal sequence control signal En0 and the external sequence control signal according to the magnitude of the feedback voltage FV provided from the feedback circuit 175 of the second power supply unit 170. By changing the output level of (En1), the operation of the first power supply unit 160 and the second power supply unit 170 can be controlled. Accordingly, the power supply unit 150 of the present invention can easily adjust the generation and output timing of a plurality of voltages output from the first power supply unit 160 and the second power supply unit 170, and the first power supply unit 160 and Even if an abnormal situation occurs in any one of the second power supply units 170, malfunction of the power supply unit 150 may be prevented.

The second power supply unit 170 may generate and output the gamma reference voltage VDD from the input voltage Vin according to the level of the external sequence control signal En1 output from the control circuit 165 . The second power supply unit 170 may include a boost circuit 171 and a feedback circuit 175 .

The boost circuit 171 may generate the gamma reference voltage VDD from the input voltage Vin according to the level of the external sequence control signal En1 and output the gamma reference voltage VDD after the gate low voltage VGL is output. there is.

The feedback circuit 175 may generate a feedback voltage FV according to the gamma reference voltage VDD generated by the boost circuit 171 and output the feedback voltage FV to the control circuit 165 .

As shown in FIG. 6 , the boost circuit 171 may include an inductor (L), a diode (D), a PWM circuit 173 and a capacitor (C).

The inductor (L) may store current by the input voltage (Vin) according to the PWM signal (PWM) output from the PWM circuit (173).

The diode (D) can store current in the inductor (L) according to the PWM signal (PWM) output from the PWM circuit (173) or store the voltage boosted by the current stored in the inductor (L) in the capacitor (C). there is.

The operation of the PWM circuit 173 may be controlled according to the level of the external sequence control signal En1 output from the control circuit 165 of the first power supply unit 160 to output the PWM signal PWM.

The operation of the boost circuit 171 is as follows.

First, the operation of the PWM circuit 173 can be controlled by the external sequence control signal En1 output from the control circuit 165 of the first power supply unit 160 . The PWM circuit 173 may output a PWM signal PWM according to the high level external sequence control signal En1.

When the PWM signal (PWM) is output from the PWM circuit 173, the diode (D) is turned off in the high level section of the PWM signal (PWM), and the inductor (L) can store the current caused by the input voltage (Vin). .

Subsequently, the diode (D) is turned on during the low-level period of the PWM signal (PWM), and the current stored in the inductor (L) is converted into a voltage boosted by the turned-on diode (D) and is applied to the capacitor (C). can be stored

Also, the capacitor C may output the stored voltage as the gamma reference voltage VDD.

The feedback circuit 175 may include a first resistor R1 and a second resistor R2 connected in parallel to the output terminal of the boost circuit 171 . The first resistor R1 and the second resistor R2 may be connected in series with each other.

The feedback circuit 175 may divide the voltage of the gamma reference voltage VDD output from the boost circuit 171 through the first resistor R1 and the second resistor R2 and output the feedback voltage FV.

As such, in the boost circuit 171 of this embodiment, the generation and output timing of the gamma reference voltage VDD can be controlled according to the level of the external sequence control signal En1 output from the control circuit 165.

7 is a diagram showing a waveform diagram when the power supply unit of the present invention is normally operated.

As shown in FIG. 7 , when input voltage Vin is supplied from an external system to the power supply unit 150, the control circuit 165 of the first power supply unit 160 outputs a high level after the first delay time DLY0. An internal sequence control signal (En0) of can be generated.

Also, the first power supply unit 160 may sequentially generate and output a logic voltage VCC, a reset voltage RST, and a gate low voltage VGL according to the high level internal sequence control signal En0. Here, the reset voltage RST and the gate low voltage VGL may be generated and output after the second delay time DLY1 after the logic voltage VCC is generated.

Next, the control circuit 165 generates a high level external sequence control signal En1 after the third delay time DLY2 after the gate low voltage VGL is generated, and generates the external sequence control signal En1 of the second power supply unit 170. It can be output to the boost circuit 171.

The boost circuit 171 generates the PWM signal PWM according to the high level external sequence control signal En1, and generates and outputs the gamma reference voltage VDD from the input voltage Vin. In this case, the gamma reference voltage VDD may be output after the gate low voltage VGL is output from the first power supply unit 160 .

In addition, the feedback circuit 175 of the second power supply unit 170 outputs the feedback voltage FV obtained by voltage-dividing the gamma reference voltage VDD to the control circuit 165, and the control circuit 165 outputs the feedback voltage FV. ), the levels of the internal sequence control signal En0 and the external sequence control signal En1 may be changed.

As such, the power supply unit 150 of the present invention generates a plurality of voltages according to the internal sequence control signal En0 and the external sequence control signal En1 generated by the control circuit 165 of the first power supply unit 160 and Output timing can be controlled. Therefore, the operation sequence of the first power supply unit 160 and the second power supply unit 170 of the power supply unit 150 can be easily controlled.

8 is a diagram showing a waveform diagram when the power supply unit of the present invention is abnormally operated.

As shown in FIG. 8, when an abnormal situation such as an abnormal operation occurs in the second power supply unit 170 of the power supply unit 150, the gamma reference voltage VDD and the feedback voltage FV are output at a specific time point T0. this may be discontinued.

When the feedback voltage FV is not output from the second power supply unit 170, the control circuit 165 of the first power supply unit 160 may output a high level comparison result from the comparator 167. Accordingly, the switching element 168 of the control circuit 165 may be turned on to output the internal sequence control signal En0 and the external sequence control signal En1 of low level at a specific time point T0.

The low-level internal sequence control signal En0 output from the control circuit 165 may stop the operation of the first power supply unit 160 . In addition, the low level external sequence control signal En1 may stop the operation of the second power supply unit 170 .

In this way, the power supply unit 150 of the present invention shuts down the operation of both the first power supply unit 160 and the second power supply unit 170 when an operation error occurs in the second power supply unit 170, It is possible to prevent an abnormal operation from occurring in the display device 100 due to the abnormal power supply 150 .

As described above, the power supply unit 150 of the present invention includes the first power supply unit 160 and the second power supply unit 170, each of which generates operating voltages, and the control circuit of the first power supply unit 160 ( 165 may control the operation of the first power supply unit 160 and the second power supply unit 170 by monitoring the voltage output from the second power supply unit 170 . Therefore, the power supply unit 150 of the present invention can easily control the operation sequence of the first power supply unit 160 and the second power supply unit 170, and which one of the first power supply unit 160 and the second power supply unit 170 Even if an abnormal operation occurs in one device, it is possible to prevent an abnormal operation from occurring in the display device 100 due to this.

Although many details have been specifically described in the foregoing description, this should be interpreted as an example of a preferred embodiment rather than limiting the scope of the invention. Therefore, the invention should not be defined according to the described examples, but should be defined according to the scope of the claims and the scope of the claims.

100: display device 110: display panel
120: gate driving unit 130: data driving unit
140: timing control unit 150: power supply unit
160: first power supply unit 165: control circuit
170: second power supply unit 171: boost circuit
175: feedback circuit

Claims (9)

a control circuit outputting a first sequence control signal and a second sequence control signal according to the magnitude of the feedback voltage;
a first power supply unit generating and sequentially outputting a plurality of first operating voltages from an input voltage according to the first sequence control signal; and
A second power supply unit generating and outputting a second operating voltage from the input voltage according to the second sequence control signal and generating and outputting the feedback voltage from the second operating voltage;
The control circuit,
a comparator that compares the magnitudes of the feedback voltage and the reference voltage and outputs a comparison result; and
and a switching element configured to perform a switching operation according to the comparison result and output one of first and second sequence control signals of a first level and first and second sequence control signals of a second level. delete According to claim 1,
When the feedback voltage is the same as the reference voltage, the control circuit outputs first and second sequence control signals of the first level;
When the feedback voltage is smaller than the reference voltage, the control circuit outputs first and second sequence control signals of the second level;
The first level is a low level,
The second level is a high level power supply. According to claim 1,
the control circuit outputs the first sequence control signal of the first level before the second sequence control signal of the first level, and simultaneously outputs the first and second sequence control signals of the second level;
The first level is a high level,
The second level is a low level power supply. According to claim 1,
The plurality of first operating voltages include a logic voltage, a reset voltage, a gate low voltage and a gate high voltage, and the second operating voltage includes a gamma reference voltage;
The first power supply generates and outputs the logic voltage, the reset voltage, the gate low voltage, and the gate high voltage in order according to the first sequence control signal of the first level;
The second power supply unit generates the gamma reference voltage according to the second sequence control signal of the first level and outputs the gamma reference voltage after the gate low voltage is output;
The first level is a high level power supply. According to claim 1,
The first power supply unit and the second power supply unit are both shut down according to the first and second sequence control signals of the second level;
The second level is a low level power supply. According to claim 1,
The second power supply unit,
a boost circuit generating the second operating voltage according to the second sequence control signal; and
and a feedback circuit generating the feedback voltage from the second operating voltage. According to claim 7,
The feedback circuit is composed of one or more resistors connected to an output terminal of the boost circuit, and generates the feedback voltage by voltage dividing the second operating voltage. a gate driver outputting gate signals to a plurality of gate lines of the display panel;
a data driver outputting data signals to a plurality of data lines of the display panel;
a timing controller controlling operations of the gate driver and the data driver; and
A power supply unit outputting a plurality of operating voltages to the gate driver, data driver, and timing controller;
The power supply unit,
a control circuit outputting a first sequence control signal and a second sequence control signal according to the magnitude of the feedback voltage;
a first power supply unit generating and sequentially outputting a plurality of first operating voltages from an input voltage according to the first sequence control signal; and
A second power supply unit generating and outputting a second operating voltage from the input voltage according to the second sequence control signal and generating and outputting the feedback voltage from the second operating voltage;
The control circuit,
a comparator that compares the magnitudes of the feedback voltage and the reference voltage and outputs a comparison result; and
A display device comprising a switching element configured to perform a switching operation according to the comparison result and output one of first and second sequence control signals of a first level and first and second sequence control signals of a second level.

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