KR102504600B1 - Source driver ic for compensating display fan-out and display system having same - Google Patents

Abstract

A source driver IC capable of driving a flat panel display includes a first control logic circuit generating first output signals for driving first source lines arranged in a first area of the flat panel display, and a second area of the flat panel display. and a second control logic circuit for generating second output signals for driving second source lines disposed on, wherein a first output delay between two adjacent output signals among the first output signals and the second control logic circuit. Second output delays between two adjacent output signals among the two output signals are different from each other.

Description

A source driver IC capable of compensating for display fan-out and a display system including the same

Embodiments according to the concept of the present invention relate to a source driver IC, and in particular, to a source driver IC capable of compensating for fan-out of a display panel and partially adjusting an output delay time, and a display system including the same.

As the size of a display panel included in a display device increases, RC delay of a gate line included in the display panel increases. As the scan rate of the display panel increases and the resolution of the display panel increases, a gate signal transmitted through a gate line included in the display panel and transmitted through a source line (or data line) included in the display panel The timing margin between the data signals to be reduced.

The size of a printed circuit board (PCB) connected to a plurality of source driver ICs driving pixels disposed on a display panel tends to be reduced for cost reduction. Accordingly, the fan-out of the display panel driven by each source driver IC may be different or asymmetric for each source driver IC. As the size of the display panel increases, the fan-out of the display panel driven by the source driver IC increases, but the conventional source driver IC cannot accurately compensate for the fan-out of the display panel.

A technical problem to be achieved by the present invention is to provide a source driver IC capable of compensating for fan-out of a display panel and partially adjusting an output delay time, and a display system including the same.

A source driver IC capable of driving a flat panel display according to an embodiment of the present invention includes a first control logic circuit generating first output signals for driving first source lines disposed in a first area of the flat panel display; and a second control logic circuit generating second output signals for driving second source lines disposed in a second region of the flat panel display, wherein a signal between two adjacent output signals among the first output signals A first output delay and a second output delay between two adjacent output signals among the second output signals are different from each other.

The first control logic circuit divides each of the input clocks at a first division ratio and generates each of the first enable signals related to the generation of each of the first output signals, and the second control logic circuit divides the input clocks at a first division ratio. Dividing each of the clocks at a second division ratio, generating each of second enable signals related to the generation of each of the second output signals, the first output delay being determined according to the first division ratio, The second output delay is determined according to the second division ratio.

The first control logic circuit sequentially outputs first pulses selected from the pulse sequences of each of the first division clocks divided at the first division ratio as the first enable signals, and the second control logic circuit outputs the first pulses sequentially as the first enable signals. Second pulses selected from the pulse sequences of each of the second frequency division clocks divided at a frequency division ratio of 2 are sequentially output as the second enable signals.

The number of the first division clocks is less than the number of the first enable signals, and the number of the second division clocks is less than the number of the second enable signals.

The first control logic circuit generates the first enable signals in the same order or in the opposite order to the input order of the input clocks in response to a control signal.

The second control logic circuit generates the second enable signals in the same order or in an opposite order to the input order of the input clocks in response to the control signal.

According to embodiments, a third output delay between a last output signal among the first output signals and a first output signal among the second output signals is different from the second output delay.

According to embodiments, a third output delay between a last output signal among the first output signals and a first output signal among the second output signals is equal to the first output delay.

According to an embodiment of the present invention, a source driver IC capable of driving a flat panel display includes first output signals for driving a first source line and a second source line adjacent to each other, among source lines disposed on the flat panel display. and second output signals driving the third source line and the fourth source line adjacent to each other, wherein the first output delay between the first output signals is a second output delay between the second output signals and are different from each other

The source driver IC divides each of the input clocks at a first division ratio to generate each of the first enable signals related to the generation of each of the first output signals, and each of the input clocks. and a second control logic circuit for generating each of the second enable signals related to the generation of each of the second output signals by dividing them at a second division ratio, wherein the first output delay is determined according to the first division ratio. and the second output delay is determined according to the second division ratio.

The first control logic circuit generates the first enable signals in the same order or in the opposite order to the input order of the input clocks in response to a control signal. The second control logic circuit generates the second enable signals in the same order or in an opposite order to the input order of the input clocks in response to the control signal.

A display system according to an embodiment of the present invention drives a flat panel display including a first area and a second area, and first source lines disposed in the first area and second source lines disposed in the second area. It includes a source driver IC capable of

The source driver IC includes a first control logic circuit generating first output signals for driving the first source lines and a second control logic circuit generating second output signals for driving the second source lines. A first output delay between two adjacent output signals among the first output signals is different from a second output delay between two adjacent output signals among the second output signals.

The first control logic circuit generates first enable signals related to generation of the first output signals by dividing each of the input clocks at a first division ratio, and the second control logic circuit divides each of the input clocks at a division ratio. is divided by a second division ratio to generate each of the second enable signals related to the generation of each of the second output signals, the first output delay is determined according to the first division ratio, and the second output delay Is determined according to the second division ratio.

The source driver IC according to the embodiment of the present invention has an effect of compensating for fan-out of the display panel. The source driver IC has an effect of partially adjusting output delay times of output signals of the source driver IC.

The source driver IC has an effect of compensating for an RC delay of a gate line included in a display panel.

The source driver IC has an effect of removing a mismatch occurring at a boundary where a spread step is changed.

As the source driver IC is used in a display system, there is an effect of removing design restrictions on a PCB connected to the source driver IC.

A detailed description of each drawing is provided in order to more fully understand the drawings cited in the detailed description of the present invention.
1 shows a block diagram of a display system including source driver ICs according to an embodiment of the present invention.
2 is a conceptual diagram for explaining fan-out and output delay of each of conventional source driver ICs.
FIG. 3 shows a schematic block diagram of the source driver IC shown in FIG. 1 .
FIG. 4 shows a detailed block diagram of the source driver IC shown in FIG. 1;
FIG. 5 is a circuit diagram of the first driver cell block shown in FIG. 4 .
6 is a block diagram of the control logic circuit block shown in FIG. 4;
FIG. 7 shows a timing diagram of basic clocks output from the basic clock generator shown in FIG. 6 .
FIG. 8 shows a timing diagram of output signals of the first control logic shown in FIG. 6 .
FIG. 9 is a timing diagram of output signals of the first enable signal generator shown in FIG. 6 .
FIG. 10 is a timing diagram of output signals of the fourth control logic shown in FIG. 6 .
FIG. 11 is a timing diagram of output signals of the fourth enable signal generator shown in FIG. 6 .
12 is a block diagram of the control logic circuit block shown in FIG. 4;
FIG. 13 shows output delay times of output signals of the control logic circuit block shown in FIG. 4 or FIG. 12 .
14 is a timing diagram illustrating an output delay according to an embodiment of the present invention.
15 shows a start delay and an output delay time of each of source driver ICs according to embodiments of the present invention.
16 is a conceptual diagram illustrating fan-out and output delay of each of source driver ICs according to embodiments of the present invention.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification are only illustrated for the purpose of explaining the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention It can be embodied in various forms and is not limited to the embodiments described herein.

Embodiments according to the concept of the present invention can apply various changes and have various forms, so the embodiments are illustrated in the drawings and described in detail in this specification. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosure forms, and includes all changes, equivalents, or substitutes included in the spirit and technical scope of the present invention.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another, e.g. without departing from the scope of rights according to the concept of the present invention, a first component may be termed a second component and similarly a second component may be termed a second component. A component may also be referred to as a first component.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when a component is referred to as “directly connected” or “directly connected” to another component, it should be understood that no other component exists in the middle. Other expressions describing the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", etc., should be interpreted similarly.

Terms used in this specification are used only to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "having" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in this specification, but one or more other features It should be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in this specification, it should not be interpreted in an ideal or excessively formal meaning. don't

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows a block diagram of a display system including source driver ICs according to an embodiment of the present invention. Referring to FIG. 1 , a display system 100 includes a flat panel display 110, a plurality of source driver ICs 121 and 123, a timing controller 125, and a plurality of gate driver ICs 127 and 127. 129) may be included.

The display system 100 may be implemented as a personal computer (PC), a digital TV, an IP TV, or a mobile device. The flat panel display 110 may include a TFT-LCD panel, an LED panel, an OLED panel, and an AMOLED panel, but is not limited thereto. Although FIG. 1 shows a TFT LCD panel as an example of the flat panel display 110, it is not limited thereto.

The TFT LCD panel 110 may include a plurality of source lines, a plurality of gate lines, and a plurality of pixels. Each of the plurality of pixels may be connected to each of the plurality of source lines and each of the plurality of gate lines.

Each source driver IC 121 and 123 may be connected to each flexible printed circuit (FPC) 120 and 122, and each FPC 120 and 122 is connected to a source driver PCB 124 and a TFT LCD panel. (110). The timing controller 125 may be mounted on the source driver PCB 124.

The timing controller 125 can generate control signals capable of controlling each source driver IC 121 and 123, and each source driver IC 121 and 123 responds to the control signals to display a TFT-LCD panel. Among the included source lines, source lines assigned to it can be driven.

Each gate driver 127 and 129 may be connected to each FPC 126 and 128. Each of the FPCs 126 and 128 may be connected to a gate driver PCB (not shown) and the TFT LCD panel 110 . For example, each component 120, 122, 126, and 127 may mean a chip on film (COF) or a COF package, but is not limited thereto.

The source driver ICs 121 and 123 may drive a plurality of source lines disposed on the TFT LCD panel 110 under the control of the timing controller 125 . The gate driver ICs 127 and 129 may drive a plurality of gate lines disposed on the TFT LCD panel 110 under the control of a controller included in a gate driver PCB (not shown). That is, according to the control of the source driver ICs 121 and 123 and the gate driver ICs 127 and 129, pixels disposed on the TFT LCD panel 110 may display data.

Although, in FIG. 1, two source driver ICs 121 and 123 and two gate driver ICs 127 and 129 are illustratively shown, the number of source driver ICs included in the display system 100 and The number of gate driver ICs may be variously changed according to embodiments.

For example, the first source driver IC 121 may control the source lines Y1R to Y960R included in the two regions RG1 and RG2 of the TFT LCD panel 110, and the second source driver IC ( 123), it is assumed that source lines (Y1L to Y960L) included in two regions (RG3 and RG4) of the TFT LCD panel 110 can be controlled.

Each of the source driver ICs 121 and 123 generates enable signals (or output signals) having different output delays (or output delay times) according to the position of a channel or the position of a channel group. can Accordingly, each of the source driver ICs 121 and 123 can compensate for the fan-out of the TFT-LCD panel 110 and the RC delay of the gate line. Even if the TFT-LCD panel 110 has a large gate line delay and a high scan rate, the source driver ICs 121 and 123 can generate output signals having effective output characteristics.

A channel may mean a source line (or data line) for transmitting data, and a channel group may include at least two channels. According to embodiments, each of the source driver ICs 121 and 123 may control a different output delay (or delay amount) for each channel or each channel group.

According to embodiments, the source driver IC 121 may adjust the first delay between the first channel and the second channel and the second delay between the second channel and the third channel differently from each other, and the second delay and The third delay between the third channel and the fourth channel may be differently adjusted.

According to embodiments, the source driver IC 121 may adjust the first delay between the first channel group and the second channel group and the second delay between the second channel group and the third channel group differently from each other, and the The second delay and the third delay between the third and fourth channel groups may be differently adjusted. However, the source driver IC 121 can equally adjust the delay between two adjacent channels among channels included in the same channel group.

2 is a conceptual diagram for explaining fan-out and output delay of each of conventional source driver ICs. Referring to FIG. 2 , the TFT-LCD panel 110A includes four regions RG11 to RG14, and the conventional source driver IC (S-IC1) included in the FPC 131 includes a first region RG11. ) and controls the source lines (Y1-1 to Y960-1) included in the FPC 133, and the conventional source driver IC (S-IC2) included in the FPC 133 controls the source lines included in the second region RG12. (Y1-2 to Y960-2), and the conventional source driver IC (S-IC3) included in the FPC 135 connects the source lines (Y1-3 to Y960- 3), and the conventional source driver IC (S-IC4) included in the FPC 137 controls the source lines Y1-4 to Y960-4 included in the fourth region RG14. . Each of the FPCs 131, 133, 135, and 137 is connected to the TFT-LCD panel 110A through a connecting means 130.

Referring to FIG. 2, the arrangement positions of each source driver IC (S-IC1, S-IC2, S-IC3, and S-IC4) corresponding to each area (RG11, RG12, RG13, and RG14) are different. For example, when viewed from the center of the first region RG11, the source driver IC (S-IC1) is displaced to the left, and when viewed from the center of the second region RG12, the source driver IC (S-IC2) ) is skewed to the left, the source driver IC (S-IC3) is skewed to the right when viewed from the center of the third region RG13, and the source driver IC (S-IC3) is disposed to the right when viewed from the center of the fourth region RG14. The driver IC (S-IC4) is displaced to the right. In addition, the source driver IC (S-IC1) is more to the left than the source driver IC (S-IC2), and the source driver IC (S-IC4) is more to the right than the source driver IC (S-IC3). do.

Figure 2 (a) shows the fan-out according to the arrangement position of each source driver IC (S-IC1, S-IC2, S-IC3 and S-IC4). Figure 2 (b) shows the ideal output delay according to the arrangement position of each source driver IC (S-IC1, S-IC2, S-IC3 and S-IC4). Figure 2 (c) shows the actual output delay according to the arrangement position of each source driver IC (S-IC1, S-IC2, S-IC3 and S-IC4). Referring to (c) of FIG. 2, the actual output delay does not consider the arrangement position of each channel.

FIG. 3 shows a schematic block diagram of the source driver IC shown in FIG. 1 . Referring to FIG. 3 , the structure of the first source driver IC 121 is the same as or similar to the structure of the second source driver IC 123 .

Referring to FIG. 3 , the source driver IC 121 includes a control logic circuit block 121-1 generating enable signals, a plurality of driver cells DRV_CELL1 to DRV_CELL960, and a plurality of pads P1 to P960. can include A pad may mean a pin. The internal structure of the first source driver IC 121 shown in FIG. 3 is for description and may be variously changed according to embodiments. Each of the plurality of driver cells (DRV_CELL1 to DRV_CELL960) has the same or similar structure. Each of the plurality of pads P1 to P960 may be connected to each of the plurality of source lines Y1R to Y960R through each of the metal lines disposed on the FPC 120 .

FIG. 4 shows a detailed block diagram of the source driver IC shown in FIG. 1;

1, 3, and 4, the first source driver IC 121 drives 960 source lines (Y1R to Y960R) included in two areas (RG1 and RG2), and The 480 source lines (Y1R to Y480R) included in the region RG1 are controlled by 40 right enable signals (RSTR<1> to RSTR<40>), and the right enable signals ( It is assumed that each of RSTR<1> to RSTR<40>) adjusts the output delay of 12 driver cells.

In addition, 480 source lines Y481R to Y960R included in the second region RG2 are controlled by 40 left enable signals LSTR<1> to LSTR<40>, and the left-in It is assumed that each of the enable signals LSTR<1> to LSTR<40> controls the output delay of 12 driver cells.

For example, enabling or disabling of the first driver cell block 210 - 1 including 12 driver cells DRV_CELL1 to DRV_CELL12 may be controlled by a first write enable signal RSTR<1>. When the first driver cell block 210-1 is enabled by the first write enable signal RSTR<1>, the 12 output signals DS1 to DS12 are simultaneously or in parallel 12 source lines ( Y1R to Y12R). Each of the output signals DS1 to DS960 may refer to a driving signal for driving each source line Y1R to Y960R.

Enabling or disabling of the second driver cell block 210 - 2 including 12 driver cells DRV_CELL13 to DRV_CELL24 may be controlled by the second write enable signal RSTR<2>. For example, when the second driver cell block 210 - 2 is enabled, 12 output signals DS13 to DS24 may be simultaneously or in parallel transmitted through 12 source lines Y13R to Y24R.

Enabling or disabling of the 40th driver cell block 210 - 40 including 12 driver cells DRV_CELL469 to DRV_CELL480 may be controlled by the 40th write enable signal RSTR<40>. For example, when the 40th driver cell block 210-40 is enabled, 12 output signals DS469 to DS480 may be simultaneously or in parallel transmitted through 12 source lines Y469R to Y480R.

Enabling or disabling of the 41st driver cell block 210 - 41 including 12 driver cells DRV_CELL481 to DRV_CELL492 may be controlled by the first left enable signal LSTR<1>. When the 41st driver cell block 210-41 is enabled by the first left enable signal LSTR<1>, the 12 output signals DS481 to DS492 are simultaneously or in parallel 12 source lines ( Y481R to Y492R).

Enabling or disabling of the 42nd driver cell block 210 - 42 including 12 driver cells DRV_CELL493 to DRV_CELL504 may be controlled by the second left enable signal LSTR<2>. For example, when the 42nd driver cell block 210-42 is enabled, 12 output signals DS493 to DS504 may be simultaneously or in parallel transmitted through 12 source lines Y493 to Y504R.

Enabling or disabling of the 80th driver cell block 210-80 including 12 driver cells DRV_CELL949 to DRV_CELL960 may be controlled by the 40th left enable signal LSTR<40>. For example, when the 80th driver cell blocks 210-80 are enabled, 12 output signals DS949 to DS960 may be simultaneously or in parallel transmitted through 12 source lines Y949R to Y960R.

The control logic circuit block 121-1 generates respective enable signals RSRT<1> to RSTR<40> and LSTR<1> to LSTR<40> in response to the basic clock BCLK and control signals. Generation timing and/or generation direction may be controlled. For example, the enable signals RSRT<1> to RSTR<20> having the timing shown in FIG. 9 may be defined as enable signals having the first direction, and the timing shown in FIG. The enable signals LSRT<21> to LSTR<40> may be defined as enable signals having a second direction.

FIG. 5 is a circuit diagram of the first driver cell block shown in FIG. 4 . Structures and operations of the respective drive cell blocks 210-1 to 210-80 are the same or similar. Referring to FIGS. 4 and 5 , the first driver cell block 210 - 1 may include 12 driver cells DRV_CELL1 to DRV_CELL12 . Each driver cell (DRV_CELL1 to DRV_CELL12) may include a data register, a level shifter, a decoder, and an output buffer.

The first driver cell DRV_CELL1 may include a data register 311 , a level shifter 313 , a decoder 315 , and an output buffer 317 . The data register 311 latches data DATA in response to the first shift clock Sft_CLK1 and transmits the latched data to the level shifter 313 in response to the first write enable signal RSRT<1>. can The level shifter 313 shifts the level of the data output from the data register 311, outputs the level-shifted data to the decoder 315, and the decoder 315 outputs a plurality of gray scales based on the level-shifted data. One of the voltages V0 to V63 is selected, and the selected voltage is output to the output buffer 317 . The output buffer 317 may buffer the voltage (eg, analog voltage) selected by the decoder 315 and supply the buffered voltage DS1 to the first source line Y1R through the first output pad P1. there is.

Simultaneously or in parallel with the operation of the first driver cell DRV_CELL1, the twelfth driver cell DRV_CELL12 may supply the buffered voltage DS12 to the twelfth source line Y12R through the twelfth output pad P12. . The data register 321 latches data DATA in response to the twelfth shift clock Sft_CLK12 and transmits the latched data to the level shifter 323 in response to the first write enable signal RSRT<1>. can The level shifter 323 shifts the level of the data output from the data register 321, outputs the level-shifted data to the decoder 325, and the decoder 325 outputs a plurality of gray scales based on the level-shifted data. One of the voltages V0 to V63 is selected, and the selected voltage is output to the output buffer 327 . The output buffer 327 may buffer the voltage (eg, analog voltage) selected by the decoder 325 and supply the buffered voltage DS12 to the twelfth source line Y12R through the twelfth output pad P12. there is. A plurality of gray scale voltages (V0 to V63) may be generated from the gray scale voltage generator 330.

6 is a block diagram of the control logic circuit block shown in FIG. 4;

1, 4, and 6, a control logic circuit block 121-1 includes a clock source 410, a basic clock generator 415, and a plurality of control logics 420-1 to 420-4. , and enable signal generators 425-1 to 425-4. According to embodiments, each enable signal generator 425-1 to 425-4 may be included in each control logic 420-1 to 420-4. It is assumed that the first source driver IC 121 includes four control logics 420-1 to 420-4 and four enable signal generators 425-1 to 425-4. According to embodiments, the number of control logics and the number of enable signal generators may be changed.

The clock source 410 may generate the source clock MCLK. The basic clock generator 415 may generate a plurality of basic clocks BCLK using the source clock MCLK.

FIG. 7 shows a timing diagram of basic clocks output from the basic clock generator shown in FIG. 6 . Referring to FIGS. 6 and 7 , it is assumed that the basic clock generator 415 can generate 10 basic clocks BLCK<1> to BCLK<10>. However, according to embodiments, the number of basic clocks that can be generated by the basic clock generator 415 may be variously changed. In this specification, clock may mean a clock signal, and control logic may mean a control logic circuit.

FIG. 8 shows a timing diagram of output signals of the first control logic shown in FIG. 6 .

For example, assuming that the first division ratio DV_1 is 3, the first control logic 420-1 sets each of the 10 basic clocks BLCK<1> to BCLK<10> to the first division ratio DV_1= 3), and only a part of the pulse sequence of each divided clock (CLKA<1> to CLKA<10>) can be selectively output.

For example, the first control logic 420-1 divides the basic clock (BCLK<1>) by 3, and only the two pulses defined as (1) and (11) among the divided clocks (CLKA<1>) can output The first control logic 420-1 divides the basic clock (BCLK<2>) by 3 and outputs only two pulses defined as (2) and (12) among the divided clocks (CLKA<2>). can do. The first control logic 420-1 divides the basic clock (BCLK<10>) by 3 and outputs only two pulses defined as (10) and (20) among the divided clocks (CLKA<10>). can do.

The first enable signal generator 425-1 receives 10 clocks (CLKA<1> to CLKA<10>) having a first direction, and responds to a control signal at the timing shown in FIG. 9 ( Alternatively, write enable signals RSTR<1> to RSTR<20> having a first direction) may be generated. For example, the first write enable signal RSTR<1> is a pulse defined as (1) in the clock CLKA<1> shown in FIG. 8, and the second write enable signal RSTR<2> is Pulse defined as (2) in the clock CLKA<2> shown in FIG. 8, and the tenth write enable signal RSTR<10> is defined as (10) in the clock CLKA<10> shown in FIG. ) is the pulse defined by

The eleventh write enable signal RSTR<11> is a pulse defined by (11) in the clock CLKA<1> shown in FIG. 8, and the twelfth write enable signal RSTR<12> is the pulse of FIG. is a pulse defined as (12) in the clock (CLKA<2>) shown in , and the twentieth write enable signal (RSTR<20>) is defined as (20) in the clock (CLKA<10>) shown in FIG. It is a defined pulse.

The first write enable signal RSTR<1> is supplied to the first driver cell block 210-1, and the second write enable signal RSTR<2> is supplied to the second driver cell block 210-2. and the twentieth write enable signal RSTR<20> is supplied to the twentieth driver cell block.

For example, assuming that the second division ratio DV_2 is 1, the second control logic 420-2 may selectively output only some of 10 basic clocks BLCK<1> to BCLK<10>. . The operation of the second control logic 420-2 and the operation of the first control logic 420-1 are the same or similar, and the operation of the second enable signal generator 425-2 is the first enable signal generator ( 425-1) is the same as or similar to the operation.

That is, the second control logic 420-2 outputs clocks CLKB having a first direction, and the second enable signal generator 425-2 outputs write enable signals RSRT having a first direction. <21>~RSTR<40>) can be output. At this time, it is assumed that N in FIG. 6 is 4.

Excluding that the first division ratio DV_1 is 3 and the second division ratio DV_2 is 1, from the 21st write enable signal RSTR<21> to the 40th write enable signal RSTR<40> It is assumed that the timing for the waveforms is similar to that for the waveforms shown in FIG. 9 . That is, the second enable signal generator 425-2 may generate write enable signals RSTR<21> to (RSTR<40>) having a first direction.

Accordingly, the 21st write enable signal RSTR<21> is supplied to the 21st driver cell block, the 22nd write enable signal RSTR<22> is supplied to the 22nd driver cell block, and the 40th write-in The enable signal RSTR<40> is supplied to the 40th driver cell block 210-40.

For example, assuming that the third division ratio DV_3 is 3, the third control logic 420-3 controls each of the 10 basic clocks BLCK<1> to BCLK<10> to the third division ratio DV_3= 3), and only some of the divided clocks (CLKC=CLKC<1>~CLKC<10>) can be selectively output. The structure and operation of the third control logic 420-3 are the same as or similar to those of the first control logic 420-1, and the structure and operation of the third enable signal generator 425-3 are the same as those of the first control logic 420-1. The structure and operation of the 1-enable signal generator 425-1 are identical or similar.

9 shows the waveforms of the first left enable signal LSTR<1> to the twentieth left enable signal LSTR<20> generated by the third enable signal generator 425-3. Assume similar timing for the waveforms shown. That is, the third enable signal generator 425 - 3 may generate first left enable signals LSTR<1> to (LSTR<20>) having a first direction.

Accordingly, the first left enable signal LSTR<1> is supplied to the 41st driver cell block 210-41, and the second left enable signal LSTR<2> is supplied to the 42nd driver cell block 210-41. 42), and the 20th left enable signal is supplied to the 60th driver cell block.

FIG. 10 is a timing diagram of output signals of the fourth control logic shown in FIG. 6 , and FIG. 11 is a timing diagram of output signals of the fourth enable signal generator shown in FIG. 6 .

For example, assuming that the fourth division ratio DV_4 is 1, the fourth control logic 420-4 controls each of the 10 basic clocks BLCK<1> to BCLK<10> at the fourth division ratio DV_4= 1), and only a part of the pulse sequence of each clock (CLKD<1>~CLKD<10>) can be selectively output.

For example, the fourth control logic 420-4 outputs only two pulses defined as (1) and (11) among the clock (CLKD<1>) generated based on the basic clock (BCLK<1>). can The fourth control logic 420-4 may output only two pulses defined as (2) and (12) among the clock (CLKD<2>) generated based on the basic clock (BCLK<2>). . The fourth control logic 420-4 may output only two pulses defined as (10) and (20) among the clock (CLKD<10>) generated based on the basic clock (BCLK<10>). .

The fourth enable signal generator 425-4 receives 10 clocks (CLKD<1> to CLKD<10>) and responds to a control signal to enable a left enable signal having timing as shown in FIG. 11 . s (LSTR<21> to LSTR<40>) can be created. That is, the fourth enable signal generator 425-4 may generate left enable signals LSTR<21> to LSTR<40> having the second direction.

For example, the 21st left enable signal LSTR<21> is a pulse defined as (1) in the clock CLKD<1> shown in FIG. 10, and the 22nd left enable signal LSTR<22> is It is a pulse defined as (2) in the clock (CLKD<2>) shown in FIG. 10, and the 30th left enable signal (LSTR<30>) is (10) in the clock (CLKD<10>) shown in FIG. ) is the pulse defined by The 31st left enable signal LSTR<31> is a pulse defined by (11) in the clock CLKD<1> shown in FIG. 10, and the 32nd left enable signal LSTR<32> is is a pulse defined as (12) in the clock (CLKD<2>) shown in , and the 40th left enable signal (LSTR<40>) is defined as (20) in the clock (CLKD<10>) shown in FIG. It is a defined pulse.

The 21st left enable signal LSTR<21> is supplied to the 61st driver cell block, the 22nd left enable signal LSTR<22> is supplied to the 62nd driver cell block, and the 40th left enable signal (LSTR<40>) is supplied to the 80th driver cell block 210-80.

For example, each of the control logics 420-1 to 420-4 may use clocks having a delay (or timing) shown in FIG. 8 or a delay (or timing) shown in FIG. 10 based on the control signal SWI. It is possible to generate clocks with That is, each of the control logics 420-1 to 420-4 may control the generation direction (eg, first direction or second direction) of the clock signals based on the control signal SWI. In addition, each of the control logics 420-1 to 420-4 may adjust the number of pulses included in each of the output clock signals based on the control signal SWI. Each of the enable signal generators 425-1 to 425-4 may adjust generation timing of enable signals. The control signal SWI may include one or more bits. Each of the above bits may be defined as logic 1 or logic 0.

12 is a block diagram of the control logic circuit block shown in FIG. 4;

Referring to FIGS. 6 and 12 , the control logic circuit block 121-1 may include a plurality of control logics. Each control logic generates enable signals (RSTR<1>~RSTR<40/0.5N>, RSTR<(40/0.5N)+1>~RSTR<80/ 0.5N>, RSTR<39>, RSTR<40>, LSTR<1>~LSTR<40/0.5N>, LSTR<(40/0.5N)+1>~LSTR<80/0.5N>, LSTR<39 >, and generation timing and/or generation direction of LSTR<40>) may be controlled.

FIG. 13 shows output delay times of output signals of the control logic circuit block shown in FIG. 4 or FIG. 12 . Referring to FIGS. 1, 4, 6, and 13, 240 included in the first region RG1 using the first control logic 420-1 and the first enable signal generator 425-1. Write enable signals (RSTR<1> to RSTR<20>) having a first direction driving the source lines Y1R to Y240R may be generated, and the second control logic 420-2 and the second control logic 420-2 Write enable signals (RSTR<21> ~RSTR<40>) can be generated, and 240 source lines included in the second region RG2 can be generated by using the third control logic 420-3 and the third enable signal generator 425-3. Left enable signals (LSTR<1> to LSTR<20>) having a first direction driving Y481R to Y720R may be generated, and the fourth control logic 420-4 and the fourth enable signal may be generated. Left enable signals (LSTR<21> to LSTR<40 >) can be created.

Referring to FIG. 13, the delay between the two write enable signals (RSTR<20> and RSTR<21>) and the delay between the two write enable signals (RSTR<21> and RSTR<22>) are different from each other. can be different. Also, a delay between the two write enable signals RSTR<1> and RSTR<2> and a delay between the two write enable signals RSTR<22> and RSTR<23> may be different from each other. .

A delay between the two enable signals RSTR<40> and LSTR<1> and a delay between the two enable signals LSTR<1> and LSTR<2> may be different from each other. Also, a delay between two write enable signals RSTR<39> and RSTR<40> and a delay between two left enable signals LSTR<2> and LSTR<3> may be different from each other. .

A delay between the two left enable signals LSTR<20> and LSTR<21> and a delay between the two left enable signals LSTR<21> and LSTR<22> may be different from each other. Also, the delay between the two left enable signals LSTR<19> and LSTR<20> and the delay between the two left enable signals LSTR<22> and LSTR<23> may be different from each other. .

The division ratio may mean a spread step. As described with reference to FIG. 6 , the first division ratio DV_1 allocated to the first control logic 420-1 is 3, and the second division ratio DV_2 allocated to the second control logic 420-2. ) is 1, the third division ratio DV_3 allocated to the third control logic 420-3 is 3, and the fourth division ratio DV_4 allocated to the fourth control logic 420-4 is 1. . However, referring to FIG. 13, mismatch does not occur at each boundary where each spread step is changed.

For example, the second control logic 420-2 may determine the generation timing of the twenty-first write enable signal RSTR<21> using the output signals of the first control logic 420-1, and may determine the generation timing of the third control logic 420-1. The logic 420-3 may determine the generation timing of the first left enable signal LSTR<1> using the output signals of the second control logic 420-2, and the fourth control logic 420-4 ) may determine the generation timing of the twenty-first left enable signal LSTR<21> using the output signals of the third control logic 420-3.

14 is a timing diagram illustrating an output delay according to an embodiment of the present invention. 6, 13, and 14, the division ratio (or spread step) of the first control logic 420-1 is 4 and the division ratio (or spread step) of the second control logic 420-2 is 1, and if there is a start delay in the second control logic 420-2, the difference between the division ratio of the first control logic 420-1 and the division ratio of the second control logic 420-2 A mismatch at a boundary between enable signals (eg, RSTR<20> and RSTR<21>) may be eliminated according to embodiments of the present invention.

15 shows a start delay and an output delay time of each of source driver ICs according to embodiments of the present invention.

13 to 15, the second control logic 420-2 is adjusted so that the first start delay D1 exists between the first logic clock LOGIC1_CLK and the second logic clock LOGIC2_CLK. The third control logic 420-3 is adjusted so that the second start delay D2 exists between the first logic clock LOGIC1_CLK and the third logic clock LOGIC3_CLK, and the third start delay D3 corresponds to the first logic clock LOGIC1_CLK. When the fourth control logic 420-4 is adjusted to exist between the clock (LOGIC1_CLK) and the fourth logic clock (LOGIC4_CLK), each boundary where each spread step is changed (eg, RSTR<20> and RSTR<21>) , between RSRT<40> and LSTR<1>, and between LSTR<20> and LSTR<21>) can be eliminated.

According to example embodiments, the first logic clock LOGIC1_CLK may be a clock related to generation of the first write enable signal RSTR<1>, and the second logic clock LOGIC2_CLK may be a twenty-first write enable signal RSTR. <21>), the third logic clock LOGIC3_CLK may be a clock related to the generation of the first left enable signal LSTR<1>, and the fourth logic clock LOGIC4_CLK It may be a clock related to generation of the twenty-first left enable signal RSTR<21>.

According to embodiments, the first logic clock LOGIC1_CLK may be a clock related to generating the clock CLKA<1>, and the second logic clock LOGIC2_CLK may be related to generating the clock CLKB<1>. The third logic clock LOGIC3_CLK may be a clock related to the generation of the clock CLKC<1>, and the fourth logic clock LOGIC4_CLK may be a clock related to the generation of the clock CLKD<1>. .

16 is a conceptual diagram illustrating fan-out and output delay of each of source driver ICs according to embodiments of the present invention.

The first source driver IC SDRV_IC1 drives the source lines Y1-1 to Y960-1 implemented in the first area RG11, and the second source driver IC SDRV_IC2 drives the second area RG12. The implemented source lines (Y1-2 to Y960-2) are driven, and the third source driver IC (SDRV_IC3) drives the source lines (Y1-3 to Y960-3) implemented in the third region (RG13). and the fourth source driver IC (SDRV_IC4) drives the source lines (Y1-4 to Y960-4) implemented in the fourth region (RG14), and the structure and operation of each source driver IC (SDRV_IC1 to SDRV_IC4) It is assumed that the structure and operation of the first source driver IC 121 described with reference to FIGS. 3 to 15 are the same or similar.

16(a) shows fan-out according to the arrangement position of each source driver IC (SDRV_IC1 to SDRV_IC4). 16(b) shows an ideal output delay according to the arrangement position of each source driver IC (SDRV_IC1 to SDRV_IC4).

16(c) shows the actual output delay according to the arrangement position of each source driver IC (SDRV_IC1 to SDRV_IC4). For example, assuming that the first source driver IC SDRV_IC1 controls the first region RG11 by dividing it into a first sub-region SB1 and a second sub-region SB2, the plurality of first enable signals are Driving of source lines (eg, Y1-1 to Y480-1) included in the first sub-region SB1 may be controlled, and a plurality of second enable signals are applied to the second sub-region SB2. Driving of included source lines (eg, Y481-1 to Y960-1) can be controlled. As shown in (c) of FIG. 16, a delay (or output delay) between enable signals (or output signals) supplied to two adjacent source lines included in the first sub-region SB1. ) and enable signals (or output signals) supplied to two adjacent source lines included in the second sub-region SB2 (or output delays) may be differently adjusted.

Assuming that the second source driver IC (SDRV_IC2) controls the second region RG12 by dividing it into a third sub-region SB3 and a fourth sub-region SB4, the plurality of third enable signals are Driving of source lines (eg, Y1-2 to Y480-2) included in the sub-region SB3 may be controlled, and a plurality of fourth enable signals are included in the fourth sub-region SB4. Driving of source lines (eg, Y481-2 to Y960-2) may be controlled. As shown in (c) of FIG. 16, a delay (or output delay) between enable signals (or output signals) supplied to two adjacent source lines included in the third sub-region SB3. ) and the enable signals (or output signals) supplied to the two source lines included in the fourth sub-region SB4 (or output delay) may be differently adjusted.

Assuming that the third source driver IC (SDRV_IC3) controls the third region (RG13) by dividing it into a fifth sub-region (SB5) and a sixth sub-region (SB6), the plurality of fifth enable signals are Driving of source lines (eg, Y1-3 to Y480-3) included in the sub-region SB5 may be controlled, and a plurality of sixth enable signals are included in the sixth sub-region SB6. Driving of source lines (eg, Y481-3 to Y960-3) may be controlled. As shown in (c) of FIG. 16, a delay (or output delay) between enable signals (or output signals) supplied to two adjacent source lines included in the fifth sub-region SB5. ) and enable signals (or output signals) supplied to two adjacent source lines included in the sixth sub-region SB6 (or output delay) may be differently adjusted.

Assuming that the fourth source driver IC (SDRV_IC4) controls the fourth region (RG14) by dividing it into a seventh sub-region (SB7) and an eighth sub-region (SB8), the plurality of seventh enable signals are Driving of source lines (eg, Y1-4 to Y480-4) included in the sub-region SB7 may be controlled, and a plurality of eighth enable signals are included in the eighth sub-region SB8. Driving of source lines (eg, Y481-4 to Y960-4) may be controlled. As shown in (c) of FIG. 16, a delay (or output delay) between enable signals (or output signals) supplied to two source lines included in the seventh sub-region SB7 and Delays (or output delays) between enable signals (or output signals) supplied to the two source lines included in the eighth sub-region SB8 may be adjusted differently.

As described with reference to (c) of FIG. 16, each source driver IC (SDRV_IC1 to SDRV_IC4) may include two control logics and two enable signal generators.

Referring to (d) of FIG. 16, each region RG11, RG12, RG13, and RG14 may be divided into four sub-regions. In this case, each source driver IC (SDRV_IC1 to SDRV_IC4) may include 4 control logics and 4 enable signal generators.

At this time, the plurality of first enable signals generated from the first source driver IC SDRV_IC1 are source lines (eg, Y1-1 to Y240-1) included in the first sub-region of the first region RG11. , and the plurality of second enable signals generated from the first source driver IC SDRV_IC1 are source lines included in the second sub-region of the first region RG11 (eg, Y241- 1 to Y480-1), and a plurality of third enable signals generated from the first source driver IC (SDRV_IC1) are source lines included in the third sub-region of the first region RG11. (e.g., Y481-1 to Y720-1), and the plurality of fourth enable signals generated from the first source driver IC (SDRV_IC1) is the fourth sub- Driving of source lines (eg, Y721-1 to Y960-1) included in the region may be controlled.

Delay between output signals supplied to two adjacent source lines among the source lines (eg, Y1-1 to Y240-1) included in the first sub-region and the source line included in the second sub-region Delays between output signals supplied to two adjacent source lines among (eg, Y241-1 to Y480-1) may be adjusted differently.

Delay between output signals supplied to two adjacent source lines among the source lines (eg, Y241-1 to Y480-1) included in the second sub-region and the source line included in the third sub-region Delays between output signals supplied to two adjacent source lines among (eg, Y481-1 to Y720-1) may be adjusted differently.

Delay between output signals supplied to two adjacent source lines among the source lines (eg, Y481-1 to Y720-1) included in the third sub-region and the source line included in the fourth sub-region Delays between output signals supplied to two adjacent source lines among (eg, Y721-1 to Y960-1) may be adjusted differently.

Comparing FIG. 2(c) with FIG. 16(c) or FIG. 2(c) with FIG. 16(d), the first source driver IC (SDRV_IC1) according to the embodiment of the present invention Depending on the arrangement position of the source lines of each sub-region included in the region RG11, a delay between output signals supplied to two source lines included in each sub-region or an output delay may be differently adjusted. .

The operation of the first source driver IC (SDRV_IC1) is identical to or similar to that of each of the other source drivers (SDRV_IC2 to SDRV_IC4). As shown in (d) of FIG. 16, the delay between output signals supplied to two adjacent source lines included in each sub-region included in each region RG12, RG13, and RG14 is may be adjusted differently.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the attached claims.

100: display system
110: flat panel display
121 and 123: source driver
125: timing controller
121-1: Control Logic Circuit Block
210-1~210-80: Driver cell block
410: clock generator
415 Basic clock generator
420-1~420-4: control logics
425-1 to 425-4: enable signal generators

Claims (20)

In a source driver IC capable of driving a flat panel display,
a first control logic circuit generating first output signals for driving first source lines disposed in a first area of the flat panel display; and
a second control logic circuit generating second output signals for driving second source lines disposed in a second region of the flat panel display;
A first output delay between two adjacent output signals among the first output signals and a second output delay between two adjacent output signals among the second output signals are different from each other,
The first control logic circuit divides each of the input clocks at a first division ratio and generates each of the first enable signals related to the generation of each of the first output signals;
The second control logic circuit divides each of the input clocks at a second division ratio and generates each of the second enable signals related to the generation of each of the second output signals;
The first output delay is determined according to the first division ratio,
The second output delay is determined according to the second division ratio. delete According to claim 1,
The first control logic circuit sequentially outputs, as the first enable signals, first pulses selected from the pulse sequences of each of the first division clocks divided at the first division ratio;
wherein the second control logic circuit sequentially outputs, as the second enable signals, second pulses selected from pulse sequences of each of the second division clocks divided at the second division ratio. According to claim 3,
The number of the first division clocks is less than the number of the first enable signals;
The number of the second frequency division clocks is less than the number of the second enable signals. According to claim 1,
wherein the first control logic circuit generates the first enable signals in the same order as or in an opposite order to the input order of the input clocks in response to a control signal. According to claim 5,
wherein the second control logic circuit generates the second enable signals in the same order as or in an opposite order to the input order of the input clocks in response to the control signal. According to claim 1,
A third output delay between a last output signal of the first output signals and a first output signal of the second output signals is different from the second output delay. According to claim 1,
A third output delay between a last output signal of the first output signals and a first output signal of the second output signals is equal to the first output delay. A source driver IC capable of driving a flat panel display, the source driver IC comprising:
Among the source lines disposed on the flat panel display, first output signals driving the first and second source lines adjacent to each other, and second output signals driving the third and fourth source lines adjacent to each other. generate output signals;
A first output delay between the first output signals is different from a second output delay between the second output signals;
The source driver IC,
a first control logic circuit for generating each of the first enable signals related to the generation of each of the first output signals by dividing each of the input clocks at a first division ratio; and
a second control logic circuit for generating each of the second enable signals related to the generation of each of the second output signals by dividing each of the input clocks at a second division ratio;
The first output delay is determined according to the first division ratio,
The second output delay is determined according to the second division ratio. delete According to claim 9,
wherein the first control logic circuit generates the first enable signals in the same order as or in an opposite order to the input order of the input clocks in response to a control signal. According to claim 11,
wherein the second control logic circuit generates the second enable signals in the same order as or in an opposite order to the input order of the input clocks in response to the control signal. According to claim 9,
The first control logic circuit sequentially outputs, as the first enable signals, first pulses selected from the pulse sequences of each of the first division clocks divided at the first division ratio;
wherein the second control logic circuit sequentially outputs, as the second enable signals, second pulses selected from pulse sequences of each of the second division clocks divided at the second division ratio. a flat panel display including a first area and a second area; and
A source driver IC capable of driving first source lines disposed in the first region and second source lines disposed in the second region;
The source driver IC,
a first control logic circuit generating first output signals for driving the first source lines; and
A second control logic circuit generating second output signals for driving the second source lines;
A first output delay between two adjacent output signals among the first output signals and a second output delay between two adjacent output signals among the second output signals are different from each other,
The first control logic circuit divides each of the input clocks at a first division ratio to generate each of the first enable signals related to the generation of the first output signals;
The second control logic circuit generates each of the second enable signals related to the generation of each of the second output signals by dividing each of the input clocks at a second division ratio;
The first output delay is determined according to the first division ratio,
The second output delay is determined according to the second division ratio. delete According to claim 14,
The first control logic circuit sequentially outputs, as the first enable signals, first pulses selected from the pulse sequences of each of the first division clocks divided at the first division ratio;
wherein the second control logic circuit sequentially outputs, as the second enable signals, second pulses selected from the pulse sequences of each of the second division clocks divided at the second division ratio. According to claim 14,
The display system of claim 1 , wherein the first control logic circuit generates the first enable signals in the same order as or in an opposite order to the input order of the input clocks in response to a control signal. According to claim 17,
The second control logic circuit generates the second enable signals in the same order as or in the opposite order to the input order of the input clocks in response to the control signal. According to claim 14,
A third output delay between a last output signal of the first output signals and a first output signal of the second output signals is different from the second output delay. According to claim 14,
A third output delay between a last output signal of the first output signals and a first output signal of the second output signals is equal to the first output delay.

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