KR102491590B1 - Display device and method for manufacturing thereof - Google Patents

Abstract

The present invention provides a display device capable of preventing an encapsulation film from being formed on a scribing line and a manufacturing method thereof. A display device according to an embodiment of the present invention includes a substrate including a display area where pixels are disposed and a non-display area surrounding the display area, an encapsulation film covering the display area and including an inorganic film, and a non-display area. and a buffer layer contacting the edge of the inorganic film.

Description

Display device and its manufacturing method {DISPLAY DEVICE AND METHOD FOR MANUFACTURING THEREOF}

The present invention relates to a display device and a manufacturing method thereof.

As the information society develops, demands for display devices for displaying images are increasing in various forms. Accordingly, in recent years, non-light emitting display devices such as liquid crystal displays (LCDs) and plasma display panels (PDPs), organic light emitting displays (OLEDs), and quantum dot light emitting displays Various display devices such as an electroluminescence display (QLED) such as a quantum dot light emitting display (QLED) are being utilized.

Among display devices, organic light emitting displays and quantum dot light emitting displays are self-emitting, and have excellent viewing angles and contrast ratios compared to liquid crystal displays (LCDs). Power has its advantages. In addition, the organic light emitting display device can be driven at low DC voltage, has a fast response speed, and has low manufacturing cost.

An organic light emitting display device includes pixels each including a light emitting element, and a bank partitioning the pixels to define the pixels. The bank may serve as a pixel defining layer. The light emitting device includes an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. In this case, when a high potential voltage is applied to the anode electrode and a low potential voltage is applied to the cathode electrode, holes and electrons move to the light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light emitting layer to emit light.

The light emitting device has a disadvantage in that deterioration easily occurs due to external factors such as external moisture and oxygen. In order to prevent this, the organic light emitting display device forms an encapsulation film to prevent external moisture and oxygen from penetrating the light emitting element.

A quantum dot light emitting display device includes a light emitting structure. The light emitting structure includes an anode electrode, a cathode electrode facing the anode electrode, and a light emitting element positioned between the anode electrode and the cathode electrode. The light emitting device includes a hole transport layer, a light emitting layer, and an electron transport layer. A light emitting layer includes a quantum dot material.

1 is a diagram illustrating a mother substrate on which a plurality of display panels are formed. FIG. 2 is a cross-sectional view schematically illustrating an existing display device along the line I-I' shown in FIG. 1, and FIG. 3 is a cross-sectional view illustrating a method of forming an inorganic film on an existing display device.

1 to 3 , a mother substrate (MS) is a substrate for simultaneously manufacturing a plurality of display panels (PNL) for process convenience. The display panels PNL are individually separated to serve as each display device. A plurality of display panels PNL are simultaneously formed on the mother substrate MS and then separated through a cutting process or a scribing process.

In a conventional display device, an encapsulation film 30 is formed on a substrate 10 on which an organic light emitting element 20 is formed. At this time, the encapsulation film 30 includes the first inorganic film 30a, the organic film 30b, and the second inorganic film 30c, thereby preventing oxygen or moisture from permeating the light emitting layer and the electrode.

The first inorganic layer 30a and the second inorganic layer 30c are deposited on the substrate 10 using a chemical vapor deposition (CVD) technique. In the CVD technique, as shown in FIG. 3, a mask 40 is disposed on the substrate 10, and a gas containing an element constituting the first inorganic film 30a or the second inorganic film 30c is applied to the substrate ( 10) Supply above. The supplied gas undergoes a chemical reaction on the surface of the substrate 10 in an area where the mask 40 is not formed, and thus, the mask 40 forms the first inorganic film 30a or the second inorganic film 30c. It is formed on the surface of the substrate 10 in the undisposed area.

However, in the CVD technique, since the mask 40 is spaced apart from the substrate 10 at a predetermined interval, gas penetrates between the mask 40 and the substrate 10, and the substrate 10 in the region where the mask 40 is disposed A chemical reaction occurs on the surface, and accordingly, the first inorganic layer 30a or the second inorganic layer 30c may be formed even on the surface of the substrate 10 in the area where the mask 40 is disposed.

In this way, when the first inorganic film 30a or the second inorganic film 30c is formed even on the surface of the substrate 10 in the region where the mask 40 is disposed, for example, the scribing line SL, the display panel Cracks may occur in the first inorganic layer 30a or the second inorganic layer 30c during a cutting process for separating the (PNL), that is, a laser cutting process or a mechanical scribing process. Cracks may be propagated to the inside along the inorganic film due to external impact, and moisture and oxygen introduced according to the propagated cracks cause dark spots and black streaks.

Meanwhile, recently, in order to solve the limitation that the step coverage of the CVD technique is low, the first inorganic film 30a and the second inorganic film 30c are formed on a substrate (Atomic Layer Deposition) (ALD) technique. 10) The technique of depositing on top is attracting attention. The ALD technique is a method of forming a thin film by disposing a mask 40 on the substrate 10 and crossing a raw material containing ALD metal with a reaction gas. This ALD technique has superior adsorption power compared to the CVD technique, so it has high thin film coating properties, and it is advantageous to form a very thin thin film because the thin film thickness can be adjusted.

However, since the ALD technique has excellent adsorption power as described above, it can be formed long into the region where the mask 40 is disposed on the substrate 10. Accordingly, compared to the CVD technique, the first inorganic film 30a or There is a problem that the possibility that the second inorganic film 30c is formed up to the scribing line SL is high.

In order to solve the above problems, the mask 40 is disposed close to the light emitting device 20 to reduce the separation distance between the substrates 10, and the first inorganic film 30a or the second inorganic film 30c is the mask ( 40) may be considered as a method for preventing penetration into the disposed region. However, the method may damage or deform the organic light emitting element 20 while disposing the mask 40, causing black spots to occur.

Meanwhile, a plurality of metal lines are disposed on the substrate 10. For example, the metal lines disposed in the non-display area are covered only with a thin protective film during the CVD process. When a high voltage is momentarily applied in the CVD process, the protective film protecting the metal line may be torn off by the high voltage, and another problem is that static electricity is generated between the metal lines in the non-display area and the mask 40. there is. Due to static electricity, the display panel does not operate properly due to damage to the metal line, and the mask 40 may also become unusable.

The present invention provides a display device capable of preventing an encapsulation film from being formed in an unintended area, for example, a scribing line, and preventing static electricity from being generated between a mask and a metal line, and a manufacturing method thereof.

A display device according to an exemplary embodiment of the present invention includes a substrate including a display area where pixels are disposed and a non-display area surrounding the display area, an encapsulation layer covering the display area and including an inorganic film, and a non-display area. It is spaced apart from the display area and includes a buffer layer in contact with the edge of the inorganic film.

A method of manufacturing a display device according to another embodiment of the present invention includes forming pixels in a display area on a substrate and forming a buffer layer in a non-display area, disposing a mask on the buffer layer, and covering the display area. and removing the mask after forming the inorganic film.

According to the present invention, a buffer layer is formed between the non-display area and the scribing line, and a mask is disposed on the buffer layer during deposition of the inorganic film to prevent formation of the inorganic film on the scribing line, and thus, during the scribing process The yield and reliability of the display device may be improved by preventing cracks from occurring in the inorganic film.

In addition, the present invention can improve the lifespan and reliability of the display device by forming a buffer layer in the non-display area to minimize penetration of moisture and oxygen from the side of the display device.

Further, in the present invention, damage to the dam can be minimized when a mask is disposed on the buffer layer by forming the buffer layer higher than the dam. Accordingly, propagation of moisture and oxygen to the organic film through the damaged dam can be prevented.

In addition, the present invention can minimize the stress increase in the non-display area due to the formation of the buffer layer 130 by forming the buffer layer with a plurality of island-type patterns.

In addition, the present invention can minimize damage to the electrode when disposing a mask on the buffer layer by forming the buffer layer so as not to overlap with the electrode. Accordingly, defects caused by damaged electrodes can be prevented.

Further, according to the present invention, the first inorganic layer and the second inorganic layer may be formed to have different areas by forming a first buffer layer and a second buffer layer, and thus, the second inorganic layer completely covers the first inorganic layer and the organic layer. It can be covered to prevent penetration of oxygen and moisture.

Further, in the present invention, since the buffer layer is formed of the same material as at least one of the planarization film and the bank, there is no need to add a separate manufacturing process.

In addition, in the present invention, by forming a buffer layer on a power auxiliary line that supplies power voltage to a power line, even if a large amount of charge is momentarily gathered at the edge of the mask in the process of depositing the first inorganic film or the second inorganic film, the buffer layer The generation of static electricity between the mask and the auxiliary power line can be prevented.

In addition, the present invention can prevent moisture and oxygen introduced from the outside from being propagated to the inside by forming at least one groove exposing the protective film in the buffer layer.

In addition, the present invention can increase the cross-sectional area of the power auxiliary line by additionally forming the second power auxiliary line on the first power auxiliary line using the buffer layer, thereby reducing the resistance to stably supply the power voltage. there is.

The effects obtainable in the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below. .

1 is a diagram illustrating a mother substrate on which a plurality of display panels are formed.
FIG. 2 is a cross-sectional view schematically illustrating a conventional display device along the line I-I' shown in FIG. 1 .
3 is a cross-sectional view to explain a method of forming an inorganic film on a conventional display device.
4 is a perspective view showing a display device according to an exemplary embodiment of the present invention.
FIG. 5 is a plan view illustrating a first substrate, a source drive IC, a flexible film, a circuit board, and a timing controller of FIG. 4 .
6 is a plan view schematically showing a first substrate according to a first embodiment of the present invention.
FIG. 7 is a cross-sectional view schematically illustrating a cross section along the line II′ shown in FIG. 6 .
FIG. 8 is a cross-sectional view schematically illustrating a cross-section along line II-II′ shown in FIG. 6 .
FIG. 9 is a cross-sectional view schematically illustrating a cross section along line III-III′ shown in FIG. 6 .
10 is a cross-sectional view showing an example in which a mask is disposed on the buffer layer of FIG. 8 .
11 is a plan view schematically showing a first substrate according to a second embodiment of the present invention.
FIG. 12 is a cross-sectional view schematically illustrating a cross section along line II-II' shown in FIG. 11 .
13 is a plan view schematically showing a first substrate according to a third embodiment of the present invention.
FIG. 14 is a cross-sectional view schematically illustrating a cross section along line II-II′ shown in FIG. 13 .
15 is a plan view schematically showing a first substrate according to a fourth embodiment of the present invention.
FIG. 16 is a cross-sectional view schematically illustrating a cross-section along line II-II′ shown in FIG. 14 .
17 is a plan view schematically showing a first substrate according to a fifth embodiment of the present invention.
18 is a plan view schematically showing a first substrate according to a sixth embodiment of the present invention.
FIG. 19 is a cross-sectional view schematically illustrating a cross section along line III-III′ shown in FIG. 18 .
20 is a cross-sectional view showing an example in which a mask is disposed on the buffer layer of FIG. 19 .
21 is a cross-sectional view schematically illustrating a modified embodiment of FIG. 19 .
22 is a plan view schematically showing a first substrate according to a seventh embodiment of the present invention.
FIG. 23 is a cross-sectional view schematically illustrating a cross section along line III-III′ shown in FIG. 22 .
24 is a cross-sectional view schematically illustrating a modified embodiment of FIG. 23 .
25 is a flowchart for explaining a method of manufacturing a display device according to a first embodiment of the present invention.
26A to 26H are cross-sectional views for explaining a method of manufacturing a display device according to a first embodiment of the present invention.
27 is a flowchart for explaining a method of manufacturing a display device according to a second embodiment of the present invention.
28A to 28L are cross-sectional views for explaining a method of manufacturing a display device according to a second embodiment of the present invention.
29 is a plan view schematically showing a first substrate according to an eighth embodiment of the present invention.
FIG. 30 is a cross-sectional view schematically illustrating a cross section along line III-III' shown in FIG. 29 .
FIG. 31 is a cross-sectional view schematically illustrating a cross section along line II-II' shown in FIG. 29 .

Advantages and features of the present invention, and methods for achieving them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the present embodiments make the disclosure of the present invention complete, and those skilled in the art in the art to which the present invention belongs It is provided to fully inform the person of the scope of the invention, and the invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiment of the present invention are exemplary, the present invention is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is made upright, and may be broader within the range in which the configuration of the present invention can function functionally. It can mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It may mean a combination of all items that can be presented from one or more.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in an association relationship. may be

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a perspective view showing a display device according to an exemplary embodiment of the present invention. FIG. 5 is a plan view illustrating a first substrate, a source drive IC, a flexible film, a circuit board, and a timing controller of FIG. 4 . Hereinafter, the display device according to an exemplary embodiment of the present invention has been mainly described as an organic light emitting display (OLED), but is not limited thereto. That is, the display device according to an embodiment of the present invention includes not only an organic light emitting display device, but also a liquid crystal display device, an electroluminescence display device, and a quantum dot light emitting diode display device. And it may be implemented as any one of an electrophoresis display.

4 and 5, a display device 100 according to an embodiment of the present invention includes a display panel 110, a source drive integrated circuit (hereinafter referred to as "IC") 140, and a flexible film. 150, a circuit board 160, and a timing controller 170.

The display panel 110 includes a first substrate 111 and a second substrate 112 . The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film or a glass substrate, but is not limited thereto. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film, but is not limited thereto.

Gate lines, data lines, and pixels are formed on one surface of the first substrate 111 facing the second substrate 112 . Pixels are provided in an area defined by a cross structure of gate lines and data lines.

Each of the pixels may include a light emitting device including a thin film transistor, a first electrode, a light emitting layer, and a second electrode. Each of the pixels uses a thin film transistor to supply a predetermined current to the light emitting device according to the data voltage of the data line when a gate signal is input from the gate line. Due to this, the light emitting element of each of the pixels can emit light with a predetermined brightness according to a predetermined current. The structure of each of the pixels will be described later in conjunction with FIGS. 6 and 7 .

As shown in FIG. 5 , the display panel 110 may be divided into a display area DA in which pixels are formed to display an image and a non-display area NDA in which an image is not displayed. Gate lines, data lines, and pixels may be formed in the display area DA. A gate driver and pads may be formed in the non-display area NDA.

The gate driver supplies gate signals to the gate lines according to the gate control signal input from the timing controller 170 . The gate driver may be formed in the non-display area DA outside one or both sides of the display area DA of the display panel 110 in a gate driver in panel (GIP) method. Alternatively, the gate driver may be manufactured as a driving chip, mounted on a flexible film, and attached to the non-display area DA on one side or both sides of the display area DA of the display panel 110 by a tape automated bonding (TAB) method. may be

The source drive IC 140 receives digital video data and a source control signal from the timing controller 170. The source drive IC 140 converts digital video data into analog data voltages according to a source control signal and supplies them to data lines. When the source drive IC 140 is manufactured as a driving chip, it may be mounted on the flexible film 150 in a chip on film (COF) or chip on plastic (COP) method.

Pads such as data pads may be formed in the non-display area NDA of the display panel 110 . Wires connecting pads and the source drive IC 140 and wires connecting pads and wires of the circuit board 160 may be formed on the flexible film 150 . The flexible film 150 is attached to the pads using an anisotropic conducting film, so that the pads and wires of the flexible film 150 can be connected.

The circuit board 160 may be attached to the flexible films 150 . A plurality of circuits implemented as driving chips may be mounted on the circuit board 160 . For example, the timing controller 170 may be mounted on the circuit board 160 . The circuit board 160 may be a printed circuit board or a flexible printed circuit board.

The timing controller 170 receives digital video data and timing signals from an external system board through a cable of the circuit board 160 . The timing controller 170 generates a gate control signal for controlling the operation timing of the gate driver and a source control signal for controlling the source drive ICs 140 based on the timing signal. The timing controller 170 supplies a gate control signal to the gate driver and supplies a source control signal to the source drive ICs 140 .

No. 1 Example

6 is a plan view schematically showing a first substrate according to a first embodiment of the present invention.

Referring to FIG. 6 , the first substrate 111 is divided into a display area DA and a non-display area NDA, and in the non-display area NDA, a pad area PA in which pads are formed, and a dam 120 And a buffer layer 130 may be formed.

Pixels P displaying images are formed in the display area DA. Each of the pixels may include a light emitting device including a thin film transistor, a first electrode, a light emitting layer, and a second electrode. Each of the pixels uses a thin film transistor to supply a predetermined current to the light emitting device according to the data voltage of the data line when a gate signal is input from the gate line. Due to this, the light emitting element of each of the pixels can emit light with a predetermined brightness according to a predetermined current.

Hereinafter, the structure of the pixel P of the display area DA according to the exemplary embodiments will be described in detail with reference to FIG. 7 .

7 is a cross-sectional view illustrating an example of a pixel of the display area of FIG. 6 .

Referring to FIG. 7 , thin film transistors 210 and capacitors 220 are formed on one surface of the first substrate 111 facing the second substrate 112 .

A buffer film may be formed on the first substrate 111 to protect the thin film transistors 210 from moisture penetrating through the first substrate 111 , which is vulnerable to moisture permeation.

Each of the thin film transistors 210 includes an active layer 211 , a gate electrode 212 , a source electrode 213 and a drain electrode 214 . In FIG. 7 , it is illustrated that the gate electrodes 212 of the thin film transistors 210 are formed in a top gate (top gate) method positioned above the active layer 211, but it should be noted that the present invention is not limited thereto. That is, the thin film transistor 210 is a bottom gate (bottom gate) method in which the gate electrode 212 is positioned below the active layer 211 or the gate electrode 212 is located above and below the active layer 211. It may be formed in a double gate method located in both.

An active layer 211 is formed on the buffer layer of the first substrate 111 . The active layer 211 may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. A light blocking layer may be formed on the first substrate 111 to block external light incident on the active layer 211 .

A gate insulating layer 230 may be formed on the active layer 211 . The gate insulating layer 230 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

A gate electrode 212 may be formed on the gate insulating layer 230 . The gate electrode 212 is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or these It may be a single layer or multi-layer made of an alloy of, but is not limited thereto.

An interlayer insulating layer 240 may be formed on the gate electrode 212 . The interlayer insulating layer 240 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

A source electrode 213 and a drain electrode 214 may be formed on the interlayer insulating layer 240 . Each of the source electrode 213 and the drain electrode 214 may be connected to the active layer 211 through contact holes CH1 and CH2 penetrating the gate insulating layer 230 and the interlayer insulating layer 240 . The source electrode 213 and the drain electrode 214 are composed of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper ( Cu) may be a single layer or a multi-layer made of any one or an alloy thereof, but is not limited thereto.

Each of the capacitors 220 includes a lower electrode 221 and an upper electrode 222 . The lower electrode 221 is formed on the gate insulating layer 230 and may be formed of the same material as the gate electrode 212 . The upper electrode 222 is formed on the interlayer insulating layer 240 and may be formed of the same material as the source electrode 223 and the drain electrode 224 .

A protective layer 250 may be formed on the thin film transistor 210 and the capacitor 220 . The protective layer 250 may serve as an insulating layer. The protective layer 250 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

A planarization layer 260 may be formed on the passivation layer 250 to flatten a level difference between the thin film transistor 210 and the capacitor 220 . The planarization layer 260 may be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. there is.

A light emitting element 280 and a bank 284 are formed on the planarization film 260 . The light emitting element 280 includes a first electrode 282 , a light emitting layer 283 , and a second electrode 281 . The first electrode 282 may be a cathode electrode, and the second electrode 281 may be an anode electrode. An area in which the first electrode 282 , the light emitting layer 283 , and the second electrode 281 are stacked may be defined as the light emitting part EA.

The second electrode 281 may be formed on the planarization layer 260 . The second electrode 281 is connected to the drain gap 214 of the thin film transistor 210 through the contact hole CH3 penetrating the passivation layer 250 and the planarization layer 260 . The second electrode 281 may include a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO/APC /ITO) may be formed of a metal material with high reflectivity. An APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

The bank 284 may be formed to cover the edge of the second electrode 281 on the planarization layer 260 to partition the light emitting units EA. The bank 284 may be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. .

A light emitting layer 283 is formed on the second electrode 281 and the bank 284 . The light emitting layer 283 may include a hole transporting layer, at least one light emitting layer, and an electron transporting layer. In this case, when a voltage is applied to the second electrode 281 and the first electrode 282, holes and electrons move to the light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light emitting layer to emit light.

The light emitting layer 283 may be formed of a white light emitting layer that emits white light. In this case, it may be formed to cover the second electrode 281 and the bank 284 . In this case, a color filter may be formed on the second substrate 112 .

Alternatively, the light emitting layer 283 may include a red light emitting layer emitting red light, a green light emitting layer emitting green light, or a blue light emitting layer emitting blue light. In this case, the light emitting layer 283 may be formed in an area corresponding to the second electrode 281 , and a color filter may not be formed on the second substrate 112 .

The first electrode 282 is formed on the light emitting layer 283 . When the organic light emitting display device is formed with a top emission structure, the first electrode 282 is a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or magnesium (Mg). ), silver (Ag), or a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). A capping layer may be formed on the first electrode 282 .

An encapsulation film 290 is formed on the light emitting element 280 . The encapsulation film 290 serves to prevent oxygen or moisture from penetrating into the light emitting layer 283 and the first electrode 282 . To this end, the encapsulation layer 290 may include at least one inorganic layer and at least one organic layer.

For example, the encapsulation film 290 may include a first inorganic film 291 , an organic film 292 , and a second inorganic film 293 . In this case, the first inorganic layer 291 is formed to cover the first electrode 282 . An organic layer 292 is formed on the first inorganic layer 291 . The organic layer 292 is preferably formed to a thickness sufficient to prevent particles from penetrating the first inorganic layer 291 and being injected into the light emitting layer 283 and the first electrode 282 . The second inorganic layer 293 is formed to cover the organic layer 292 .

First to third color filters and a black matrix may be formed on the encapsulation film 290 . A red color filter 323 may be formed in the red light emitting part, a blue color filter 322 may be formed in the blue light emitting part, and a green color filter 321 may be formed in the green light emitting part.

The encapsulation film 290 of the first substrate 111 and the color filters of the second substrate 112 are bonded using the adhesive layer 330, and thus the first substrate 111 and the second substrate 112 are bonded together. It can be. The adhesive layer 330 may be a transparent adhesive resin.

Referring again to FIG. 6 , the pad area PA may be disposed on one edge of the first substrate 111 . The pad area PA includes a plurality of pads, and the plurality of pads may be electrically connected to wires of the flexible film 150 by using an anisotropic conducting film.

The dam 120 is disposed to surround the display area DA and blocks the flow of the organic layer 292 . In addition, the dam 120 is disposed between the display area DA and the pad area PA to prevent the organic film 292 constituting the encapsulation film 290 of the pixel P from invading the pad area PA. The flow of the organic layer 292 is blocked.

The buffer layer 130 is spaced apart from the display area DA in the non-display area NDA and includes the first inorganic film 291 or the second inorganic film 293 constituting the encapsulation film 290 of the pixel P. come into contact with

Hereinafter, the dam and the buffer layer according to the first embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10 .

FIG. 8 is a cross-sectional view schematically showing a cross-section along line II-II' shown in FIG. 6, and FIG. 9 is a cross-sectional view schematically showing a cross-section along line III-III' shown in FIG. 10 is a cross-sectional view showing an example in which a mask is disposed on the buffer layer of FIG. 8 .

8 to 10 illustrate the TFT substrate 200 including the thin film transistors 210 and the capacitor 220, omitting specific configurations of the thin film transistors 210 and the capacitor 220 for convenience of explanation. The TFT substrate 200 may include the first substrate 111 shown in FIG. 8 , a gate insulating layer 230 and an interlayer insulating layer 240 .

The display device illustrated in FIG. 8 includes an encapsulation film 290 formed on a first substrate 111 , a dam 120 and a buffer layer 130 . In this case, the first substrate 111 includes a display area DA in which pixels P are formed and a pad area PA in which a plurality of pads are formed.

The encapsulation film 290 is formed to cover the light emitting element 280 formed in the display area DA and prevents oxygen or moisture from penetrating the light emitting element 280 . In this case, the encapsulation film 290 includes at least one inorganic film and at least one organic film. For example, the encapsulation film 290 may include a first inorganic film 291 , an organic film 292 , and a second inorganic film 293 . In this case, the first inorganic layer 291 is formed to cover the first electrode 282 . An organic layer 292 is formed on the first inorganic layer 291 , and a second inorganic layer 293 is formed to cover the organic layer 292 .

Each of the first and second inorganic layers 291 and 293 may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first and second inorganic layers 291 and 293 may be deposited using a chemical vapor deposition (CVD) technique or an atomic layer deposition (ALD) technique, but are not limited thereto.

The organic layer 292 may be transparent to pass light emitted from the light emitting layer 283 . The organic layer 292 is an organic material capable of passing 99% or more of the light emitted from the light emitting layer 283, for example, an acrylic resin, an epoxy resin, a phenolic resin, or a polyamide resin. (polyamide resin) or polyimide resin. The organic layer 292 may be formed by vapor deposition using an organic material, printing, or slit coating, but is not limited thereto, and the organic layer 292 may be formed using an ink-jet jet) process.

The dam 120 is formed to surround the periphery of the display area DA and blocks the flow of the organic layer 292 constituting the encapsulation layer 290 . Since the organic layer 292 constituting the encapsulation layer 290 has excellent covering performance but poor barrier performance, it must be sealed by the second inorganic layer 293 . However, when the organic layer 292 overflows outside the region where the organic layer 292 is to be formed, moisture, oxygen, and the like penetrate through the exposed organic layer 292 without being sealed by the second inorganic layer 293 . To prevent this, the organic layer 292 may be prevented from being exposed to the outside of the display device by blocking the flow of the organic layer 292 using the dam 120 .

In addition, the dam 120 is disposed between the display area DA and the pad area PA to prevent the organic film 292 constituting the encapsulation film 290 from invading the pad area PA. block the flow of When the organic film 292 constituting the encapsulation film 290 invades the pad area PA, electrical contact is not properly made in the pad due to the organic film 292 , and driving failure or lighting inspection failure may occur. To prevent this, the flow of the organic layer 292 constituting the encapsulation layer 290 is blocked using the dam 120, thereby preventing the organic layer 292 from invading the pad area PA. .

8 to 10 show one dam 120, but are not limited thereto. In another embodiment, the dam 120 may include a first dam and a second dam disposed in the non-display area and spaced apart from the first dam. The second dam blocks the flow of the organic film 292 overflowing to the outside of the first dam.

The dam 120 may be formed at the same time as at least one of the planarization film 260 and the bank 284 of the pixel P, and may be made of the same material as at least one of the planarization film 260 and the bank 284. there is. In this case, the dam 120 is made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can be formed

The buffer layer 130 is spaced apart from the display area DA in the non-display area NDA and contacts at least one of the first inorganic layer 291 and the second inorganic layer 293 . More specifically, the buffer layer 130 is formed between the dam 120 and the scribing line SL in the non-display area NDA to deposit the first inorganic layer 291 or the second inorganic layer 293. During the process, the mask 140 is supported so that the mask 140 maintains a predetermined distance from the TFT substrate 200 . To this end, the mask 140 is disposed on the buffer layer 130 so as to contact the buffer layer 130 .

When the first inorganic layer 291 or the second inorganic layer 293 is deposited after the mask 140 is disposed on the buffer layer 130, the first inorganic layer 291 or the second inorganic layer 293 It is formed in an area other than the area where the mask 140 is disposed. At this time, since no space is formed between the mask 140 and the TFT substrate 200 by the buffer layer 130, the first inorganic film 291 or the second inorganic film 293 enters the area where the mask 140 is disposed. penetration is blocked. As a result, the present invention arranges the buffer layer 130 between the dam 120 and the scribing line SL and places the mask 140 in contact with the buffer layer 130, thereby forming the first inorganic film 291 Alternatively, it is possible to prevent the second inorganic layer 293 from being formed outside the buffer layer 130, for example, on the scribing line SL.

Meanwhile, as shown in FIG. 9 , the buffer layer 130 is formed between the dam 120 and the pad area PA so that the first inorganic film 291 or the second inorganic film 293 is in the pad area PA. formation can be prevented. Through this, it is possible to prevent driving failure or lighting inspection failure from occurring due to electrical contact not being made in the pad part by the first inorganic layer 291 or the second inorganic layer 293 .

Also, the buffer layer 130 contacts an edge of at least one of the first inorganic layer 291 and the second inorganic layer 292 deposited as described above. 8 shows that the buffer layer 130 contacts the edges of the first inorganic film 291 and the edges of the second inorganic film 293, but is not limited thereto.

In another embodiment, the buffer layer 130 may contact only the edge of the second inorganic layer 293 . More specifically, the first inorganic layer 291 and the second inorganic layer 293 may be deposited using different masks. The first inorganic layer 291 may be deposited using a first mask, and the second inorganic layer 293 may be deposited using a second mask. In this case, the first mask may have a larger area than the second mask and may be disposed close to the light emitting device 280 so that the first inorganic layer 291 may be smaller than the second inorganic layer 293 . Accordingly, the first inorganic layer 291 may have a smaller area than the second inorganic layer 293 . The second inorganic layer 293 may completely cover the first inorganic layer 291 and the organic layer 292 formed on the first inorganic layer 291 .

In another embodiment, the buffer layer 130 may contact only the edge of the first inorganic layer 291 . More specifically, the first inorganic layer 291 and the second inorganic layer 293 may be deposited using different deposition techniques. Since the light emitting device 280 is not formed flat, the first inorganic layer 291 may be deposited using an ALD technique having high step coverage. The first inorganic layer 291 may be deposited using an ALD technique after disposing the mask 140 on the buffer layer 130 so as to contact the buffer layer 130 . Accordingly, the buffer layer 130 may contact the edge of the first inorganic layer 291 . On the other hand, since the second inorganic layer 293 is formed on the relatively flat organic layer 292, it may be deposited using a CVD technique. The second inorganic layer 293 may be deposited on the buffer layer 130 using a CVD technique after disposing the mask 140 to be spaced apart from the buffer layer 130 . Accordingly, the second inorganic layer 293 may completely cover the first inorganic layer 291 and the organic layer 292 .

Meanwhile, the height H2 of the buffer layer 130 may be equal to or greater than the height H1 of the dam 120 . When the height H2 of the buffer layer 130 is smaller than the height H1 of the dam 120, a mask is formed on the buffer layer 130 in the process of depositing the first inorganic layer 291 or the second inorganic layer 293. When disposing 140, the dam 120 may be damaged by the mask 140. Also, when the organic film 292 comes into contact with the damaged dam 120, oxygen or moisture penetrating into the damaged dam 120 is absorbed into the organic film 292 and penetrates into the light emitting element 280, so that the light emitting element 280 deterioration may occur.

Preferably, the height H2 of the buffer layer 130 is formed to be greater than the height H1 of the dam 120 as shown in FIG. 8, so that when the mask 140 is disposed on the buffer layer 130, the dam (120) can reduce damage, but is not limited thereto. If the mask 140 is precisely controlled, the possibility that the dam 120 is damaged by the mask 140 will be reduced. In this case, the need to form the height H2 of the buffer layer 130 greater than the height H1 of the dam 120 may also be reduced.

The buffer layer 130 may be formed at the same time as at least one of the planarization film 260 and the bank 284 of the pixel P, and may be made of the same material as at least one of the planarization film 260 and the bank 284. there is. In this case, the buffer layer 130 is made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can be formed

2nd Example

FIG. 11 is a plan view schematically showing a first substrate according to a second embodiment of the present invention, and FIG. 12 is a cross-sectional view schematically showing a cross section taken along line II-II′ shown in FIG. 11 .

11 and 12 illustrate the TFT substrate 200 including the thin film transistors 210 and the capacitor 220, omitting specific configurations of the thin film transistors 210 and the capacitor 220 for convenience of description. The TFT substrate 200 may include the first substrate 111 shown in FIG. 7 , a gate insulating layer 230 and an interlayer insulating layer 240 .

Referring to FIG. 11 , the first substrate 111 is divided into a display area DA and a non-display area NDA, and in the non-display area NDA, a pad area PA where pads are formed, and a dam 120 And a buffer layer 130 may be formed. At this time, the buffer layer 130 shown in FIGS. 11 and 12 is different from the first substrate shown in FIGS. 6 to 10 in that it is disposed between the dam 120 and the display area DA. Hereinafter, the same contents as those of FIGS. 6 to 10 will be omitted.

The dam 120 is formed to surround the periphery of the buffer layer 130 in the non-display area NDA and blocks the flow of the organic layer 292 overflowing to the periphery of the buffer layer 130 . In addition, the dam 120 is disposed between the buffer layer 130 and the pad area PA to block the flow of the organic film 292 so that the organic film 292 does not invade the pad area PA.

11 and 12 show one dam 120, but is not limited thereto. In another embodiment, the dam 120 may include a first dam and a second dam disposed in the non-display area and spaced apart from the first dam. The second dam may block the flow of the organic layer 292 overflowing to the outside of the first dam.

The buffer layer 130 is formed in the non-display area NDA and contacts at least one of the first inorganic layer 291 and the second inorganic layer 293 . More specifically, the buffer layer 130 is formed between the dam 120 and the display area DA in the non-display area NDA to deposit the first inorganic film 291 or the second inorganic film 293. In the process, the mask 140 is supported so that the mask 140 maintains a predetermined distance from the TFT substrate 200 . To this end, the mask 140 is disposed on the buffer layer 130 so as to contact the buffer layer 130 .

When the first inorganic layer 291 or the second inorganic layer 293 is deposited after the mask 140 is disposed on the buffer layer 130, the first inorganic layer 291 or the second inorganic layer 293 It is formed in an area other than the area where the mask 140 is disposed. At this time, since no space is formed between the mask 140 and the TFT substrate 200 by the buffer layer 130, the first inorganic film 291 or the second inorganic film 293 enters the area where the mask 140 is disposed. penetration is blocked. As a result, the present invention disposes the buffer layer 130 between the dam 120 and the display area DA, and disposes the mask 140 to contact the buffer layer 130, so that the first inorganic film 291 or Formation of the second inorganic layer 293 on the outside of the buffer layer 130, eg, on the scribing line SL, may be prevented.

Also, the buffer layer 130 contacts an edge of at least one of the first inorganic layer 291 and the second inorganic layer 292 deposited as described above. 13 shows that the buffer layer 130 contacts the edges of the first inorganic film 291 and the edges of the second inorganic film 293, but is not limited thereto.

In another embodiment, the buffer layer 130 may contact only the edge of the first inorganic layer 291 . More specifically, the first inorganic layer 291 and the second inorganic layer 293 may be deposited using different deposition techniques and different masks. Since the light emitting device 280 is not formed flat, the first inorganic layer 291 may be deposited using an ALD technique having high step coverage. The first inorganic layer 291 may be deposited using an ALD technique after disposing a first mask on the buffer layer 130 so as to contact the buffer layer 130 . Accordingly, the buffer layer 130 may contact the edge of the first inorganic layer 291 . On the other hand, since the second inorganic layer 293 is formed on the relatively flat organic layer 292, it may be deposited using a CVD technique. The second inorganic layer 293 may be deposited on the TFT substrate 200 using a CVD technique after disposing a second mask so as not to overlap the buffer layer 130 and the dam 120 . In this case, the second mask may have a smaller formation area than the first mask but a larger open area so that the second inorganic layer 293 may be formed wider than the first inorganic layer 291 . Accordingly, the second inorganic layer 293 may completely cover the first inorganic layer 291 and the organic layer 292 formed on the first inorganic layer 291 .

Meanwhile, the height H2 of the buffer layer 130 may be greater than the height H1 of the dam 120 . When the height H2 of the buffer layer 130 is equal to or smaller than the height H1 of the dam 120, the first inorganic layer 291 or the second inorganic layer 293 is deposited on the buffer layer 130 When the mask 140 is placed on the dam 120, the mask 140 may contact the dam 120 and damage the dam 120. Also, when the organic film 292 comes into contact with the damaged dam 120, oxygen or moisture penetrating into the damaged dam 120 is absorbed into the organic film 292 and penetrates into the light emitting element 280, so that the light emitting element 280 deterioration may occur.

In the process of depositing the first inorganic film 291 or the second inorganic film 293 by forming the height H2 of the buffer layer 130 greater than the height H1 of the dam 120, the buffer layer 130 Damage to the dam 120 may be reduced when the mask 140 is placed thereon, but is not limited thereto.

In addition, the buffer layer 130 is formed so as not to overlap the first electrode 282 . If the buffer layer 130 is formed to overlap the first electrode 282, the mask 140 may be disposed on the buffer layer 130 in the process of depositing the first inorganic layer 291 or the second inorganic layer 293. When the mask 140 moves, the first electrode 282 may be damaged. The damaged second electrode may cause pixels to not properly drive and black spots to occur.

In the process of depositing the first inorganic film 291 or the second inorganic film 293 by forming the buffer layer 130 so as not to overlap with the first electrode 282, the mask 140 is formed on the buffer layer 130. When disposing the , damage to the first electrode 282 may be reduced.

3rd Example

FIG. 13 is a plan view schematically showing a first substrate according to a third embodiment of the present invention, and FIG. 14 is a cross-sectional view schematically showing a cross section taken along line II-II′ shown in FIG. 13 .

13 and 14 illustrate the TFT substrate 200 including the thin film transistors 210 and the capacitor 220, omitting specific configurations of the thin film transistors 210 and the capacitor 220 for convenience of description. The TFT substrate 200 may include the first substrate 111 shown in FIG. 8 , a gate insulating layer 230 and an interlayer insulating layer 240 .

13 and 14, the first substrate 111 is divided into a display area DA and a non-display area NDA, and in the non-display area NDA, a pad area PA in which pads are formed, a dam (120), a first buffer layer 132 and a second buffer layer 134 may be formed. At this time, the buffer layer 130 shown in FIGS. 13 and 14 is different from the first substrate shown in FIGS. 6 to 10 in that it includes a first buffer layer 132 and a second buffer layer 134 . Hereinafter, the same contents as those of FIGS. 6 to 10 will be omitted.

The dam 120 is formed to surround the periphery of the first buffer layer 132 in the non-display area NDA and blocks the flow of the organic layer 292 overflowing to the periphery of the first buffer layer 132 . In addition, the dam 120 is disposed between the first buffer layer 132 and the pad area PA to block the flow of the organic film 292 so that the organic film 292 does not invade the pad area PA.

13 and 14 show one dam 120, but are not limited thereto. In another embodiment, the dam 120 may include a first dam and a second dam disposed in the non-display area and spaced apart from the first dam. The second dam blocks the flow of the organic film 292 overflowing to the outside of the first dam.

The first buffer layer 132 is formed in the non-display area NDA and contacts the edge of the first inorganic layer 291 . More specifically, the first buffer layer 132 is formed between the dam 120 and the display area DA in the non-display area NDA, and the first mask is used in the process of depositing the first inorganic layer 291. The first mask is supported to maintain a predetermined distance from the TFT substrate 200 . To this end, the first mask is disposed on the first buffer layer 132 to contact the first buffer layer 132 .

When the first inorganic layer 291 is deposited after disposing the first mask on the first buffer layer 132, the first inorganic layer 291 is formed in an area other than the area where the first mask is disposed. At this time, since no space is formed between the first mask and the TFT substrate 200 by the first buffer layer 132, the first inorganic layer 291 is blocked from penetrating into the region where the first mask is disposed. As a result, the present invention arranges the first buffer layer 132 between the dam 120 and the display area DA and arranges the first mask to contact the first buffer layer 132, so that the first inorganic film 291 ) may be prevented from being formed outside the first buffer layer 132, for example, on the scribing line SL.

In addition, the first buffer layer 132 is formed so as not to overlap the first electrode 282 . If the first buffer layer 132 is formed to overlap the first electrode 282, when the first mask is disposed on the first buffer layer 132 in the process of depositing the first inorganic film 291, the first mask While moving, the first electrode 282 may be damaged. The damaged second electrode may cause pixels to not properly drive and black spots to occur.

In the present invention, the first buffer layer 132 is formed so as not to overlap with the first electrode 282, so that when the first mask is disposed on the first buffer layer 132 in the process of depositing the first inorganic film 291, Damage to the first electrode 282 can be reduced.

The second buffer layer 134 is formed in the non-display area NDA and contacts the edge of the second inorganic layer 293 . More specifically, the second buffer layer 134 is formed between the dam 120 and the scribing line SL in the non-display area NDA to form a second mask in the process of depositing the second inorganic layer 293. The second mask is supported so as to maintain a predetermined distance from the TFT substrate 200 . To this end, the second mask is disposed on the second buffer layer 134 to contact the second buffer layer 134 .

When the second inorganic layer 293 is deposited after disposing the second mask on the second buffer layer 134, the second inorganic layer 293 is formed in an area other than the area where the second mask is disposed. At this time, since no space is formed between the second mask and the TFT substrate 200 by the second buffer layer 134, the second inorganic layer 293 is blocked from penetrating into the region where the second mask is disposed. As a result, the present invention disposes the second buffer layer 134 between the dam 120 and the scribing line SL and disposes the second mask to contact the second buffer layer 134, so that the second inorganic film 293 may be prevented from being formed outside the second buffer layer 134, for example, on the scribing line SL.

Meanwhile, according to the present invention, the first inorganic film 291 and the second inorganic film 293 may have different areas by forming the first buffer layer 132 and the second buffer layer 134 . More specifically, the second inorganic film 293 is formed by forming the first buffer layer 132 between the dam 120 and the display area DA, and forming the second buffer layer 132 outside the dam 120. It is possible to completely cover the first inorganic layer 291 and the organic layer 292 in which flow is blocked by the dam 120 to prevent penetration of oxygen and moisture. In this case, the first inorganic layer 291 and the second inorganic layer 292 may be formed using the same deposition technique or may be formed using different deposition techniques.

Meanwhile, the height H2 of the first buffer layer 132 may be greater than the height H1 of the dam 120 . . When the height H2 of the first buffer layer 132 is equal to or smaller than the height H1 of the dam 120, a first mask is formed on the first buffer layer 132 in the process of depositing the first inorganic film 291. When disposing the dam 120 may be damaged by the first mask. Also, the height H3 of the second buffer layer 134 may be equal to or greater than the height H1 of the dam 120 . When the height H3 of the second buffer layer 134 is smaller than the height H1 of the dam 120, a second mask is disposed on the second buffer layer 134 in the process of depositing the second inorganic film 292. When doing so, the dam 120 may be damaged by the second mask. Also, when the organic film 292 comes into contact with the damaged dam 120, oxygen or moisture penetrating into the damaged dam 120 is absorbed into the organic film 292 and penetrates into the light emitting element 280, so that the light emitting element 280 deterioration may occur.

The first buffer layer 132 and the second buffer layer 134 may be formed simultaneously with at least one of the planarization film 260 and the bank 284 of the pixel P, and the planarization film 260 and the bank 284 It may be made of the same material as at least one of them. In this case, the first buffer layer 132 and the second buffer layer 134 are made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. (polyimide resin) or the like.

4th Example

FIG. 15 is a plan view schematically showing a first substrate according to a fourth embodiment of the present invention, and FIG. 16 is a cross-sectional view schematically showing a cross section taken along line II-II′ shown in FIG. 15 .

15 and 16 illustrate the TFT substrate 200 including the thin film transistors 210 and the capacitor 220, omitting specific configurations for convenience of description. The TFT substrate 200 may include the first substrate 111 shown in FIG. 8 , a gate insulating layer 230 and an interlayer insulating layer 240 .

15 and 16 , the first substrate 111 is divided into a display area DA and a non-display area NDA, and a pad area PA and a buffer layer in which pads are formed in the non-display area NDA. (130) may be formed. At this time, the first substrate shown in FIGS. 15 and 16 is different from the first substrates shown in FIGS. 6 to 10 in that a dam is not formed and the encapsulation film does not include an organic film. Hereinafter, the same contents as those of FIGS. 6 to 10 will be omitted.

The encapsulation film 290 is formed to cover the light emitting element 280 formed in the display area DA and prevents oxygen or moisture from penetrating the light emitting element 280 . At this time, the encapsulation film 290 includes at least one inorganic film. For example, the encapsulation film 290 may include one first inorganic film 291 . In this case, the first inorganic layer 291 is formed to cover the first electrode 282 .

The first inorganic layer 291 may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first inorganic layer 291 may be deposited using a chemical vapor deposition (CVD) technique or an atomic layer deposition (ALD) technique, but is not limited thereto.

15 and 16 show one first inorganic layer 291, but are not limited thereto. In another embodiment, the inorganic layer may include a first inorganic layer 291 and a second inorganic layer 292 .

The buffer layer 130 is formed in the non-display area NDA and contacts the edge of the first inorganic layer 291 . More specifically, the buffer layer 130 is formed to be spaced apart from the scribing line SL in the non-display area NDA, and in the process of depositing the first inorganic layer 291, the mask 140 is formed on the TFT substrate 200. ) and the mask 140 is supported to maintain a predetermined distance. To this end, the mask 140 is disposed on the buffer layer 130 so as to contact the buffer layer 130 .

When the first inorganic layer 291 is deposited after disposing the mask 140 on the buffer layer 130, the first inorganic layer 291 is formed in an area other than the area where the mask 140 is disposed. At this time, since no space is formed between the mask 140 and the TFT substrate 200 by the buffer layer 130, the first inorganic layer 291 is blocked from penetrating into the area where the mask 140 is disposed. As a result, the present invention disposes the buffer layer 130 in the non-display area NDA to be spaced apart from the scribing line SL and disposes the mask 140 to contact the buffer layer 130, so that the first inorganic film 291 may be prevented from being formed outside the buffer layer 130, for example, on the scribing line SL.

The buffer layer 130 may be formed at the same time as at least one of the planarization film 260 and the bank 284 of the pixel P, and may be made of the same material as at least one of the planarization film 260 and the bank 284. there is. In this case, the buffer layer 130 is made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can be formed

5th Example

17 is a plan view schematically showing a first substrate according to a fifth embodiment of the present invention.

Referring to FIG. 17 , the first substrate 111 is divided into a display area DA and a non-display area NDA, and in the non-display area NDA, a pad area PA where pads are formed and a dam 120 are formed. And a buffer layer 130 may be formed. At this time, the buffer layer 130 shown in FIG. 18 is formed with a plurality of island-type patterns. The buffer layer 130 formed of a plurality of island-type patterns may also be applied to other embodiments.

The buffer layer 130 may be formed in a plurality of island patterns along the periphery of the dam 120 . In the present invention according to the fifth embodiment, since the buffer layer 130 is formed with a plurality of island patterns instead of line patterns, an increase in stress in the non-display area NDA due to the formation of the buffer layer 130 can be reduced.

6th Example

18 is a plan view schematically showing a first substrate according to a sixth embodiment of the present invention.

Data lines and gate lines crossing the data lines are formed in the display area DA. Also, in the display area DA, pixels P displaying an image in a matrix form are formed at intersections of the data lines and the gate lines. Each of the pixels P supplies a predetermined current to the light emitting element 260 according to the data voltage of the data line when the gate signal of the gate line is input. As a result, the light emitting element 260 of each of the pixels P may emit light with a predetermined brightness according to a predetermined current. In addition, a power supply voltage is supplied to the power line. The power line supplies a power voltage to each of the pixels P.

In the non-display area NDA, the dam 120, the power auxiliary line VAL connected to the power lines, the pads PAD connected to the power auxiliary line VAL, and the buffer layer 130 are formed. In addition, although not specifically shown in the drawings for convenience of description, data link lines DLLs to which data lines are connected are further formed in the non-display area NDA.

The pad area PA may be disposed on one side edge of the first substrate 111 . The pad area PA includes a plurality of pads, and the plurality of pads may be electrically connected to wires of the flexible film 150 by using an anisotropic conducting film.

The dam 120 is disposed to surround the display area DA and blocks the flow of the organic layer 292 . In addition, the dam 120 is disposed between the display area DA and the pad area PA to prevent the organic film 292 constituting the encapsulation film 290 of the pixel P from invading the pad area PA. The flow of the organic layer 292 is blocked.

The data link lines DLL are connected one-to-one with the pads PAD disposed in the pad area PA and connected one-to-one with the data lines disposed in the display area DA. Specifically, one end of the data link line DLL is connected to the data line through the first contact hole, and the other end is connected to the pad PAD through the second contact hole. The pad PAD may be electrically connected to the wires of the flexible film 150 through the third contact hole using an anisotropic conducting film.

The data link line DLL may be formed parallel to the data line at one end connected to the data line and then formed obliquely to the data line until a predetermined length, and from the predetermined length to the other end connected to the pad PAD. (PAD) can be formed in parallel.

The data link lines DLL may be formed of a gate metal pattern made of the same material as the gate electrode 212 . The data line and pad PAD may be formed of a source/drain metal pattern made of the same material as the source/drain electrodes 213/214.

The power auxiliary line VAL is formed parallel to the gate lines and is connected to the pad PAD disposed in the pad area PA and the power lines disposed in the display area DA. When the power supply voltage is applied from the pad PAD, the power auxiliary line VAL supplies the applied power voltage to the power line. In this case, the power auxiliary line VAL is not directly connected to the power lines, but may be connected to the power lines by using connection lines connected to the power lines one-to-one.

The connection lines may be formed of a gate metal pattern made of the same material as the gate electrode 212 . The auxiliary power line VAL and the power line may be formed of a source/drain metal pattern made of the same material as the source/drain electrodes 213/214.

The buffer layer 130 is disposed on a power auxiliary line VAL to which a power supply voltage is applied from a metal pattern, for example, a pad PAD, in the non-display area NDA, and forms an encapsulation film 290 of the pixel P. In contact with the first inorganic film 291 or the second inorganic film 293 constituting the. The sixth embodiment of the present invention is characterized in that the first inorganic film 291 or the second inorganic film 293 covers a portion of the upper surface of the buffer layer 130 .

Hereinafter, a buffer layer according to a sixth embodiment of the present invention will be described in detail with reference to FIG. 19 .

19 is a cross-sectional view schematically illustrating a cross-section along line III-III′ shown in FIG. 18, and FIG. 20 is a cross-sectional view showing an example in which a mask is disposed on the buffer layer of FIG. 19. Referring to FIG. 21 is a cross-sectional view schematically illustrating a modified embodiment of FIG. 19 . Hereinafter, differences from the first embodiment will be mainly described, and the same contents as the first embodiment will be omitted.

The display device shown in FIG. 19 includes an encapsulation film 290 formed on a first substrate 111 , a dam 120 and a buffer layer 130 . At this time, the first substrate 111 is divided into a display area DA in which pixels P are formed and a non-display area NDA, and a pad area PA in which a plurality of pads PAD are formed in the non-display area NDA. ).

The encapsulation film 290 is formed to cover the light emitting element 280 formed in the display area DA and prevents oxygen or moisture from penetrating the light emitting element 280 . In this case, the encapsulation film 290 includes at least one inorganic film and at least one organic film. For example, the encapsulation film 290 may include a first inorganic film 291 , an organic film 292 , and a second inorganic film 293 . In this case, the first inorganic layer 291 is formed to cover the first electrode 282 . An organic layer 292 is formed on the first inorganic layer 291 , and a second inorganic layer 293 is formed to cover the organic layer 292 .

The dam 120 is formed to surround the periphery of the display area DA and blocks the flow of the organic layer 292 constituting the encapsulation layer 290 . Since the organic layer 292 constituting the encapsulation layer 290 has excellent covering performance but poor barrier performance, it must be sealed by the second inorganic layer 293 . However, when the organic layer 292 overflows outside the region where the organic layer 292 is to be formed, moisture, oxygen, and the like penetrate through the exposed organic layer 292 without being sealed by the second inorganic layer 293 . To prevent this, the organic layer 292 may be prevented from being exposed to the outside of the display device by blocking the flow of the organic layer 292 using the dam 120 .

In addition, the dam 120 is disposed between the display area DA and the pad area PA to prevent the organic film 292 constituting the encapsulation film 290 from invading the pad area PA. block the flow of When the organic film 292 constituting the encapsulation film 290 invades the pad area PA, electrical contact is not properly made on the pad PAD by the organic film 292, resulting in driving failure or lighting inspection failure. can To prevent this, the flow of the organic layer 292 constituting the encapsulation layer 290 is blocked using the dam 120, thereby preventing the organic layer 292 from invading the pad area PA. .

19 and 20 show one dam 120, but are not limited thereto. In another embodiment, the dam 120 may include a first dam and a second dam disposed in the non-display area and spaced apart from the first dam. The second dam blocks the flow of the organic film 292 overflowing to the outside of the first dam.

The dam 120 may be formed at the same time as at least one of the planarization film 260 and the bank 284 of the pixel P, and may be made of the same material as at least one of the planarization film 260 and the bank 284. there is. In this case, the dam 120 is made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can be formed

The buffer layer 130 is formed in the non-display area NDA and contacts an edge of at least one of the first inorganic layer 291 and the second inorganic layer 293 . More specifically, the buffer layer 130 is formed in the process of depositing the first inorganic layer 291 or the second inorganic layer 293 between the dam 120 and the scribing line SL in the non-display area NDA. The mask 140 is supported so that the mask 140 maintains a predetermined distance from the first substrate 111 . To this end, the mask 140 is disposed on the buffer layer 130 so as to contact the buffer layer 130 as shown in FIG. 20 .

When the first inorganic layer 291 or the second inorganic layer 293 is deposited after the mask 140 is disposed on the buffer layer 130, the first inorganic layer 291 or the second inorganic layer 293 It is formed in an area other than the area where the mask 140 is disposed. At this time, since no space is formed between the mask 140 and the TFT substrate 200 by the buffer layer 130, the first inorganic film 291 or the second inorganic film 293 enters the area where the mask 140 is disposed. penetration is blocked. As a result, the present invention arranges the buffer layer 130 between the dam 120 and the scribing line SL and places the mask 140 in contact with the buffer layer 130, thereby forming the first inorganic film 291 Alternatively, it is possible to prevent the second inorganic layer 293 from being formed outside the buffer layer 130, for example, on the scribing line SL.

In addition, the buffer layer 130 may be formed between the dam 120 and the pad area PA to prevent the formation of the first inorganic film 291 or the second inorganic film 293 in the pad area PA. . Through this, it is possible to prevent driving failure or lighting inspection failure from occurring due to electrical contact not being made in the pad part by the first inorganic layer 291 or the second inorganic layer 293 .

On the other hand, when the first inorganic layer 291 or the second inorganic layer 293 is deposited using the CVD technique, a high voltage is instantaneously applied in the process of depositing the first inorganic layer 291 or the second inorganic layer 293. is formed For example, since a large amount of charge is instantly gathered at the edge E of the mask 140, static electricity is generated between the mask 140 and the power auxiliary line VAL disposed in a region corresponding to the edge E. Therefore, there is a problem that a defect occurs in the mask 140 as well as in the power auxiliary line VAL. Although the protective film 250 is formed on the power auxiliary line VAL, the protective film 250 is generally formed very thin, so that a high voltage is applied in the process of depositing the first inorganic film 291 or the second inorganic film 293. It is often torn off by

In order to solve the above problems, the sixth embodiment of the present invention forms the buffer layer 130 on the metal pattern formed in the non-display area NDA, for example, on the power auxiliary line VAL. Also, in the process of depositing the first inorganic layer 291 or the second inorganic layer 293, the mask 140 is disposed to cover only a portion of the upper surface of the buffer layer 130 as shown in FIG. 21 . The buffer layer 130 contacts an edge of the first inorganic layer 291 or the second inorganic layer 293, and a portion of the upper surface is covered with the first inorganic layer 291 or the second inorganic layer 293.

Accordingly, since the buffer layer 130 is formed between the edge E of the mask 140 and the power auxiliary line VAL, in the process of depositing the first inorganic film 291 or the second inorganic film 293 Even if a large amount of charge is momentarily gathered at the edge E of the mask 140 , generation of static electricity between the mask 140 and the power auxiliary line VAL can be prevented by the buffer layer 130 .

At least one of the first inorganic layer 291 and the second inorganic layer 292 deposited as described above covers a portion of the upper surface of the buffer layer 130 . 20 illustrates that the buffer layer 130 is partially covered by the first inorganic layer 291 and the second inorganic layer 293, but is not limited thereto.

In another embodiment, only the second inorganic layer 293 may be formed on a part of the upper surface of the buffer layer 130 and only the edge of the second inorganic layer 293 may come into contact with it. More specifically, the first inorganic layer 291 and the second inorganic layer 293 may be deposited using different deposition techniques. Since the light emitting device 280 is not formed flat, the first inorganic layer 291 may be deposited using an ALD technique having high step coverage. In the case of manufacturing with the ALD technique, unlike the CVD process, since a high voltage is not formed, there is no problem in that static electricity is generated between the mask and the power auxiliary line. Accordingly, the first inorganic layer 291 may be deposited using an ALD technique after disposing a mask to be spaced apart from the first substrate 111 . In this case, the mask may be disposed to contact the buffer layer 130 or may be disposed to be spaced apart from the buffer layer 130 . Also, the mask may be disposed to cover the entire upper surface of the buffer layer 130 .

On the other hand, since the second inorganic layer 293 is formed on the relatively flat organic layer 292, it may be deposited using a CVD technique. The second inorganic layer 293 may be deposited using a CVD technique after disposing the mask 140 on the buffer layer 130 so as to contact the buffer layer 130 . In this case, the mask 140 may be disposed to cover a portion of the upper surface of the buffer layer 130 . Accordingly, the second inorganic layer 293 may completely cover the first inorganic layer 291 and the organic layer 292 .

And, the buffer layer 130 can prevent the propagation of cracks by forming at least one groove 135 exposing the protective film 150 as shown in FIG. 22 . At least one groove 135 may be referred to as an anti-crack groove.

The buffer layer 130 may be formed at the same time as at least one of the planarization film 260 and the bank 284 of the pixel P, and may be made of the same material as at least one of the planarization film 260 and the bank 284. there is. In this case, the buffer layer 130 is made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. can be formed

7th Example

22 is a plan view schematically showing a first substrate according to a seventh embodiment of the present invention. 22 is different from the first substrate shown in FIG. 18 in that the power auxiliary lines include a first power auxiliary line VAL1 and a second power auxiliary line VAL2. Hereinafter, the overlapping content with FIG. 19 will be omitted.

In the non-display area NDA, the dam 120, a first power auxiliary line VAL1 to which power lines are connected, a second power auxiliary line VAL2 disposed on the first power auxiliary line VAL1, and a first power Pads PAD connected to the auxiliary line VAL1 and the buffer layer 130 are formed. In addition, although not specifically shown in the drawings for convenience of description, data link lines DLLs to which data lines are connected are further formed in the non-display area NDA.

The power auxiliary line VAL is formed parallel to the gate lines and is connected to the pad PAD disposed in the pad area PA and the power lines disposed in the display area DA. When the power supply voltage is applied from the pad PAD, the power auxiliary line VAL supplies the applied power voltage to the power line. In this case, the power auxiliary line VAL is not directly connected to the power lines, but may be connected to the power lines by using connection lines connected to the power lines one-to-one.

The power auxiliary line VAL may include a first power auxiliary line VAL1 and a second power auxiliary line VAL2. The second power auxiliary line VAL2 may be formed on the first power auxiliary line VAL1 and connected to the first power auxiliary line VAL1 through a contact hole. More specifically, the second power auxiliary line VAL2 is connected to the first power auxiliary line VAL1 through a contact hole penetrating the third buffer layer 136 . In this way, by additionally forming the second power auxiliary line VAL2 on the first power auxiliary line VAL1, the power auxiliary line VAL can increase its sectional area and, as a result, reduce the resistance to stabilize the power supply voltage. can be supplied with

The connection lines may be formed of a gate metal pattern made of the same material as the gate electrode 212 . The first power auxiliary line VAL1 and the power line may be formed of a source/drain metal pattern made of the same material as the source/drain electrodes 213/214.

The buffer layer 130 is disposed on a power auxiliary line VAL to which a power supply voltage is applied from a metal pattern, for example, a pad PAD, in the non-display area NDA, and forms an encapsulation film 290 of the pixel P. In contact with the first inorganic film 291 or the second inorganic film 293 constituting the. The buffer layer 130 according to the seventh embodiment of the present invention includes a third buffer layer 136 and a fourth buffer layer 138, and the fourth buffer layer 138 is the first inorganic layer 291 or the second inorganic layer. It is characterized in that a part of the upper surface is covered by (293).

Hereinafter, a buffer layer according to a seventh embodiment of the present invention will be described in detail with reference to FIGS. 23 and 24 .

FIG. 23 is a cross-sectional view schematically illustrating a cross-section along the line III-III′ shown in FIG. 22, and FIG. 24 is a cross-sectional view schematically illustrating a modified embodiment of FIG. In the first substrate shown in FIGS. 23 and 24, the buffer layer 130 includes the third buffer layer 136 and the fourth buffer layer 138, and the third buffer layer 136 and the fourth buffer layer 138 are interposed between the first substrate. It is different from the first substrate shown in FIGS. 18 to 20 in that 2 power auxiliary lines VAL2 are formed. Hereinafter, overlapping content with FIGS. 18 to 20 will be omitted.

The display device shown in FIG. 22 includes an encapsulation film 290 formed on a first substrate 111 , a dam 120 and a buffer layer 130 . At this time, the first substrate 111 is divided into a display area DA in which pixels P are formed and a non-display area NDA, and a pad area PA in which a plurality of pads PAD are formed in the non-display area NDA. ).

The buffer layer 130 includes a third buffer layer 136 and a fourth buffer layer 138 . The third buffer layer 136 is formed on the first power auxiliary line VAL1 in the non-display area NDA. The second power auxiliary line VAL2 is formed on the third buffer layer 136 and is connected to the first power auxiliary line VAL1 through a contact hole penetrating the third buffer layer 136 and the passivation layer 150 . Also, the fourth buffer layer 138 is formed on the second power auxiliary line VAL2.

The fourth buffer layer 138 contacts an edge of at least one of the first inorganic layer 291 and the second inorganic layer 293 . In the process of depositing the first inorganic layer 291 or the second inorganic layer 293 , the mask 140 is disposed to cover only a portion of the upper surface of the fourth buffer layer 138 . Accordingly, the fourth buffer layer 138 is in contact with the edge of the first inorganic layer 291 or the second inorganic layer 293, and a portion of the upper surface is attached to the first inorganic layer 291 or the second inorganic layer 293. covered by

Since the fourth buffer layer 138 is formed between the edge E of the mask 140 and the second power auxiliary line VAL2, the process of depositing the first inorganic layer 291 or the second inorganic layer 293 Even if a large amount of charge is instantaneously gathered at the edge E of the mask 140, generation of static electricity between the mask 140 and the second power auxiliary line VAL2 can be prevented by the fourth buffer layer 138. In addition, since the third buffer layer 136 and the fourth buffer layer 138 are formed between the edge E of the mask 140 and the first power auxiliary line VAL1, the first inorganic layer 291 or the second In the process of depositing the inorganic film 293, even if a lot of charge is momentarily gathered at the edge E of the mask 140, the mask 140 and the first power supply are blocked by the third buffer layer 136 and the fourth buffer layer 138. Generation of static electricity between the auxiliary lines VAL1 can be prevented.

At least one of the first inorganic layer 291 and the second inorganic layer 292 deposited as described above covers a portion of the upper surface of the fourth buffer layer 138 . 23 illustrates that a portion of the upper surface of the fourth buffer layer 138 is covered by the first inorganic layer 291 and the second inorganic layer 293, but is not limited thereto.

In another embodiment, only the second inorganic layer 293 may be formed on a part of the upper surface of the fourth buffer layer 138 and only the edge of the second inorganic layer 293 may come into contact with it. More specifically, the first inorganic layer 291 and the second inorganic layer 293 may be deposited using different deposition techniques. Since the light emitting device 280 is not formed flat, the first inorganic layer 291 may be deposited using an ALD technique having high step coverage. In the case of manufacturing with the ALD technique, unlike the CVD process, since a high voltage is not formed, there is no problem in that static electricity is generated between the mask and the power auxiliary line. Accordingly, the first inorganic layer 291 may be deposited using an ALD technique after disposing a mask to be spaced apart from the first substrate 111 . In this case, the mask may be placed in contact with the fourth buffer layer 138 or may be spaced apart from the fourth buffer layer 136 . Also, the mask may be disposed to cover the entire upper surface of the fourth buffer layer 136 .

On the other hand, since the second inorganic layer 293 is formed on the relatively flat organic layer 292, it may be deposited using a CVD technique. The second inorganic layer 293 may be deposited on the fourth buffer layer 138 using a CVD technique after disposing the mask 140 so as to contact the fourth buffer layer 138 . In this case, the mask 140 may be disposed to cover a portion of the upper surface of the fourth buffer layer 138 . Accordingly, the second inorganic layer 293 may completely cover the first inorganic layer 291 and the organic layer 292 .

Meanwhile, the third buffer layer 136 and the fourth buffer layer 138 may have the same area as shown in FIG. 23, but are not limited thereto. In another embodiment, the fourth buffer layer 138 may be formed to have a larger area than the third buffer layer 136 as shown in FIG. 24 .

The buffer layer 130 may be formed at the same time as at least one of the planarization film 260 and the bank 284 of the pixel P, and may be made of the same material as at least one of the planarization film 260 and the bank 284. there is. For example, the third buffer layer 136 may be formed simultaneously with the planarization layer 260 and may be made of the same material as the planarization layer 260 . The fourth buffer layer 138 may be formed at the same time as the bank 284 and may be made of the same material as the bank 284 .

18 to 28 illustrate that the buffer layer 130 is disposed only between the dam 120 and the pad area PA, but is not limited thereto. In another embodiment, the buffer layer 130 may be disposed to surround the dam 120 . Also, the buffer layer 130 may be formed in a plurality of island-type patterns. A plurality of metal lines may be disposed in the non-display area NDA as needed in addition to the power auxiliary line VAL. The plurality of metal lines may be disposed between the display area DA and the pad area PA according to panel design, or may be disposed on a side of the non-display area NDA on which the pad area PA is not disposed. When the first inorganic film 291 or the second inorganic film 293 constituting the encapsulation film is deposited by forming the buffer layer 130 on the plurality of metal lines, there is a gap between the edge E of the mask 140 and the metal line. The generation of static electricity can be prevented.

25 is a flowchart for explaining a method for manufacturing a display device according to the first embodiment of the present invention, and FIGS. 26A to 26H are cross-sectional views for explaining a method for manufacturing a display device according to the first embodiment of the present invention. .

First, the pixel P is formed in the display area DA, and the buffer layer 130 is formed in the non-display area NDA (S2601).

More specifically, as shown in FIG. 26A , a TFT substrate 200 is prepared and a protective film 250 is formed on the TFT substrate 200 . The protective layer 250 may serve as an insulating layer. The protective layer 250 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

Then, as shown in FIG. 26B, a planarization layer 260, a dam 120, and a lower buffer layer 1301 are formed. More specifically, a planarization layer 260, a dam 120, and a lower buffer layer 1301 are formed on the passivation layer 250. At this time, the dam 120 is formed in the non-display area NDA, and the lower buffer layer 1301 is formed outside the dam 120 . Each of the planarization film 260, the dam 120 and the lower buffer layer 1301 is made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. (polyimide resin) or the like. Although the planarization film 260 has been described as a single layer, it may be formed of two or more layers. For example, when it consists of two layers, a protective film may be additionally formed between the two layers. In the case of forming the planarization film 260 composed of two layers such as an upper planarization film and a lower planarization film, the buffer layer 1301 and the dam 120 may be selectively formed together when forming the upper planarization film and the lower planarization film. there is. For example, when forming the lower planarization layer, the buffer layer 1301 and the dam 120 may be formed together or only the buffer layer 1301 may be formed. In addition, when forming the upper planarization layer, the buffer layer 1301 and the dam 120 may be formed together or only the buffer layer 1301 may be formed.

26B shows that the dam 120 is formed between the lower buffer layer 1301 and the planarization layer 260, but in another embodiment, the dam 120 may not be formed.

Meanwhile, although FIG. 26B shows that the lower buffer layer 1301 is formed outside the dam 120, in another embodiment, the lower buffer layer 1301 is formed between the dam 120 and the planarization film 260 It could be.

26B shows that the dam 120 is formed simultaneously with the flattening film 260, but in another embodiment, the dam 120 may be formed simultaneously with the protective film 250 or the bank 284 formed later. there is.

And, as shown in FIG. 26C, a contact hole CH3 is formed through the passivation layer 250 and the planarization layer 260 to expose the source or drain electrode 224 of the thin film transistor 210, and the second electrode 281 form The second electrode 281 may include a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO/APC /ITO) may be formed of a metal material with high reflectivity. An APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

Then, as shown in FIG. 26D, a bank 284 and an upper buffer layer 1302 are formed. More specifically, the bank 284 is formed to cover the edge of the second electrode 281 on the planarization layer 260 to partition the light emitting units EA. Then, an upper buffer layer 1302 is formed on the lower buffer layer 1301 . Each of the bank 284 and the upper buffer layer 1302 is made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like. It can be formed as an organic film.

Then, as in 26e, the light emitting layer 283 and the first electrode 282 are formed. More specifically, a light emitting layer 283 is formed on the second electrode 281 and the bank 284 . Then, a first electrode 282 is formed on the light emitting layer 283 . The first electrode 282 is a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or magnesium (Mg), silver (Ag), or magnesium (Mg) and silver (Ag). It may be formed of a semi-transmissive conductive material such as an alloy of. A capping layer may be formed on the first electrode 282 .

Next, a mask 140 is disposed on the buffer layer 130 (S2602). More specifically, as shown in FIG. 26F , a mask 140 is disposed on the upper buffer layer 1302 so as to contact the upper buffer layer 1302 .

Next, an inorganic layer is formed to cover the display area DA (S2603).

As shown in FIG. 26G , a first inorganic layer 291 , an organic layer 292 , and a second inorganic layer 293 are formed. More specifically, the first inorganic layer 291 is formed to cover the display area DA. At this time, the first inorganic layer 291 is formed in an area excluding the area where the mask 140 is disposed by using a CVD technique or an ALD technique. The first inorganic layer 291 may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide.

Then, an organic layer 292 is formed to cover the first inorganic layer 291 and not to cover the dam 120 . The organic layer 292 is an organic material capable of passing 99% or more of the light emitted from the light emitting layer 283, for example, an acrylic resin, an epoxy resin, a phenolic resin, or a polyamide resin. (polyamide resin) or polyimide resin.

Then, a second inorganic layer 293 is formed to cover the organic layer 292 . At this time, the second inorganic layer 293 is formed in an area excluding the area where the mask 140 is disposed by using a CVD technique or an ALD technique. The second inorganic layer 293 may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide.

26G shows that the organic layer 292 and the second inorganic layer 293 are formed on the first inorganic layer 291, but in another embodiment, the organic layer 292 and the second inorganic layer ( 293) may not be formed. Also, the organic layer 292 may be formed as a double layer. A third inorganic layer may be formed between organic layers formed as double layers.

Next, the mask 140 is removed (S2604). 26H shows after the mask 140 is removed. More specifically, after removing the mask 140 disposed on the upper buffer layer 1302, although not shown in the drawing, the first substrate 111 and the second substrate 112 are bonded. When a plurality of display devices are simultaneously manufactured using one mother substrate, a scribing process is performed to separate a plurality of display panels formed on the mother substrate into display devices. A scribing line SL is formed between adjacent display panels, and each display panel is separated into a display device by cutting along the scribing line SL.

In the present invention, since the first inorganic layer 291 and the second inorganic layer 293 are not formed on the scribing line SL by the buffer layer 130, the first inorganic layer 291 and the second inorganic layer 291 are not formed in the scribing process. Generation of cracks in the second inorganic layer 293 may be prevented. Accordingly, degradation of the light emitting element 280 may be prevented.

27 is a flowchart illustrating a method of manufacturing a display device according to a second embodiment of the present invention, and FIGS. 28A to 28L are cross-sectional views illustrating a method of manufacturing a display device according to a second embodiment of the present invention. .

First, the pixel P is formed in the display area DA, and the first buffer layer 132 and the second buffer layer 134 are formed in the non-display area NDA (S2801).

More specifically, as shown in FIG. 28A , a TFT substrate 200 is prepared and a protective film 250 is formed on the TFT substrate 200 . The protective layer 250 may serve as an insulating layer. The protective layer 250 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

And, as shown in FIG. 28B, a planarization layer 260, a dam 120, a first lower buffer layer 1321, and a second lower buffer layer 1341 are formed. More specifically, a planarization layer 260 , a dam 120 , a first lower buffer layer 1321 , and a second lower buffer layer 1341 are formed on the passivation layer 250 . At this time, the dam 120 is formed between the first lower buffer layer 1321 and the second lower buffer layer 1341 in the non-display area NDA. The first lower buffer layer 1321 is formed between the dam 120 and the planarization layer 260 in the non-display area NDA. The second lower buffer layer 1341 is formed outside the dam 120 in the non-display area NDA.

Each of the planarization film 260, the dam 120, the first lower buffer layer 1321 and the second lower buffer layer 1341 is made of acrylic resin, epoxy resin, phenolic resin, It may be formed of an organic film such as polyamide resin or polyimide resin.

Although FIG. 28B shows that the dam 120 is formed, in another embodiment, the dam 120 may not be formed.

28B shows that the dam 120 is formed simultaneously with the planarization film 260, but in another embodiment, the dam 120 may be formed simultaneously with the protective film 250 or the bank 284 formed later. there is.

And, as shown in FIG. 28C, a contact hole (CH3) is formed to expose the source or drain electrode 224 of the thin film transistor 210 through the passivation layer 250 and the planarization layer 260, and the second electrode 281 form The second electrode 281 may include a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO/APC /ITO) may be formed of a metal material with high reflectivity. An APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

And, as shown in FIG. 28D, a bank 284, a first upper buffer layer 1322, and a second upper buffer layer 1342 are formed. More specifically, the bank 284 is formed to cover the edge of the second electrode 281 on the planarization layer 260 to partition the light emitting units EA. Then, a first upper buffer layer 1322 is formed on the first lower buffer layer 1321 , and a second upper buffer layer 1342 is formed on the second lower buffer layer 1341 .

Each of the bank 284, the first upper buffer layer 1322, and the second upper buffer layer 1342 is made of acrylic resin, epoxy resin, phenolic resin, or polyamide resin. resin), polyimide resin, or the like.

Then, as in 28e, the light emitting layer 283 and the first electrode 282 are formed. More specifically, a light emitting layer 283 is formed on the second electrode 281 and the bank 284 . Then, a first electrode 282 is formed on the light emitting layer 283 . The first electrode 282 is a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or magnesium (Mg), silver (Ag), or magnesium (Mg) and silver (Ag). It may be formed of a semi-transmissive conductive material such as an alloy of. A capping layer may be formed on the first electrode 282 .

Next, a first mask 142 is disposed on the first buffer layer 132 (S2802). More specifically, as shown in FIG. 28F , the first mask 142 is disposed on the first upper buffer layer 1322 so as to contact the first upper buffer layer 1322 .

Next, a first inorganic layer 291 is formed to cover the display area DA (S2803).

As shown in FIG. 28G , a first inorganic layer 291 is formed. More specifically, the first inorganic layer 291 is formed to cover the display area DA. At this time, the first inorganic layer 291 is formed in an area excluding the area where the first mask 142 is disposed by using a CVD technique or an ALD technique. The first inorganic layer 291 may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide.

Next, the first mask 142 is removed (S2804). More specifically, the first mask 142 disposed on the first buffer layer 132 is removed as shown in FIG. 28H. And, as shown in FIG. 28I, an organic layer 292 is formed to cover the first inorganic layer 291 and not to cover the dam 120 at the same time. The organic layer 292 is an organic material capable of passing 99% or more of the light emitted from the light emitting layer 283, for example, an acrylic resin, an epoxy resin, a phenolic resin, or a polyamide resin. (polyamide resin) or polyimide resin.

Although FIG. 28I illustrates forming the organic layer 292 on the first inorganic layer 291, in another embodiment, the organic layer 292 may not be formed.

Next, a second mask 144 is disposed on the second buffer layer 134 (S2805). More specifically, as shown in FIG. 28J , the second mask 144 is disposed on the second upper buffer layer 1342 so as to contact the second upper buffer layer 1342 . In this case, the area of the second mask 144 may be smaller than that of the first mask 142 so that the second inorganic layer 293 may be formed wider than the first inorganic layer 291 .

Next, a second inorganic layer 293 is formed on the first inorganic layer 291 (S2806). More specifically, as shown in FIG. 28K , a second inorganic layer 293 is formed to cover the organic layer 292 . At this time, the second inorganic layer 293 is formed in an area excluding the area where the second mask 144 is disposed by using a CVD technique or an ALD technique. The second inorganic layer 293 may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide.

Next, the second mask 144 is removed (S2807). More specifically, the second mask 144 disposed on the second buffer layer 134 is removed as shown in FIG. 28L. Although not shown in the figure, the first substrate 111 and the second substrate 112 are bonded. When a plurality of display devices are simultaneously manufactured using one mother substrate, a scribing process is performed to separate a plurality of display panels formed on the mother substrate into display devices. A scribing line SL is formed between adjacent display panels, and each display panel is separated into a display device by cutting along the scribing line SL.

8th Example

29 is a plan view schematically showing a first substrate according to an eighth embodiment of the present invention. FIG. 30 is a cross-sectional view schematically showing a cross-section along line III-III' shown in FIG. 29, and FIG. 31 is a cross-sectional view schematically showing a cross-section along line II-II' shown in FIG.

29 to 31 , the first substrate 111 may be divided into a display area DA and a non-display area NDA.

Pixels P displaying images may be formed in the display area DA. Each of the pixels may include a thin film transistor 210 , a light emitting device 280 and an auxiliary electrode 215 . The light emitting device 280 may include a second electrode 281 , a light emitting layer 283 and a first electrode 282 . Each of the pixels uses the thin film transistor 210 to supply a predetermined current to the light emitting element 280 according to the data voltage of the data line when a gate signal is input from the gate line. Due to this, the light emitting element 280 of each of the pixels may emit light with a predetermined brightness according to a predetermined current.

A pad area PA where pads are formed, a dam 120 , a buffer layer 130 , and an auxiliary buffer layer 180 may be formed in the non-display area NDA.

The pad area PA may be disposed on one edge of the first substrate 111 . The pad area PA includes a plurality of pads, and the plurality of pads may be electrically connected to wires of the flexible film using an anisotropic conducting film (ACF).

The dam 120 may include a first dam 122 and a second dam 121 . The first dam 122 and the second dam 121 may be disposed to surround the display area DA, and at least one of the first dam 122 and the second dam 121 is the organic layer 292 can block the flow of In addition, the first dam 122 and the second dam 121 are disposed between the display area DA and the pad area PA, and the organic film 292 constituting the encapsulation film 290 of the pixel P is The flow of the organic layer 292 may be blocked so as not to invade the pad area PA.

The buffer layer 130 may be spaced apart from the display area DA in the non-display area NDA. For example, it may be disposed between the display area DA and the pad area PA, and wires connecting the pad PAD of the pad area PA and the pixel P of the display area DA are protected from static electricity. can protect In addition, it may serve to support a mask device used to form the first inorganic film 291 or the second inorganic film 293 constituting the encapsulation film 290 .

The auxiliary buffer layer 180 may be spaced apart from the display area DA in the non-display area NDA. For example, it may be spaced apart from the second dam 121 constituting the dam 120 in the non-display area NDA, and the first inorganic film 291 or the second inorganic film constituting the encapsulation film 290 It may serve to support a mask device used to form the film 293 .

Hereinafter, the structure of the pixel P of the display area DA according to the eighth embodiment of the present invention, the dam 120, the buffer layer 130, and the auxiliary buffer layer 180 will be described in detail with reference to FIGS. 30 to 31. Let's see.

FIG. 30 is a cross-sectional view schematically illustrating a cross section along line III-III' shown in FIG. 29 . A cross-sectional view showing an example of the dam 120 and the buffer layer 130 in the non-display area NDA of FIG. 29 and the pixel P in the display area DA.

Referring to FIG. 30 , a thin film transistor 210 and a light emitting device 280 may be formed on one surface of the first substrate 111 in the display area DA.

A buffer layer 231 may be formed on the first substrate 111 to protect the thin film transistor 210 from moisture penetrating through the first substrate 111 , which is vulnerable to moisture permeation.

Each of the thin film transistors 210 includes an active layer 211 , a gate electrode 212 , a source electrode 213 and a drain electrode 214 . 30 illustrates that the gate electrodes 212 of the thin film transistors 210 are formed in a top gate (top gate) method located above the active layer 211, but is not limited thereto. For example, the thin film transistor 210 has a bottom gate (bottom gate) method in which the gate electrode 212 is located below the active layer 211 or the gate electrode 212 is located above the active layer 211. It may be formed in a double gate method located on both the and lower sides.

An active layer 211 is formed on the buffer layer 231 of the first substrate 110 . The active layer 211 may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. A light blocking layer may be formed on the first substrate 111 to block external light incident on the active layer 211 .

A gate insulating layer 230 may be formed on the active layer 211 . The gate insulating layer 230 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

A gate electrode 212 may be formed on the gate insulating layer 230 . The gate electrode 212 is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or these It may be a single layer or multi-layer made of an alloy of, but is not limited thereto.

An interlayer insulating layer 240 may be formed on the gate electrode 212 . The interlayer insulating layer 240 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

A source electrode 213 and a drain electrode 214 may be formed on the interlayer insulating layer 240 . Each of the source electrode 213 and the drain electrode 214 may be connected to the active layer 211 through a contact hole passing through the gate insulating layer 230 and the interlayer insulating layer 240 . The source electrode 213 and the drain electrode 214 are composed of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper ( Cu) may be a single layer or a multi-layer made of any one or an alloy thereof, but is not limited thereto.

A protective layer 250 may be formed on the thin film transistor 210 . The protective layer 250 may serve as an insulating layer. The protective layer 250 may be formed of an inorganic layer, for example, a silicon oxide layer, a silicon nitride layer, or a multilayer thereof.

A first planarization layer 261 may be formed on the passivation layer 250 to flatten a level difference caused by the thin film transistor 210 . The first planarization layer 261 is formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be.

An auxiliary electrode 215 for electrically connecting the drain electrode 214 and the second electrode 281 may be formed on the first planarization layer 261 . The auxiliary electrode 215 may be connected to the drain electrode 214 through a contact hole passing through the first planarization layer 261 and the passivation layer 250 . The auxiliary electrode 215 is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or these It may be a single layer or multi-layer made of an alloy of, but is not limited thereto.

A second planarization layer 262 may be formed on the auxiliary electrode 215 . The second planarization film 262 is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. It can be.

A light emitting element 280 and a bank 284 are formed on the second planarization layer 262 . The light emitting element 280 includes a first electrode 282 , a light emitting layer 283 , and a second electrode 281 . The first electrode 282 may be a cathode electrode, and the second electrode 281 may be an anode electrode. An area in which the first electrode 282 , the light emitting layer 283 , and the second electrode 281 are stacked may be defined as the light emitting part EA.

The second electrode 281 may be formed on the second planarization layer 262 . The second electrode 281 may be connected to the drain gap 214 of the thin film transistor 210 through a contact hole penetrating the second planarization layer 262 . The second electrode 281 may include a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO/APC /ITO) may be formed of a metal material with high reflectivity. An APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

The bank 284 may be formed to cover the edge of the second electrode 281 on the second planarization layer 262 to partition the light emitting units EA. The bank 284 may be formed of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. .

A spacer 285 may be formed on the bank 284 . The spacer 285 may be formed of the same material as the bank 284 .

An emission layer 283 is formed on the second electrode 281 , the bank 284 and the spacer 285 . The light emitting layer 283 may include a hole transporting layer, at least one light emitting layer, and an electron transporting layer. In this case, when a voltage is applied to the second electrode 281 and the first electrode 282, holes and electrons move to the light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light emitting layer to emit light.

The first electrode 282 is formed on the light emitting layer 283 . When the electroluminescent display device is formed with a top emission structure, the first electrode 282 is a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or magnesium (Mg). ), silver (Ag), or a semi-transmissive conductive material such as an alloy of magnesium (Mg) and silver (Ag). A capping layer may be formed on the first electrode 282 .

An encapsulation film 290 is formed on the light emitting element 280 . The encapsulation film 290 serves to prevent oxygen or moisture from penetrating into the light emitting layer 283 and the first electrode 282 . To this end, the encapsulation layer 290 may include at least one inorganic layer and at least one organic layer.

For example, the encapsulation film 290 may include a first inorganic film 291 , an organic film 292 , and a second inorganic film 293 . In this case, the first inorganic layer 291 is formed to cover the first electrode 282 . An organic layer 292 is formed on the first inorganic layer 291 . The organic layer 292 may be formed to a thickness sufficient to prevent particles from penetrating the first inorganic layer 291 and being injected into the light emitting layer 283 and the first electrode 282 . The second inorganic layer 293 is formed to cover the organic layer 292 .

Referring to FIG. 30 , the non-display area NDA includes an encapsulation film 290 formed on the first substrate 111 , a dam 120 and a buffer layer 130 .

The encapsulation film 290 is formed to cover the light emitting element 280 formed in the display area DA, and can prevent oxygen or moisture from penetrating into the light emitting element 280 . In this case, the encapsulation film 290 may include at least one inorganic film and at least one organic film. For example, the encapsulation film 290 may include a first inorganic film 291 , an organic film 292 , and a second inorganic film 293 . In this case, the first inorganic layer 291 is formed to cover the first electrode 282 . An organic layer 292 is formed on the first inorganic layer 291 , and a second inorganic layer 293 is formed to cover the organic layer 292 .

Each of the first and second inorganic layers 291 and 293 may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. The first and second inorganic layers 291 and 293 may be deposited using a chemical vapor deposition (CVD) technique or an atomic layer deposition (ALD) technique, but are not limited thereto.

The organic layer 292 may be transparent to pass light emitted from the light emitting layer 283 . The organic layer 292 is an organic material capable of passing 99% or more of the light emitted from the light emitting layer 283, for example, an acrylic resin, an epoxy resin, a phenolic resin, or a polyamide resin. (polyamide resin) or polyimide resin. The organic layer 292 may be formed by vapor deposition using an organic material, printing, or slit coating, but is not limited thereto, and the organic layer 292 may be formed using an ink-jet jet) process.

The dam 120 is formed to surround the periphery of the display area DA and blocks the flow of the organic layer 292 constituting the encapsulation layer 290 . Since the organic layer 292 constituting the encapsulation layer 290 has excellent covering performance but poor barrier performance, it must be sealed by the second inorganic layer 293 . However, when the organic layer 292 overflows outside the region where the organic layer 292 is to be formed, moisture, oxygen, and the like penetrate through the exposed organic layer 292 without being sealed by the second inorganic layer 293 . To prevent this, the organic layer 292 may be prevented from being exposed to the outside of the display device by blocking the flow of the organic layer 292 using the dam 120 .

The dam 120 is disposed between the display area DA and the pad area PA to prevent the organic film 292 constituting the encapsulation film 290 from invading the pad area PA. block the flow of When the organic film 292 constituting the encapsulation film 290 invades the pad area PA, electrical contact is not properly made in the pad due to the organic film 292 , and driving failure or lighting inspection failure may occur. To prevent this, the flow of the organic layer 292 constituting the encapsulation layer 290 is blocked using the dam 120, thereby preventing the organic layer 292 from invading the pad area PA. .

As shown in FIG. 30 , the dam 120 may include a first dam 122 and a second dam 121 spaced apart from the first dam 122 . The first dam 122 may be formed to surround an outer area of the display area DA in the non-display area NDA, and the second dam 121 is spaced apart from the first dam 122 to form the first dam 122. It may be formed to surround the dam 122 . The first dam 122 blocks the flow of the organic film 292 constituting the encapsulation film 290 . When the organic layer 292 overflows to the outside of the first dam 122 , the second dam 121 spaced apart from the first dam 122 may block the flow of the organic layer 292 .

The first dam 122 and the second dam 121 may be formed of a single layer made of the same material as at least one of the second planarization film 262, the bank 284, and the spacer 285 of the pixel P. can Alternatively, at least two of the second planarization layer 262, the bank 284, and the spacer 285 may be formed of multiple layers made of the same material. For example, as shown in FIG. 30, the first dam 122 and the second dam 121 include lower layers 121c and 122c, middle layers 121b and 122b, and upper layers 121a and 122a. In the case of the middle layer, the second planarization layer 262, the bank 284, and the spacer 285 of the pixel P may be stacked with the same material. The lower layers 121c and 122c of the first dam 122 and the second dam 121 may be formed of the same material as the second planarization layer 262 of the pixel P. The intermediate layers 121b and 122b on the lower layers 121c and 122c of the first dam 122 and the second dam 121 may be formed of the same material as the bank 284 of the pixel P. Also, the upper layers 121a and 122a on the middle layers 121b and 122b of the first dam 122 and the second dam 121 may be formed of the same material as the spacer 285 of the pixel P. However, it is not limited thereto. For example, the first dam 122 is made of the same material as the bank 284 and the spacer 285 of the pixel P, and the second dam 121 is formed of the second planarization layer 262 and the bank ( 284) and the spacer 285 may be laminated with the same material. Alternatively, the first dam 122 is stacked with the same material as the bank 284 of the pixel P, and the second dam 121 is formed of the second planarization layer 262 and the bank 284 of the pixel P. They may be laminated with the same material.

The buffer layer 130 may be formed to be spaced apart from the dam 120 in the non-display area NDA. The buffer layer 130 supports the mask to maintain a predetermined distance from the first substrate 111 in the process of depositing the first inorganic layer 291 or the second inorganic layer 293 . To this end, a mask is disposed on the buffer layer 130 so as to contact the buffer layer 130 .

As shown in FIGS. 29 and 30 , the buffer layer 130 may be disposed between the pad area PA and the display area DA. For example, it is formed between the second dam 121 constituting the dam 120 and the pad area PA, so that the first inorganic film 291 or the second inorganic film 293 is formed in the pad area PA. can prevent it from happening. In addition, the wirings VAL1 and VAL2 electrically connecting the pad PAD of the pad area PA and the pixel P of the display area DA may be protected from static electricity by the buffer layer 130 .

Referring to FIG. 30 , the buffer layer 130 may include a first buffer layer 136 and a second buffer layer 138. The first buffer layer 136 and the second buffer layer 138 may be disposed between the pad area PA and the dam 120 . Further, the first buffer layer 136 is formed on the first power auxiliary line VAL1 to which the power supply voltage is applied from the pad PAD of the pad area PA or on the first data link line to which the data signal is applied from the pad PAD. can be placed in

Here, the first power auxiliary line VAL1 or the first data link line may be formed on the first substrate 111 . Also, the first buffer layer 136 may be disposed on the first power auxiliary line VAL1 or the first data link line. The first power auxiliary line VAL1 and the first data link line may be formed of the same material as the source electrode 213 and the drain electrode 214 of the pixel P. In addition, a passivation layer 250 may be disposed between the first power auxiliary line VAL1 and the first data link line and the first buffer layer 136, and the passivation layer 250 may be disposed between the first power auxiliary line VAL1 and the first buffer layer 136. 1 may be formed to cover both sides and top of the data link line.

The second power auxiliary line VAL2 or the second data link line may be formed on the first buffer layer 136, and the second power auxiliary line VAL2 and the second data link line are the auxiliary electrode of the pixel P. It may be formed of the same material as (215). The second power auxiliary line VAL2 or the second data link line is connected through a contact hole formed through the first buffer layer 136 .

The second buffer layer 138 is disposed on the second power auxiliary line VAL2 to which the power supply voltage is applied from the pad PAD of the pad area PA or on the second data link line to which the data signal is applied from the pad PAD. It can be.

The first inorganic film 291 and the second inorganic film 292 constituting the encapsulation film 290 may be formed to partially cover the upper surface of the second buffer layer 138 .

A first power line VAL1, a second power line VAL2, a first data link line, and a first power line VAL1 electrically connecting the pad PAD of the pad area PA and the pixel P of the display area PA, and The second data link wire may be protected from static electricity by the buffer layer 130 . For example, the buffer layer 130 may prevent arcing of static electricity generated in a process for forming the encapsulation film 290 .

Referring to FIG. 31 , the auxiliary buffer layer 180 according to the eighth embodiment will be described in detail. FIG. 31 is a cross-sectional view schematically illustrating a cross section along line II-II′ shown in FIG. 29 . 31 is a cross-sectional view showing an example of the dam 120 and the auxiliary buffer layer 180 in the non-display area NDA of FIG. 29 . Descriptions of the same components as those in FIG. 30 will be omitted.

Referring to FIG. 31 , the first dam 122 and the second dam 121 constituting the dam 120 are disposed in the non-display area NDA. As shown in FIG. 29 , the first dam 122 and the second dam 121 are spaced apart from the display area DA and are disposed in the non-display area NDA. The first dam 122 may be formed to surround an outer area of the display area DA in the non-display area NDA, and the second dam 121 is spaced apart from the first dam 122 to form the first dam 122. It may be formed to surround the dam 122 . The first dam 122 blocks the flow of the organic film 292 constituting the encapsulation film 290 . When the organic layer 292 overflows to the outside of the first dam 122 , the second dam 121 spaced apart from the first dam 122 may block the flow of the organic layer 292 .

On the side of the display area DA, the first power auxiliary line VAL1 may be formed on the interlayer insulating layer 240 . The second power auxiliary line VAL2 is connected to the first power auxiliary line VAL1 disposed below the protective film 250 through a contact hole formed through the protective film 250 . The second power auxiliary line VAL2 may be formed to overlap the lower surface of the lower layer 122a of the first dam 122 . The third power auxiliary line VAL3 formed on the second planarization layer 262 supplies the second power supply in the region between the ends of the first planarization layer 261 and the second planarization layer 262 and the first dam 122 . It is connected to the second power auxiliary line VAL2 through an opening exposing the auxiliary line VAL2. The third power auxiliary line VAL3 may be formed to overlap the upper surface of the lower layer 122a of the first dam 122 .

The first power auxiliary line VAL1 may be formed of the same material as the source electrode 213 and the drain electrode 214 of the pixel P. The second power auxiliary line VAL2 may be formed of the same material as the auxiliary electrode 215 of the pixel P. The third power auxiliary line VAL3 may be formed of the same material as the second electrode 291 of the pixel P.

The auxiliary buffer layer 180 may be disposed in the non-display area NDA apart from the second dam 121 constituting the dam 120 . The auxiliary buffer layer 180 supports the mask to maintain a predetermined distance from the first substrate 111 in the process of depositing the first inorganic layer 291 or the second inorganic layer 293 . To this end, a mask is disposed on the auxiliary buffer layer 180 so as to contact the auxiliary buffer layer 180 .

When the first inorganic layer 291 or the second inorganic layer 293 is deposited after disposing a mask (not shown) on the auxiliary buffer layer 180, the first inorganic layer 291 or the second inorganic layer 293 ) is formed in an area excluding the area where the mask is disposed. For example, since a space is not formed between the mask and the first substrate 111 by the auxiliary buffer layer 180, the first inorganic layer 291 or the second inorganic layer 293 penetrates into the region where the mask is disposed. it is blocked Therefore, in this embodiment, the auxiliary buffer layer 180 is disposed between the dam 120 and the scribing line SL, and the mask (by placing the auxiliary buffer layer 180 in contact with the second buffer layer 180b, It is possible to prevent the first inorganic layer 291 or the second inorganic layer 293 from being formed outside the auxiliary buffer layer 180, for example, on the scribing line SL. Area 291 and the second inorganic film 292 may be formed to partially overlap the upper surface of the second auxiliary buffer layer 180b of the auxiliary buffer layer 180 .

As shown in FIG. 29 , the auxiliary buffer layer 180 may be disposed to surround at least three surfaces of the display area DA. For example, the auxiliary buffer layer 180 may be disposed to surround three sides of the display area DA except for one side of the display area DA where the buffer layer 130 is formed. Accordingly, in the non-display area NDA, the first dam 122 is disposed to surround the display area DA. And, the second dam 121 is disposed to be spaced apart from the first dam 122 and is disposed to surround the first dam 121 . Also, the buffer layer 130 may be disposed between the second dam 121 and the pad area PA, facing one of the four surfaces of the display area DA. The auxiliary buffer layer 180 may be disposed to face three surfaces excluding one side of the display area DA facing the buffer layer 130 . Accordingly, three of the four surfaces of the second dam 121 formed to surround the first dam 122 may be disposed between the display area DA and the auxiliary buffer layer 180 . Also, the remaining surface may be disposed between the display area DA and the buffer layer 130 .

Referring to FIG. 31 , the auxiliary buffer layer 180 may include a first auxiliary buffer layer 180a on the passivation layer 250 and a second auxiliary buffer layer 180b disposed on the first auxiliary buffer layer.

The first auxiliary buffer layer 180a may be formed of the same material as the bank 284 of the pixel P. Also, the second auxiliary buffer layer 180b may be formed of the same material as the spacer 285 of the pixel P.

Also, when both sides of the display device are bent, cracks may occur in the auxiliary buffer layer 180 . In order to prevent cracks from propagating to the display area DA, grooves may be formed by patterning the first auxiliary buffer layer 180a and the second auxiliary buffer layer 180b. For example, the second auxiliary buffer layer 180b, the first auxiliary buffer layer 180a, the passivation layer 250, the interlayer insulating layer 240, the gate insulating layer 230, and the buffer layer 231 are removed to form the first substrate 111. It is possible to form a groove (groove) exposing. The groove may be referred to as a crack prevention groove.

An embodiment of the present invention can be described as follows.

A display device according to an embodiment of the present invention includes a substrate including a display area on which pixels are disposed and a non-display area surrounding the display area, an encapsulation film covering the display area and including an inorganic film, and a substrate in the non-display area. and a buffer layer spaced apart from the display area and in contact with an edge of the inorganic film.

According to some embodiments of the present invention, the encapsulation layer may include a first inorganic layer covering the display area, an organic layer formed on the first inorganic layer, and a second inorganic layer covering the organic layer, and the buffer layer may include the first inorganic layer. and at least one edge of the second inorganic layer.

According to some embodiments of the present invention, a dam may be further included in a non-display area to surround the display area and block a flow of the organic layer.

According to some embodiments of the present invention, the height of the buffer layer may be greater than the height of the dam.

According to some embodiments of the present invention, the buffer layer may be disposed outside the dam.

According to some embodiments of the present invention, each of the pixels may include a first electrode, a light emitting layer formed on the first electrode, and a second electrode formed on the light emitting layer, and a buffer layer may be disposed between the dam and the pixel and the buffer layer may not overlap the second electrode.

According to some embodiments of the present invention, the buffer layer may include a first buffer layer disposed between the dam and the pixel, and a second buffer layer disposed outside the dam.

According to some embodiments of the present invention, the first buffer layer may contact the edge of the first inorganic film, and the second buffer layer may contact the edge of the second inorganic film.

According to some embodiments of the present invention, a buffer layer may be disposed to surround the display area.

According to some embodiments of the present invention, the inorganic layer may cover a portion of the upper surface of the buffer layer.

According to some embodiments of the present invention, the non-display area may include a pad area including a pad, a dam may be disposed between the display area and the pad area, and the buffer layer may be disposed between the dam and the pad area. there is.

According to some embodiments of the present invention, a first power auxiliary line to which a voltage is applied from a pad may be included, and the buffer layer may be disposed on the first power auxiliary line.

According to some embodiments of the present invention, the buffer layer may include a third buffer layer and a fourth buffer layer disposed on the third buffer layer.

According to some embodiments of the present invention, a second power auxiliary line may be disposed between the third buffer layer and the fourth buffer layer and electrically connected to the first power auxiliary line through a contact hole penetrating the third buffer layer. can include

According to some embodiments of the present invention, a crack prevention groove may be formed in the buffer layer.

According to some embodiments of the present invention, the buffer layer may be formed of an organic material.

According to some embodiments of the present invention, the buffer layer may be formed of a plurality of island patterns.

According to some embodiments of the present invention, the second inorganic layer may be formed outside the first buffer layer.

A method of manufacturing a display device according to an embodiment of the present invention includes forming pixels in a display area on a substrate, forming a buffer layer in a non-display area, disposing a mask on the buffer layer, and forming an inorganic film to cover the display area. and removing the mask after forming.

According to some embodiments of the present invention, in the step of disposing the mask, the buffer layer and the mask may contact each other.

According to some embodiments of the present invention, in the step of disposing the mask, the mask may be disposed such that a portion of the upper surface of the buffer layer is exposed.

According to some embodiments of the present invention, forming the buffer layer in the non-display area may further include forming a dam in the non-display area.

According to some embodiments of the present invention, the height of the buffer layer may be greater than the height of the dam.

According to some embodiments of the present invention, the buffer layer may be disposed outside the dam.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device 110: display panel
111: first substrate 112: second substrate
120: dam 130: buffer layer
140: source drive IC 150: flexible film
160: circuit board 170: timing control unit
210: thin film transistor 211: active layer
212: gate electrode 213: source electrode
214: drain electrode 220: capacitor
221: lower electrode 222: upper electrode
230: gate insulating film 240: interlayer insulating film
250: protective film 260: planarization film
280: light emitting element 281: second electrode
282: first electrode 283: light emitting layer
284: bank 290: encapsulation
291: first inorganic layer 292: organic layer
293: second inorganic film

Claims (24)

a substrate including a display area on which pixels are disposed, and a non-display area including a pad area surrounding the display area and on which a pad is disposed;
an encapsulation film covering the display area and including an inorganic film;
a first power auxiliary line to which voltage is applied from the pad;
A buffer layer including a first buffer layer disposed in the non-display area and spaced apart from the display area, in contact with an edge of the inorganic layer, and disposed on the first power auxiliary line, and a second buffer layer disposed on the first buffer layer. ; and
and a second power auxiliary line disposed between the first buffer layer and the second buffer layer and electrically connected to the first power auxiliary line through a contact hole penetrating the first buffer layer. According to claim 1,
The encapsulation film,
a first inorganic layer covering the display area;
an organic layer formed on the first inorganic layer; and
A second inorganic layer covering the organic layer;
The buffer layer is in contact with an edge of at least one of the first inorganic layer and the second inorganic layer. According to claim 2,
The display device further includes a dam disposed in the non-display area to surround the display area and block flow of the organic layer. According to claim 3,
The display device, characterized in that the height of the buffer layer is greater than the height of the dam. According to claim 3,
The buffer layer is disposed outside the dam. According to claim 3,
Each of the pixels includes a first electrode, a light emitting layer formed on the first electrode, and a second electrode formed on the light emitting layer,
The buffer layer is disposed between the dam and the pixel, and the buffer layer does not overlap the second electrode. According to claim 3,
The buffer layer,
a third buffer layer disposed between the dam and the pixel; and
A display device including a fourth buffer layer disposed outside the dam. According to claim 7,
The third buffer layer contacts an edge of the first inorganic layer, and the fourth buffer layer contacts an edge of the second inorganic layer. According to claim 1,
The buffer layer is disposed to surround the display area. According to claim 1,
The inorganic film covers a portion of the upper surface of the buffer layer. According to claim 3,
The display device of claim 1 , wherein the dam is disposed between the display area and the pad area, and the buffer layer is disposed between the dam and the pad area. delete delete delete According to claim 1,
The buffer layer is a display device in which a crack prevention groove is formed. According to claim 1,
The buffer layer is a display device formed of an organic material. According to claim 1,
The buffer layer is formed of a plurality of island patterns. According to claim 8,
The second inorganic layer is formed outside the first buffer layer. forming pixels in a display area on a substrate and forming a buffer layer including a first buffer layer and a second buffer layer in a non-display area including a pad area including a pad;
disposing a mask on the buffer layer; and
Forming an inorganic film to cover the display area and then removing the mask;
Forming a buffer layer in the non-display area,
forming the first buffer layer on a first power auxiliary line formed in the non-display area and to which a voltage is applied from the pad;
forming a second power auxiliary line electrically connected to the first power auxiliary line through a contact hole penetrating the first buffer layer on the first buffer layer; and
and forming the second buffer layer on the second power auxiliary line. The method of claim 19, wherein disposing the mask comprises:
A method of manufacturing a display device in which the buffer layer and the mask contact each other. The method of claim 19, wherein disposing the mask comprises:
The method of manufacturing a display device, wherein the mask is disposed to expose a portion of the upper surface of the buffer layer. The method of claim 19 , wherein forming the buffer layer in the non-display area comprises:
The method of manufacturing a display device further comprising forming a dam in the non-display area. The method of claim 22,
The method of manufacturing a display device in which the height of the buffer layer is greater than the height of the dam. The method of claim 22,
The buffer layer is disposed outside the dam.

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