KR102455224B1 - Light Emitting Device - Google Patents

Abstract

An embodiment relates to a light emitting device, comprising: a light emitting structure in which a first semiconductor layer, an active layer, and a second semiconductor layer are stacked; a first electrode disposed on the first semiconductor layer; a second electrode disposed on the second semiconductor layer; and a passivation layer disposed on the first electrode and the first semiconductor layer to expose the second electrode, wherein roughness is disposed on an interface between the first semiconductor layer and the passivation layer.

Description

Light Emitting Device

The embodiment relates to a light emitting device.

Recently, a light emitting device display device using a plurality of light emitting devices as pixels has been widely used as a large display device for large outdoor billboards and outdoor events. In such a light emitting device display device, a plurality of light emitting devices are densely installed on the front surface of the main substrate, and a driving chip and a power supply device for driving the light emitting devices are installed on the rear side.

The light emitting device includes a light emitting structure, a first electrode, a second electrode, and a passivation layer.

The light emitting structure includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked, a first electrode is disposed on the first semiconductor layer, and a second electrode is disposed on the second semiconductor layer.

In addition, a passivation layer is disposed on the first electrode and the first semiconductor layer to expose the second electrode, and the active layer generates light by combining electrons transmitted through the first electrode and holes transmitted through the second electrode. It is a layer that can

In order to increase the sharpness of the light emitting device display device and improve image quality, the distance between the light emitting devices installed in the light emitting device display device is narrowed, and the number of the installed light emitting devices is increased.

In addition, as the distance between the light emitting devices becomes narrower, there is a problem in that the heat dissipation performance of the light emitting devices decreases, and power consumption for driving the light emitting devices increases as the number of the light emitting devices increases.

The embodiment has been devised to solve the above problems, and an object of the present invention is to provide a light emitting device capable of improving light extraction efficiency by forming roughness on the light emitting device.

In order to achieve the above object, the embodiment provides a light emitting structure in which a first semiconductor layer, an active layer, and a second semiconductor layer are stacked; a first electrode disposed on the first semiconductor layer; a second electrode disposed on the second semiconductor layer; and a passivation layer disposed on the first electrode and the first semiconductor layer to expose the second electrode, wherein roughness is disposed on an interface between the first semiconductor layer and the passivation layer. provide the element.

In an embodiment, the roughness may have a diameter of 3 nm to 4 nm.

In addition, a diffuse reflection layer may be disposed on the roughness.

In addition, the diffuse reflection layer may include at least one of silver (Ag) and aluminum (Al).

In addition, the height of the diffuse reflection layer may be lower than the height of the active layer.

In addition, the passivation layer may have a thickness of 300 nm to 500 nm.

In order to achieve the above object, another embodiment is a light emitting structure in which a first semiconductor layer, an active layer and a second semiconductor layer are stacked; a first electrode disposed on the first semiconductor layer; a second electrode disposed on the second semiconductor layer; and a passivation layer disposed on the first electrode and the first semiconductor layer to expose the second electrode, wherein roughness is disposed on an upper surface of the passivation layer in contact with the first semiconductor layer. provide the element.

In an embodiment, a diffuse reflection layer may be disposed on the roughness.

In addition, the diffuse reflection layer may include at least one of silver (Ag) and aluminum (Al).

Also, a height of the diffuse reflection layer may be lower than a height of the active layer.

According to the above-described embodiment, there is an effect of reducing power consumption for driving the light emitting device by improving light extraction efficiency by forming roughness on the light emitting device.

1 is a cross-sectional view illustrating a light emitting device according to a first embodiment.
2 is a cross-sectional view illustrating a light emitting device according to a second embodiment.
3 is a cross-sectional view illustrating a light emitting device according to a third embodiment.
4A to 4H are views illustrating a manufacturing process sequence of a light emitting device according to a third embodiment.
5 is a plan view illustrating a light emitting device according to a third embodiment.

Hereinafter, a preferred embodiment of the present invention that can specifically realize the above object will be described with reference to the accompanying drawings.

In the description of the embodiment according to the present invention, in the case where it is described as being formed on "on or under" of each element, on (above) or below (on) or under) includes both elements in which two elements are in direct contact with each other or one or more other elements are disposed between the two elements indirectly. In addition, when expressed as “up (up) or down (on or under)”, it may include not only an upward direction but also a downward direction based on one element.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not fully reflect the actual size.

1 is a cross-sectional view showing a light emitting device according to a first embodiment, FIG. 2 is a cross-sectional view showing a light emitting device according to a second embodiment, and FIG. 3 is a cross-sectional view showing a light emitting device according to a third embodiment.

1 to 3 , the light emitting devices 100A, 100B, and 100C according to the present embodiment include a light emitting structure 110 , a first electrode 120 , a second electrode 130 , and a passivation layer 140 . include

The light emitting structure 110 may include a first semiconductor layer 110a, an active layer 110b, and a second semiconductor layer 110c that are sequentially stacked.

The light emitting structure 110 may be formed by, for example, a metal organic chemical vapor deposition (MOCVD), a chemical vapor deposition (CVD), a plasma-enhanced chemical vapor deposition (PECVD), or molecular beam growth. It may be formed using a method such as Molecular Beam Epitaxy (MBE) or Hydride Vapor Phase Epitaxy (HVPE), but is not limited thereto.

The first semiconductor layer 110a may be implemented with a group III-V or group II-VI compound semiconductor, and may be doped with a first conductivity type dopant. The first semiconductor layer 110a is a semiconductor material having a composition formula of AlxInyGa(1-x-y)N (0≤≤x≤≤1, 0≤≤y≤≤1, 0≤≤x+y≤≤1), AlGaN , GaN, InAlGaN, AlGaAs, GaP, may be formed of any one or more of GaAs, GaAsP, AlGaInP.

When the first semiconductor layer 110a is an n-type semiconductor layer, the first conductivity-type dopant may include an n-type dopant such as Si, Ge, Sn, Se, Te, or the like. The first semiconductor layer 110a may be formed as a single layer or multiple layers.

The first semiconductor layer 110a is formed by injecting trimethyl gallium gas (TMGa), ammonia gas (NH3), nitrogen gas (N2), and silane gas (SiH4) including n-type impurities such as silicon (Si) into the chamber. can be formed.

A current diffusion layer 123 may be formed on the first semiconductor layer 110a of the light emitting structure. The current diffusion layer 123 may be an undoped GaN layer, but is not limited thereto.

An active layer 110b may be formed on the first semiconductor layer 110a.

The active layer 110b may be disposed between the first semiconductor layer 110a and the second semiconductor layer 110c.

The active layer 110b is a layer in which electrons and holes meet each other to emit light having an energy determined by an energy band unique to the active layer (light emitting layer) material. When the first semiconductor layer 110a is an n-type semiconductor layer and the second semiconductor layer 110c is a p-type semiconductor layer, electrons are injected from the first semiconductor layer 110a and from the second semiconductor layer 110c Holes may be injected.

The active layer 110b may include any one of a double-hetero structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure.

The active layer 110b uses a III-V group element compound semiconductor material to form a well layer and a barrier layer, for example, AlGaN/AlGaN, InGaN/GaN, InGaN/InGaN, AlGaN/GaN, InAlGaN/GaN, GaAs (InGaAs). /AlGaAs, GaP (InGaP) / may be formed of any one or more pair structure of AlGaP, but is not limited thereto. The well layer may be formed of a material having an energy band gap smaller than that of the barrier layer.

A conductive cladding layer (not shown) may be formed above and/or below the active layer 110b. The conductive cladding layer may be formed of a barrier layer of the active layer or a semiconductor having a wider bandgap than the bandgap. For example, the conductive clad layer may include GaN, AlGaN, InAlGaN, or a superlattice structure. In addition, the conductivity-type cladding layer may be doped with n-type or p-type.

The second semiconductor layer 110c may be formed of a semiconductor compound. The second semiconductor layer 110c may be implemented with a group III-V or group II-VI compound semiconductor, and may be doped with a second conductivity type dopant.

For example, the second semiconductor layer 110c is a semiconductor material having a composition formula of InxAlyGa1-x-yN (0≤≤x≤≤1, 0≤≤y≤≤1, 0≤≤x+y≤≤1) , AlGaN, GaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP may be formed of any one or more, and the second semiconductor layer 110c may be formed of AlxGa(1-x)N.

When the second semiconductor layer 110c is a p-type semiconductor layer, the second conductivity-type dopant may be a p-type dopant such as Mg, Zn, Ca, Sr, or Ba.

The second semiconductor layer 110c may be formed as a single layer or a multilayer, and the second semiconductor layer 110c is formed in a chamber with trimethyl gallium gas (TMGa), ammonia gas (NH3), nitrogen gas (N2), and magnesium (Mg). ), bisetyl cyclopentadienyl magnesium (EtCp2Mg) {Mg(C2H5C5H4)2} containing p-type impurities such as ) may be implanted to form a p-type GaN layer, but is not limited thereto.

When the second semiconductor layer 110c is a p-type semiconductor layer, a semiconductor having a polarity opposite to that of the second conductivity type, for example, an n-type semiconductor layer (not shown) may be formed on the second semiconductor layer 110c. . Accordingly, the light emitting structure 110 may be implemented as any one of an n-p junction structure, a p-n junction structure, an n-p-n junction structure, and a p-n-p junction structure.

An electron blocking layer (not shown) may be disposed adjacent to the active layer 110b between the active layer 110b and the second semiconductor layer 110c.

The electron blocking layer (not shown) may include AlGaN, and may be doped with a second conductivity type dopant.

In addition, the electron blocking layer (not shown) may be formed of an AlzGa(1-z)N/GaN (0≤≤z≤≤1) superlattice, but is not limited thereto. The electron blocking layer (not shown) can effectively block electrons that overflow by implanting p-type ions, and increase hole injection efficiency.

In addition, the first electrode 120 may be disposed on the first semiconductor layer 110a , and the second electrode 130 may be disposed on the second semiconductor layer 110c .

A conductive layer 115 may be disposed on the second semiconductor layer 110c of the light emitting device. In addition, the second electrode 130 may be formed on the second semiconductor layer 110c or the conductive layer 115 .

The conductive layer 115 may improve electrical characteristics of the second semiconductor layer 110c and may improve electrical contact with the second electrode 130 . The conductive layer 115 may be formed to have a plurality of layers or patterns, and the conductive layer 115 may be formed as a transparent electrode layer having transparency.

The conductive layer 115 is, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), IZTO (Indium Zinc Tin Oxide), IAZO (Indium Aluminum Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), IGTO ( Indium Gallium Tin Oxide), AZO (Aluminum Zinc Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO (Zinc Oxide), IrOx (Iridium Oxide), RuOx (Ruthenium Oxide), NiO (Nickel Oxide), RuOx / ITO, may be formed including at least one of Ni / IrOx / Au (Gold), but limited to these materials doesn't happen

A light extraction pattern may be formed on the conductive layer 115 . The light extraction pattern may be formed by wet etching or dry etching, and the light extraction efficiency of the light emitting structure may be improved.

In addition, the passivation layer 140 may be disposed on the first electrode 120 and the first semiconductor layer 110a so that the second electrode 130 is exposed.

The passivation layer 140 may be made of an insulating material, specifically, it may be made of an oxide or nitride, and more specifically, it may be made of a silicon oxide (SiO ₂ ) layer, an oxynitride layer, or an aluminum oxide layer.

The light emitting device according to the embodiment may be provided as a flip chip or a micro LED (Micro Light Emitting Device).

4A to 4H are views illustrating a manufacturing process sequence of a light emitting device according to a third embodiment.

As shown in FIG. 4A , the substrate 160 may be formed of a carrier wafer, a material suitable for semiconductor material growth. It may be formed of a material having excellent thermal conductivity, and may be a conductive substrate or an insulating substrate. For example, the substrate 160 may use at least one of sapphire (Al2O3), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga203, but is not limited thereto.

Meanwhile, in the case of forming a semiconductor layer of a GaN compound on the substrate 160 , a GaN substrate may be used as the same type of substrate. Since the GaN substrate can reduce the difference in lattice constant from the GaN compound semiconductor, high-quality epitaxial growth with low defect characteristics may be possible. GaN substrates may be polarizable, semi-polarizable or non-polarizable.

A light emitting structure 110 including a first semiconductor layer, an active layer, and a second semiconductor layer may be formed on the substrate 160 or the buffer layer (not shown).

In addition, a conductive layer 115 may be deposited on the second semiconductor layer of the light emitting device.

As shown in FIG. 4B, the upper surface of the first semiconductor layer 110a is mesa-etched by a thickness of 2um to 2.5um to leave a certain thickness of the first semiconductor layer 110a, and the conductive layer ( A top surface of the 115 and a top surface of the etched first semiconductor layer 110a may be exposed.

Referring to FIG. 4C , after the mesa etching as described above, the first semiconductor layer 110a may be subjected to isolation etching. Here, the first semiconductor layer 110a may be etched by a thickness of 1 μm to 1.5 μm to form a space in which a first electrode, which will be described later, is larger than the area of the conductive layer 115 .

As shown in FIG. 4D , the first electrode 120 may be disposed on an isolation-etched first semiconductor layer.

Here, the first electrode 120 includes at least one of aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), and gold (Au) to have a single-layer or multi-layer structure. can be

Referring to FIG. 4E , the passivation layer 140 may be disposed on the first electrode and the first semiconductor layer by exposing a second semiconductor layer on which a second electrode to be described later will be disposed. In addition, the passivation layer 140 may be made of an insulating material, specifically, it may be made of an oxide or nitride, and more specifically, it may be made of a silicon oxide (SiO ₂ ) layer, an oxynitride layer, and an aluminum oxide layer.

Referring to FIG. 1 , roughness 150 may be disposed on the interface 145 between the first semiconductor layer 110a and the passivation layer 140 .

Here, the roughness may be disposed between the first electrode 120 and the second electrode 130 spaced apart, and the distance between the first electrode 120 and the second electrode 130 may be 15 nm to 30 nm. have. In addition, when the distance between the first electrode 120 and the second electrode 130 is less than 15 nm, the area where the roughness is arranged is narrowed, so that there is a limit in increasing the light extraction efficiency, and the first electrode 120 and the second electrode 130 are limited. If the distance between the two electrodes 130 is greater than 30 nm, there is a problem in that a space for arranging the second electrode in the second semiconductor layer becomes narrow. However, the distance between the first electrode and the second electrode is not limited thereto as long as a roughness is formed to improve light extraction efficiency, and a space for arranging the second electrode is secured in the second semiconductor layer.

In the first embodiment, the roughness 150 may be formed by etching the passivation layer 140 to a predetermined thickness, and the roughness 150 may have a diameter of 3 nm to 4 nm. In addition, the interval at which the roughness 150 is arranged may be 1 nm to 2 nm, and the height of the lowest point and the highest point of the roughness may be 200 nm to 700 nm, but the shape of the roughness, the arrangement interval, and the height of the light emitting device It may be arranged differently depending on the size of the passivation layer or the thickness of the passivation layer.

The passivation layer 140 may have a thickness of 300 nm to 500 nm.

Here, the size of the roughness 150 refers to the thickness of the passivation layer etched and may be formed in a ratio of 3:1 to the thickness of the passivation layer, but is not limited thereto.

If the thickness of the roughness 150 is too small, it is difficult to arrange a diffuse reflection layer, which will be described later, and if the thickness of the roughness 150 is too large, the thickness of the passivation layer becomes thin and thus the light emitting device cannot be protected.

In addition, a diffuse reflection layer 155 may be disposed on the roughness 150 . Also, the diffuse reflection layer 155 may include at least one of silver (Ag) and aluminum (Al).

Also, in order to induce diffuse reflection of light emitted from the light emitting device in the direction of the first semiconductor layer, the height at which the diffuse reflection layer 155 is positioned may be lower than the height of the active layer 110b.

Referring to FIG. 2 , roughness 150 may be disposed on the interface 145 between the first semiconductor layer 110a and the passivation layer 140 . In the second embodiment, the first electrode 120 . ) after the first semiconductor layer 110a is disposed, the roughness 150 may be disposed on the first semiconductor layer 110a before the passivation layer 140 is deposited.

The roughness 150 may be formed by etching the first semiconductor layer 110a to a predetermined thickness, and the roughness 150 may have a diameter of 3 nm to 4 nm.

The passivation layer 140 may have a thickness of 1500 nm to 3000 nm.

Here, the size of the roughness 150 refers to the thickness of the passivation layer etched and may be formed in a ratio of 3:1 to the thickness of the passivation layer, but is not limited thereto.

If the thickness of the roughness 150 is too small, it is difficult to arrange a diffuse reflection layer, which will be described later, and if the thickness of the roughness 150 is too large, the thickness of the passivation layer becomes thin and thus the light emitting device cannot be protected.

In addition, a diffuse reflection layer 155 may be disposed on the roughness 150 . Also, the diffuse reflection layer 155 may include at least one of silver (Ag) and aluminum (Al).

Also, in order to induce diffuse reflection of light emitted from the light emitting device in the direction of the first semiconductor layer, the height at which the diffuse reflection layer 155 is positioned may be lower than the height of the active layer 110b.

Referring to FIG. 3 , in the third embodiment, roughness 150 may be disposed on the upper surface of the passivation layer 140 in contact with the first semiconductor layer 110a.

Accordingly, in the third embodiment, the roughness 150 may be formed by etching the top surface of the passivation layer 140 in contact with the first semiconductor layer 110a after the passivation layer 140 is disposed.

In addition, the diffuse reflection layer 155 may be disposed on the roughness 150 , and the diffuse reflection layer 155 may include at least one of silver (Ag) and aluminum (Al).

Also, in order to induce diffuse reflection of light emitted from the light emitting device in the direction of the first semiconductor layer, the height at which the diffuse reflection layer 155 is positioned may be lower than the height of the active layer 110b.

5 is a plan view illustrating a light emitting device according to a third embodiment.

4E and 5 , the diffuse reflection layer 155 may be disposed on the roughness formed on the passivation layer 140 of the light emitting device 100C. In such a structure of the light emitting device, the roughness 150 disposed on the passivation layer 140 changes the optical path of light emitted from the light emitting device to improve light extraction efficiency, and the diffuse reflection layer 155 is It is possible to increase light extraction by inducing diffuse reflection of

As shown in FIG. 4F , the second electrode 130 may be disposed on the second semiconductor layer.

Here, the second electrode 130 includes at least one of aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), copper (Cu), and gold (Au) to have a single-layer or multi-layer structure. can be

Referring to FIG. 4G , the metal substrate 170 may be disposed to be connected to the first electrode and the second electrode. In addition, a conductive ball (not shown) may be disposed between the first electrode and the second electrode and the metal substrate, so that the first electrode and the second electrode may be connected to the metal substrate.

Referring to FIG. 4H , after the bonding process of the metal substrate 170 is performed, the sapphire substrate 160 may be separated from the light emitting structure.

Here, the substrate 160 may be separated from the light emitting structure by a laser lift-off (LLO) method using a laser.

As an example of the laser lift-off method, when excimer laser light having a wavelength of a certain region is focused and irradiated in the direction of the substrate 160 , thermal energy is concentrated at the interface between the substrate 160 and the light emitting structure, and the interface becomes gallium. Separation of the substrate 110 occurs instantaneously at a portion through which the laser light passes while being separated into and nitrogen molecules.

According to the above-described embodiment, by improving light extraction efficiency by forming roughness in the light emitting device, power consumption for driving the light emitting device can be reduced.

In addition, since the number of light emitting devices installed in the display device can be reduced, there is an effect that can reduce the cost of manufacturing the display device.

The above-described light emitting device is provided as a light emitting device array in which a plurality of light emitting devices are disposed to form pixels in various display devices, and may also be used as a light source of a lighting device.

In particular, when the FPCB is used as a circuit board, it can be used as a light source of a wearable device such as a smart watch by implementing a bendable light emitting element array due to the flexibility of the FPCB.

The smart watch may perform pairing with an external digital device, and the external digital device may be a digital device capable of communication connection with the smart watch, and may include, for example, a smartphone, a laptop computer, and Internet Protocol Television (IPTV). can

The above-described light emitting device array can be used as a light source for the smart watch, and can be worn on the wrist due to the flexibility of the FPCB, and fine pixels can be implemented due to the fine size of the light emitting device.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the present invention, and those of ordinary skill in the art to which the present invention pertains are not exemplified above in the range that does not depart from the essential characteristics of the present embodiment. It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And the differences related to these modifications and applications should be construed as being included in the scope of the present invention defined in the appended claims.

100A, 100B, 100C: light emitting device 110: light emitting structure
110a: first semiconductor layer 100b: active layer
100c: second semiconductor layer 120: first electrode
130: second electrode 140: passivation layer
145: boundary 150: roughness
155: diffuse reflection layer

Claims (10)

delete a light emitting structure in which a first semiconductor layer, an active layer, and a second semiconductor layer are stacked;
a first electrode disposed on the first semiconductor layer;
a second electrode disposed on the second semiconductor layer; and
a passivation layer disposed on the first electrode and the first semiconductor layer such that the second electrode is exposed;
Roughness is disposed on an interface between the first semiconductor layer and the passivation layer or on an upper surface of the passivation layer in contact with the first semiconductor layer,
A light emitting device in which a diffuse reflection layer including at least one of silver (Ag) and aluminum (Al) is disposed on the roughness. 3. The method of claim 2,
A height of the diffuse reflection layer is lower than a height of the active layer. a light emitting structure in which a first semiconductor layer, an active layer, and a second semiconductor layer are stacked;
a first electrode disposed on the first semiconductor layer;
a second electrode disposed on the second semiconductor layer; and
a passivation layer disposed on the first electrode and the first semiconductor layer so that the second electrode is exposed;
Roughness is disposed on an interface between the first semiconductor layer and the passivation layer or on an upper surface of the passivation layer in contact with the first semiconductor layer,
A diffuse reflection layer is disposed on the roughness,
The height of the diffuse reflection layer is arranged lower than the height of the active layer,
The roughness is a light emitting device disposed to be spaced apart from the second electrode. delete delete delete delete delete delete

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