KR102449478B1 - Display apparatus - Google Patents

Abstract

A display device according to an example of the present application includes a buffer layer provided on a substrate, a thin film transistor array layer including at least one thin film transistor arranged on the buffer layer, and a buffer layer and a thin film transistor array layer while being disposed on the thin film transistor array layer. By including a protective layer surrounding the side, it is possible to improve the reliability of the display panel by preventing the film from floating and side permeation.

Description

display device {DISPLAY APPARATUS}

This application relates to a display device.

In addition to the display screen of a television or monitor, the display device is widely used as a display screen of a notebook computer, a tablet computer, a smart phone, a portable display device, a portable information device, and the like.

A liquid crystal display device and an organic light emitting display device display an image by using a transistor (Thin Film Transistor) as a switching element. Since the liquid crystal display is not a self-luminous method, an image is displayed using light irradiated from a backlight unit disposed under the liquid crystal display panel. Since the liquid crystal display has a backlight unit, there is a limitation in design, and luminance and response speed may be reduced. Since the organic light emitting diode display includes organic materials, it is vulnerable to moisture, and thus reliability and lifespan may be deteriorated.

Recently, research and development of an organic light emitting display device using a micro light emitting device has been progressed, and since the organic light emitting display device has high image quality and high reliability, it is in the spotlight as a next-generation display.

A conventional display apparatus includes a plurality of panel areas on a carrier glass substrate, forms a display panel for each of the plurality of panel areas, and then separates each of the plurality of display panels through a CPS process. However, the conventional display device has a problem in that the surface of the substrate is exposed in the process of performing the CPS process, so that a film lifting phenomenon appears at the interface between the substrate and the buffer layer. In addition, the conventional display device has a problem of deteriorating the reliability of the display panel by exposing the side surfaces of the buffer layer and the inorganic film in the process of performing the CPS process, thereby generating dark spots in the outer part due to side permeation.

The present application makes it a technical task to prevent film lifting that may occur at the interface between the substrate and the buffer layer by covering the surface of the substrate by leaving the protective layer remaining in the process of performing the CPS process.

In addition, the present application is a technical task to prevent the occurrence of dark spots in the outer portion of the display panel by covering the side of the protective layer through the metal layer to prevent moisture permeation that may occur on the side of the buffer layer and the thin film transistor array layer. .

In addition, the present application is a technical task to improve the reliability of the display panel by double sealing the surface of the substrate and the buffer layer and the side of the thin film transistor array layer through the protective layer and the metal layer, thereby preventing film lifting and side moisture permeation. .

The display device according to the present application provides a buffer layer provided on a substrate, a thin film transistor array layer including at least one thin film transistor arranged on the buffer layer, and a thin film transistor array layer disposed on the buffer layer and the thin film transistor array layer to surround the side surfaces of the buffer layer and the thin film transistor array layer. a protective layer.

Other example specifics are included in the detailed description and drawings.

The display device according to the present application may prevent film lifting that may occur at the interface between the substrate and the buffer layer by covering the surface of the substrate by leaving the protective layer remaining in the process of performing the CPS process.

The display device according to the present application covers the side surface of the protective layer through the metal layer, thereby preventing moisture permeation that may occur on the side surface of the buffer layer and the thin film transistor array layer, thereby preventing dark spots from occurring in the outer portion of the display panel.

The display device according to the present application can improve the reliability of the display panel by double sealing the surface of the substrate and the side surface of the buffer layer and the thin film transistor array layer through the protective layer and the metal layer, thereby preventing film lifting and side permeation.

In addition to the effects of the present application mentioned above, other features and advantages of the present application will be described below or will be clearly understood by those of ordinary skill in the art to which this application belongs from the description and description.

1 is a plan view illustrating a plurality of display devices provided on a carrier glass substrate in a process of performing a CPS process in a display device according to an example of the present application.
FIG. 2 is a cross-sectional view taken along line II′ shown in FIG. 1 in the display device according to an example of the present application.
3 is a cross-sectional view illustrating a display device according to an example of the present application.
4A to 4F are process cross-sectional views schematically illustrating a method of manufacturing a display device according to an example of the present application, which is a process cross-sectional view taken along line A of FIG. 2 .

Advantages and features of the present application and methods of achieving them will become apparent with reference to the examples described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the examples disclosed below, but will be implemented in various different forms, and only these examples allow the disclosure of the present invention to be complete, and to those of ordinary skill in the art to which the present invention pertains. It is provided to fully indicate the scope of the invention, and the invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the examples of the present application are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present application, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present application, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in the present application are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

In describing the components of the present application, terms such as first and second may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected,” “coupled,” or “connected” through another component.

Accordingly, the display device in the present application may include a narrow display device itself such as an LCM, an OLED module, etc., and an application product including an LCM, an OLED module, or the like, or a set device that is an end-user device.

For example, when the display panel is an organic light emitting (OLED) display panel, it may include a plurality of gate lines and data lines, and pixels formed at intersections of the gate lines and the data lines. In addition, an array substrate including a thin film transistor as a device for selectively applying a voltage to each pixel, an organic light emitting device (OLED) layer on the array substrate, and an encapsulation substrate disposed on the array substrate to cover the organic light emitting device layer Alternatively, it may be configured to include an encapsulation substrate or the like. The encapsulation substrate may protect the thin film transistor and the organic light emitting device layer from external impact, and may prevent penetration of moisture or oxygen into the organic light emitting device layer. In addition, the layer formed on the array substrate may include an inorganic light emitting layer, for example, a nano-sized material layer or quantum dots.

In addition, the display panel may further include a backing such as a metal plate attached to the display panel. It is not limited to the metal plate, and other structures may be included.

Each feature of the various examples of the present application may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each example may be implemented independently of each other or may be implemented together in a related relationship. .

Hereinafter, an example of the present application will be described with reference to the accompanying drawings and examples.

1 is a plan view illustrating a plurality of display devices provided on a carrier glass substrate in a process of performing a CPS process in a display device according to an example of the present application.

Referring to FIG. 1 , the carrier glass substrate 10 may include a plurality of panel regions. Here, each of the plurality of panel areas corresponds to an area for manufacturing one display apparatus 100 . Accordingly, each of the plurality of display apparatuses 100 may be provided in each of the plurality of panel areas provided on the carrier glass substrate 10 . Specifically, each of the plurality of display apparatuses 100 may be separated through a CPS (Cutting with Penetrable Scriber) process after a plurality of layers are deposited through the same process on the carrier glass substrate 10 . In addition, when the CPS process is completed, the carrier glass substrate 10 may be separated from the first substrate 110 by the release of the sacrificial layer by the laser release process.

FIG. 2 is a cross-sectional view taken along line II′ shown in FIG. 1 in the display device according to an example of the present application.

Referring to FIG. 2 , the display device 100 includes a first substrate 110 , a buffer layer 120 , a light blocking layer 130 , a pad unit 140 , a thin film transistor array layer, a protective layer 300 , and a planarization layer ( 410 , a bank 420 , an organic light emitting diode E, a filling layer 460 , a dam 470 , a metal layer 500 , and a second substrate 600 .

The first substrate 110 is a base substrate and may be a flexible substrate. For example, the first substrate 110 may include a transparent polyimide material. Considering that a high-temperature deposition process is performed for the first substrate 110 made of polyimide, polyimide having excellent heat resistance that can withstand high temperatures may be used. The first substrate 110 made of polyimide may be formed by curing a polyimide resin coated to a predetermined thickness on the front surface of the sacrificial layer 20 provided on the carrier glass substrate 10 . Here, the carrier glass substrate 10 is formed by the release of the sacrificial layer 20 by the laser release process after the first substrate 110 and the second substrate 600 are bonded and the CPS process is completed. 110) can be isolated.

The buffer layer 120 may be provided on the first substrate 110 . The buffer layer 120 may be formed over the entire surface of the first substrate 110 in order to block moisture from penetrating into the thin film transistor array layer through the first substrate 110 . The buffer layer 120 may be formed by stacking a plurality of inorganic layers. For example, the buffer layer 120 may be formed as a multilayer in which one or more inorganic layers of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), and a silicon oxynitride layer (SiON) are stacked.

The buffer layer 120 may include a plurality of buffer layers. According to an example, the buffer layer 120 may include a first buffer layer 121 and a second buffer layer 123 . The first buffer layer 121 may be provided on the first substrate 110 , and the second buffer layer 123 may cover the first buffer layer 121 and the light blocking layer 130 . Each of the first and second buffer layers 121 and 123 may be sequentially deposited on the first substrate 110 through a CVD deposition method. Since the buffer layer 120 includes the first and second buffer layers 121 and 123 , the water vapor transmission rate (WVTR) of the panel may be improved.

The light blocking layer 130 may be provided in a region overlapping the semiconductor layer 210 of the thin film transistor T on the first buffer layer 121 . For example, the light blocking layer 130 may be formed by depositing a metal on the first buffer layer 121 and then performing exposure patterning. The light blocking layer 130 may be formed to overlap the semiconductor layer 131 of the thin film transistor T, thereby protecting the semiconductor layer 131 from external light. According to an example, the light blocking layer 130 may include a lower light blocking layer 131 and an upper light blocking layer 133 .

The lower light blocking layer 131 may be formed between the first buffer layer 121 and the upper light blocking layer 133 to enhance adhesion between the first buffer layer 121 and the upper light blocking layer 133 . In addition, the lower light blocking layer 131 may prevent the lower surface of the upper light blocking layer 133 from being corroded.

The upper light blocking layer 133 may be formed on the upper surface of the lower light blocking layer 131 . Specifically, the upper light blocking layer 133 may be made of a metal having a relatively low resistance compared to the lower light blocking layer 131 . In addition, the upper light blocking layer 133 may be formed to be thicker than the lower light blocking layer 131 in order to reduce the overall resistance of the light blocking layer 130 .

The pad unit 140 may be disposed on the first buffer layer 121 to be spaced apart from the light blocking layer 130 . For example, the pad part 140 may be formed by depositing a metal on the first buffer layer 121 and then performing exposure patterning. According to an example, the pad part 140 may be provided on the same layer as the light blocking layer 130 to be spaced apart from each other. Specifically, the pad part 140 is provided in the non-display area on the first buffer layer 121 , and the light blocking layer 130 overlaps the semiconductor layer 210 of the thin film transistor T on the first buffer layer 121 . It may be provided in an area where Accordingly, the pad part 140 and the light blocking layer 130 may be simultaneously provided in the non-display area on the first buffer layer 121 and the area overlapping the semiconductor layer 210 through a single patterning process.

The thin film transistor array layer may include at least one thin film transistor T arranged on the buffer layer 120 . According to an example, the thin film transistor array layer may form a display area of the first substrate 110 by arranging a plurality of thin film transistors T on the buffer layer 120 .

The thin film transistor T may include a semiconductor layer 210 , a gate insulating layer 220 , a gate electrode 230 , an interlayer insulating layer 240 , a source electrode 250 , and a drain electrode 260 .

The semiconductor layer 210 may be provided in the display area of the first substrate 110 on the buffer layer 120 . The semiconductor layer 210 may be disposed to overlap the gate electrode 230 , the source electrode 250 , and the drain electrode 260 . The semiconductor layer 210 may directly contact the source electrode 250 and the drain electrode 260 , and may face the gate electrode 230 with the gate insulating layer 220 interposed therebetween. According to an example, a portion of the semiconductor layer 210 may be formed of a semiconductor material undoped with a dopant, and another portion of the semiconductor layer 210 may be formed of a semiconductor material doped with a dopant.

The gate insulating layer 220 may be provided on the channel region of the semiconductor layer 210 . Specifically, the gate insulating layer 220 may be disposed on the semiconductor layer 210 , and may insulate the semiconductor layer 210 and the gate electrode 230 .

The gate electrode 230 is provided on the gate insulating layer 220 and may be formed together with the gate line. Specifically, the gate electrode 230 may overlap the central region of the semiconductor layer 210 with the gate insulating layer 220 interposed therebetween. The gate electrode 230 may be pattern-formed on the gate insulating layer 220 to overlap the channel region of the semiconductor layer 210 . The gate electrode 230 may serve as a mask to prevent the channel region of the semiconductor layer 210 from being conductive by the dry etching gas during the patterning process of the gate insulating layer 220 using the dry etching process.

The interlayer insulating layer 240 may be provided on the gate electrode 230 . Specifically, the interlayer insulating layer 240 may be provided on the entire surface of the display area including the gate electrode 230 . The interlayer insulating layer 240 may function to protect the thin film transistor T. In the interlayer insulating layer 240 , a corresponding region may be removed so that the semiconductor layer 210 and the source electrode 250 or the drain electrode 260 contact each other. For example, the insulating interlayer 240 may include a first contact hole through which the source electrode 250 passes and a second contact hole through which the drain electrode 260 passes. According to an example, the top and side surfaces of the interlayer insulating layer 240 may be surrounded by the passivation layer 300 . In addition, the upper surface and the side surface of the interlayer insulating film 240 are double sealed through the protective layer 300 and the metal layer 500 , so that the display device 100 can prevent lateral moisture permeation through the interlayer insulating film 240 . .

The source electrode 250 and the drain electrode 260 may be provided on the interlayer insulating layer 240 to be spaced apart from each other. Specifically, the source electrode 250 and the drain electrode 260 may be formed together with a data line and a power supply line. The source electrode 250 is in contact with one end of the semiconductor layer 210 through the first contact hole provided in the interlayer insulating layer 240 , and the second contact hole of the organic light emitting device E through the third contact hole of the protective layer 300 . The first electrode 430 may be in direct contact. In addition, the drain electrode 260 may contact the other end of the semiconductor layer 210 through a second contact hole provided in the interlayer insulating layer 240 . Top surfaces of the source electrode 250 and the drain electrode 260 may be protected by the passivation layer 300 .

The protective layer 300 may be disposed on the thin film transistor array layer and cover the buffer layer 120 , the side surfaces of the thin film transistor array layer, and the upper surface of the outermost portion 110a of the first substrate 110 . Specifically, the side surface 300b of the passivation layer 300 may be in contact with the side surfaces of the first and second buffer layers 121 and 123 and the interlayer insulating layer 240 , and the end portion 300c of the passivation layer 300 . may be in contact with the upper surface of the outermost portion 110a of the first substrate 110 . Accordingly, the protective layer 300 covers the upper and side surfaces of the thin film transistor array layer, the side surface of the buffer layer 120 , and the upper surface of the outermost portion 110a of the first substrate 110 , thereby protecting the thin film transistor T. can be protected, and by preventing surface exposure of the first substrate 110 , a film lifting phenomenon that may occur at the interface between the first substrate 110 and the buffer layer 120 can be prevented. According to an example, the protective layer 300 may be made of an inorganic insulating material such as silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof, but is not limited thereto.

According to an example, the end portion 300c of the protective layer 300 may be depressed along the CPS line. Specifically, the buffer layer 120 and the thin film transistor array layer may be sequentially stacked on the first substrate 110 . In addition, a portion of the buffer layer 120 and the thin film transistor array layer may be patterned to form a CPS line on the carrier glass substrate 10 . In this case, the outermost portion 110a of the first substrate 110 may be temporarily exposed through a patterning process. Accordingly, the protective layer 300 covers the upper surfaces of the interlayer insulating layer 240 , the source electrode 250 , and the drain electrode 260 , and the end portion 300c of the protective layer 300 is patterned along the CPS line. can be submerged in As a result, the side surface 300b of the passivation layer 300 covers the side surfaces of the first and second buffer layers 121 and 123 and the interlayer insulating layer 240 , and the end portion 300c of the passivation layer 300 has the first By covering the upper surface of the outermost portion 110a of the substrate 110 , the surface of the first substrate 110 may be prevented from being exposed, and thus the interface between the first substrate 110 and the buffer layer 120 may be entirely surrounded. That is, the protective layer 300 may prevent a film lifting phenomenon occurring at the interface between the first substrate 110 and the buffer layer 120 .

According to one example, the protective layer 300 is recessed along the CPS line, the upper surface of the interlayer insulating film 240, the side surfaces of the buffer layer 120 and the interlayer insulating film 240, and the outermost portion of the first substrate 110 ( 110a) may be bent twice to cover the upper surface. Here, the bent portion between the side surface 300b and the end portion 300c of the protective layer 300 may entirely surround the interface between the first substrate 110 and the buffer layer 120 . Accordingly, the protective layer 300 may prevent a film lifting phenomenon occurring at the interface between the first substrate 110 and the buffer layer 120 .

According to an example, since the protective layer 300 is formed after the first and second buffer layers 121 and 123 and the interlayer insulating film 240 positioned on the CPS line are removed through a patterning process, the protective layer 300 positioned on the CPS line. The end portion 300c of the layer 300 is not removed through the patterning process. Accordingly, the outermost portion 110a of the first substrate 110 may not be exposed through the end portion 300c of the passivation layer 300 , and the end portion 300c of the passivation layer 300 may be disposed on the first substrate. It is possible to continue to protect the outermost portion (110a) of (110). Accordingly, the protective layer 300 may prevent a film lifting phenomenon that may occur at the interface between the first substrate 110 and the buffer layer 120 .

A region of the protective layer 300 may be removed so that the first electrode 430 and the source electrode 250 contact each other. For example, the protective layer 300 may include a third contact hole through which the first electrode 430 passes.

The planarization layer 410 may be provided on the passivation layer 300 to overlap with at least one thin film transistor T to planarize an upper end of the passivation layer 300 . The planarization layer 410 may stack the first electrode 430 and the bank 420 in the planarized area. In addition, a corresponding region of the planarization layer 410 may be removed so that the first electrode 430 and the source electrode 250 contact each other. For example, the planarization layer 410 may include a fourth contact hole through which the first electrode 430 passes. Here, the third contact hole of the protective layer 300 and the fourth contact hole of the planarization layer 410 may be connected to each other so that the first electrode 430 passes therethrough.

The bank 420 may be provided on the planarization layer 410 . The bank 420 may be provided between the first electrodes 430 adjacent to each other to partition the first electrodes 430 . Accordingly, the bank 420 may electrically insulate the first electrodes 430 adjacent to each other. The bank 420 may be made of an organic insulating material, for example, polyimides resin, acrylic resin, benzocyclobutene (BCB), or the like, but is not limited thereto.

The organic light emitting diode E may be provided on the planarization layer 410 and may be electrically connected to the thin film transistor T. The organic light emitting device E may include a first electrode 430 , an organic light emitting layer 440 , and a second electrode 450 .

The first electrode 430 may be provided on the planarization layer 410 . Specifically, the first electrode 430 may be provided in the light emitting area of each of the plurality of pixels. Here, the light emitting area of each of the plurality of pixels is a portion other than the edge portion of the first electrode 430 , and may be defined by the bank 420 formed on the planarization layer 410 . That is, the bank 420 is formed to cover the edge portion of the first electrode 430 and the planarization layer 410 , thereby exposing the remaining portions except for the edge portion of the first electrode 430 . In addition, the first electrode 430 may be in contact with the source electrode 250 of the thin film transistor T through the third contact hole provided in the protective layer 300 and the fourth contact hole provided on the planarization layer 410 . have. According to an example, the first electrode 430 may serve as an anode by being made of a transparent conductive material such as ITO, IZO, ZnO, or In2O3 having a large work function value. Accordingly, the first electrode 430 may correspond to the anode electrode of the organic light emitting diode E.

The organic emission layer 440 may be provided on the first electrode 430 and the bank 420 . Specifically, the organic light emitting layer 440 may be formed to be common to all pixels without being divided for each pixel area. According to an example, the organic light emitting layer 440 may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. In addition, the organic light-emitting layer 440 may further include at least one functional layer for improving the light-emitting efficiency and lifespan of the light-emitting layer.

The second electrode 450 may be provided on the organic emission layer 440 . The second electrode 450 may be implemented in the form of an electrode common to all pixels without being divided by pixel area. When a voltage is applied to the first electrode 430 and the second electrode 450 together, holes and electrons move to the organic emission layer 440 through the hole transport layer or the electron transport layer, respectively, and combine with each other in the organic emission layer 440 to emit light. can do. According to an example, the second electrode 450 may function as a cathode of the organic light emitting display device, and an opaque metal formed of Li, Ca, LiF/Ca, LiF/Al, Al, Mg, or a compound thereof. It can be implemented with a material. Accordingly, the second electrode 450 may correspond to a cathode electrode of the organic light emitting diode E.

The filling layer 460 may fill a space between the first substrate 110 and the second substrate 600 . Specifically, the filling layer 460 is provided on the entire upper end of the second electrode 450 and does not spread to the outside of the display apparatus 100 by the dam 470 . The filling layer 460 may prevent the penetration of moisture, etc., which may be introduced from the outside, to prevent deterioration of the organic light emitting layer 440 . Accordingly, the filling layer 460 may be disposed between the first substrate 110 and the second substrate 600 to prevent light loss and increase the adhesive force between the first substrate 110 and the second substrate 600 . have.

The dam 470 may be interposed between the first substrate 110 and the second substrate 600 . The dam 470 may be implemented in the form of a frame surrounding the display area. The dam 470 may partially overlap the planarization layer 410 and the second electrode 450 , but this is not necessarily the case. Accordingly, the dam 470 may prevent the filling layer 460 from spreading to the outside of the display apparatus 100 . In addition, the dam 470 may bond the first substrate 110 and the second substrate 600 to each other.

The metal layer 500 may cover the upper edge 300a, the side surface 300b, and the end portion 300c of the protective layer 300 while overlapping the edge of the first substrate 110 . Specifically, the metal layer 500 is formed on the carrier glass substrate 10 when the first substrate 110 , the buffer layer 120 , the thin film transistor array layer, the protective layer 300 , and the planarization layer 410 are stacked. 1 It may be provided at the edge of the substrate 110 . Here, since the metal layer 500 is disposed on top of the protective layer 300 recessed along the CPS line, it may be formed along the recessed shape of the protective layer 300 . Accordingly, the metal layer 500 may be recessed along the CPS line, similarly to the end portion 300c of the protective layer 300 recessed along the CPS line. For example, the metal layer 500 may be bent twice to cover the top edge 300a , the side surface 300b , and the end portion 300c of the protective layer 300 . Accordingly, the metal layer 500 may prevent side permeation of the display apparatus 100 .

According to an example, the metal layer 500 may include an upper end portion 500a, a side portion 500b, and an end portion 500c. The upper end portion 500a of the metal layer is disposed on the upper edge 300a of the protective layer, the side portion 500b of the metal layer surrounds the side surface 300b of the protective layer, and the end portion 500c of the metal layer is the protective layer. It may be disposed on the end portion (300c) of the. Here, the metal layer 500 may cover the upper edge 300a, the side surface 300b, and the end portion 300c of the protective layer 300 , and the protective layer 300 includes the buffer layer 120 and the thin film transistor. The side surface of the array layer and the upper surface of the outermost part 110a of the first substrate 110 may be covered. Accordingly, the end portion 500c of the metal layer may be disposed lower than the thin film transistor array layer. In other words, the distance between the end portion 500c of the metal layer and the first substrate 110 may be closer than the distance between the thin film transistor array layer and the first substrate 110 . For example, the end portion 500c of the metal layer may be disposed on the same layer as the light blocking layer 130 , but is not limited thereto.

The metal layer 500 may double seal the side surfaces of the buffer layer 120 and the thin film transistor array layer and the upper surface of the outermost portion 110a of the first substrate 110 together with the protective layer 300 . Specifically, the protective layer 300 covers the upper surface of the thin film transistor array layer and covers the side surface of the interlayer insulating film 240 , the side surfaces of the first and second buffer layers 121 and 123 , and the outermost portion of the first substrate 110 . The upper surface of the portion 110a may be covered, and the metal layer 500 may cover the upper surface edge 300a, the side surface 300b, and the end portion 300c of the protective layer 300 . Accordingly, the metal layer 500 and the protective layer 300 are formed on the side surface of the interlayer insulating film 240 , the side surfaces of the first and second buffer layers 121 and 123 , and the outermost portion 110a of the first substrate 110 . By double sealing the upper surface of the , it is possible to prevent lateral moisture permeation through the buffer layer 120 and the interlayer insulating film 240 . Therefore, the display device prevents lateral permeation through the buffer layer 120 and the interlayer insulating film 240 through the metal layer 500 and the protective layer 300, thereby preventing the occurrence of dark spots in the outer portion of the display panel, It is possible to improve the reliability of the display panel.

The metal layer 500 may be formed of the same material and the same thickness as the first electrode 430 . Specifically, the metal layer 500 is provided to surround the top edge 300a, the side surface 300b, and the end portion 300c of the protective layer 300 in the non-display area on the first substrate 110 at the same time, The first electrode 430 may be provided in a region overlapping the thin film transistor T on the planarization layer 410 . Accordingly, the metal layer 500 and the first electrode 430 may be provided to be electrically connected to the source electrode 250 of the thin film transistor T while surrounding the protective layer 300 through a single patterning process. As a result, the display device 100 has a metal layer 500 and a thin film transistor (T) surrounding the top edge 300a, the side surface 300b, and the end portion 300c of the protective layer 300 through a single patterning process. ), by providing the first electrode 430 connected to the source electrode 250 at the same time, the process cost and time can be shortened and reliability can be improved by preventing lateral moisture permeation.

The second substrate 600 may be provided on the entire top of the filling layer 460 . The second substrate 600 may be disposed on the first substrate 110 to block the thin film transistor T and the organic light emitting device E provided on the first substrate 110 from external moisture, air, etc. have. According to an example, the second substrate 600 is positioned to face the first substrate 110 , and the first substrate 110 and the second substrate 600 are attached to a sealing member (not shown) disposed along the edge thereof. can be joined to each other by For example, the second substrate 600 may be a glass substrate or a plastic substrate.

The color filter 610 may be disposed between the filling layer 460 and the second substrate 600 . The color filter 610 may be disposed on the organic light emitting device E to convert the color of white light emitted from the organic light emitting device E. For example, the color filter 610 may include a red color filter, a green color filter, and a blue color filter. Accordingly, the red sub-pixel, the green sub-pixel, and the blue sub-pixel among the plurality of sub-pixels may include the color filter 610 , and the white sub-pixel may be implemented without the color filter.

The black matrix 630 may be disposed between the filling layer 460 and the second substrate 600 . The black matrix 630 may be disposed on both sides of the color filter 610 so as not to overlap the organic light emitting diode E, thereby preventing light from leaking into the non-display area and improving light leakage and reduced visibility.

3 is a cross-sectional view illustrating a display device according to an example of the present application.

Referring to FIG. 3 , the display device may further include a protective film 700 attached to the lower surface of the first substrate 110 after the carrier glass substrate 10 is removed. Specifically, in order to manufacture the display device 100 according to the present application, the carrier glass substrate 10 and the sacrificial layer 20 stacked on top of the carrier glass substrate 10 may be provided. In addition, the first substrate 110 , the buffer layer 120 , the thin film transistor array layer, and the protective layer 300 may be sequentially stacked on the carrier glass substrate 10 . Accordingly, the carrier glass substrate 10 includes the first substrate 110 , the buffer layer 120 , and the thin film transistor array while the first substrate 110 , the buffer layer 120 , the thin film transistor array layer, and the protective layer 300 are stacked. The layer and the protective layer 300 may be supported. Accordingly, the carrier glass substrate 10 can temporarily serve as a support substrate. In addition, the carrier glass substrate 10 is a sacrificial layer 20 by a laser release process when the first substrate 110 , the buffer layer 120 , the thin film transistor array layer, and the protective layer 300 are stacked and the CPS process is completed. may be separated from the first substrate 110 by the release of . When the carrier glass substrate 10 is separated from the first substrate 110 , the protective film 700 may be attached to the lower surface of the first substrate 110 .

The protective film 700 may be implemented with a material having excellent gas and moisture blocking effect and excellent light transmittance. For example, the protective film 700 may be formed of an inorganic material such as a silicon oxide layer (SiOx), aluminum oxide (AlxOy), tantalum oxide (TaxOy), or titanium oxide (TiOx). Accordingly, the protective film 700 may prevent moisture or foreign substances from being introduced into the display device, thereby improving durability of the display device.

4A to 4F are process cross-sectional views schematically illustrating a method of manufacturing a display device according to an example of the present application, which is a process cross-sectional view taken along line A of FIG. 2 .

Referring to FIG. 4A , in order to manufacture the display device 100 according to the present application, a carrier glass substrate 10 and a sacrificial layer 20 stacked on top of the carrier glass substrate 10 may be provided. In addition, the first substrate 110 , the buffer layer 120 , the thin film transistor array layer, and the protective layer 300 may be sequentially stacked on the carrier glass substrate 10 . Accordingly, the carrier glass substrate 10 includes the first substrate 110 , the buffer layer 120 , and the thin film transistor array while the first substrate 110 , the buffer layer 120 , the thin film transistor array layer, and the protective layer 300 are stacked. The layer and the protective layer 300 may be supported. Accordingly, the carrier glass substrate 10 can temporarily serve as a support substrate.

Referring to FIG. 4B , a portion of the buffer layer 120 and the thin film transistor array layer may be patterned to form a CPS line on the carrier glass substrate 10 . Specifically, the first and second buffer layers 121 and 123 and the interlayer insulating layer 240 may be patterned along the CPS line. Accordingly, the first and second buffer layers 121 and 123 and the interlayer insulating layer 240 positioned on the CPS line may be removed through a patterning process, and a partial region of the first substrate 110 positioned on the CPS line is temporarily exposed. can be

Referring to FIG. 4C , the protective layer 300 may be disposed on the thin film transistor array layer and surround the buffer layer 120 and side surfaces of the thin film transistor array layer. Specifically, the side surface 300b of the passivation layer 300 may be in contact with the side surfaces of the first and second buffer layers 121 and 123 and the interlayer insulating layer 240 , and the end portion 300c of the passivation layer 300 . may be in contact with the upper surface of the outermost portion 110a of the first substrate 110 . Accordingly, the protective layer 300 covers the upper and side surfaces of the thin film transistor array layer, the side surface of the buffer layer 120 , and the upper surface of the outermost portion 110a of the first substrate 110 , thereby protecting the thin film transistor T. can be protected, and by preventing surface exposure of the first substrate 110 , a film lifting phenomenon occurring at the interface between the first substrate 110 and the buffer layer 120 can be prevented.

According to an example, the end portion 300c of the protective layer 300 may be depressed along the CPS line. Specifically, the protective layer 300 covers the upper surfaces of the interlayer insulating layer 240 , the source electrode 250 , and the drain electrode 260 , and the end portion 300c of the protective layer 300 is patterned along the CPS line. may be engulfed in the area. As a result, the side surface 300b of the passivation layer 300 covers the side surfaces of the first and second buffer layers 121 and 123 and the interlayer insulating layer 240 , and the end portion 300c of the passivation layer 300 has the first By covering the upper surface of the outermost portion 110a of the substrate 110 , the surface of the first substrate 110 may be prevented from being exposed, and thus the interface between the first substrate 110 and the buffer layer 120 may be entirely surrounded. That is, the protective layer 300 may prevent a film lifting phenomenon occurring at the interface between the first substrate 110 and the buffer layer 120 .

And, since the protective layer 300 is formed after the first and second buffer layers 121 and 123 and the interlayer insulating layer 240 positioned on the CPS line are removed through the patterning process, the protective layer 300 positioned on the CPS line. ) of the end portion 300c is not removed through the patterning process. Accordingly, the outermost portion 110a of the first substrate 110 may not be exposed through the end portion 300c of the passivation layer 300 , and the end portion 300c of the passivation layer 300 may be disposed on the first substrate. It is possible to continue to protect the outermost portion (110a) of (110). Accordingly, the protective layer 300 may prevent a film lifting phenomenon that may occur at the interface between the first substrate 110 and the buffer layer 120 .

Referring to FIG. 4D , the metal layer 500 may surround the upper edge 300a , the side surface 300b , and the end portion 300c of the protective layer 300 . Specifically, the metal layer 500 is formed on the carrier glass substrate 10 when the first substrate 110 , the buffer layer 120 , the thin film transistor array layer, the protective layer 300 , and the planarization layer 410 are stacked. 1 It may be provided at the edge of the substrate 110 . Here, since the metal layer 500 is disposed on top of the protective layer 300 recessed along the CPS line, it may be formed along the recessed shape of the protective layer 300 . Accordingly, the metal layer 500 may be recessed along the CPS line, similarly to the end portion 300c of the protective layer 300 recessed along the CPS line. For example, the metal layer 500 may be bent twice to cover the top edge 300a , the side surface 300b , and the end portion 300c of the protective layer 300 . Accordingly, the metal layer 500 may prevent side permeation of the display apparatus 100 .

The metal layer 500 may double seal the side surfaces of the buffer layer 120 and the thin film transistor array layer and the upper surface of the outermost portion 110a of the first substrate 110 together with the protective layer 300 . Specifically, the protective layer 300 covers the upper surface of the thin film transistor array layer and covers the side surface of the interlayer insulating film 240 , the side surfaces of the first and second buffer layers 121 and 123 , and the outermost portion of the first substrate 110 . The upper surface of the portion 110a may be covered, and the metal layer 500 may cover the upper surface edge 300a, the side surface 300b, and the end portion 300c of the protective layer 300 . Accordingly, the metal layer 500 and the protective layer 300 are formed on the side surface of the interlayer insulating film 240 , the side surfaces of the first and second buffer layers 121 and 123 , and the outermost portion 110a of the first substrate 110 . By double sealing the upper surface of the , it is possible to prevent lateral moisture permeation through the buffer layer 120 and the interlayer insulating film 240 . Therefore, the display device prevents lateral permeation through the buffer layer 120 and the interlayer insulating film 240 through the metal layer 500 and the protective layer 300, thereby preventing the occurrence of dark spots in the outer portion of the display panel, It is possible to improve the reliability of the display panel.

Referring to FIG. 4E , the carrier glass substrate 10 may include a plurality of panel regions. Here, each of the plurality of panel areas corresponds to an area for manufacturing one display apparatus 100 . Accordingly, each of the plurality of display apparatuses 100 may be provided in each of the plurality of panel areas provided on the carrier glass substrate 10 . Specifically, each of the plurality of display apparatuses 100 may be separated through a CPS (Cutting with Penetrable Scriber) process after a plurality of layers are deposited through the same process on the carrier glass substrate 10 . Accordingly, the carrier glass substrate 10 , the sacrificial layer 20 , and the first substrate 110 may be cut through a CPS process.

Referring to FIG. 4F , the carrier glass substrate 10 may be removed through a laser release process. Specifically, the sacrificial layer 20 and the first substrate 110 may be sequentially stacked on the carrier glass substrate 10 , and when an ultraviolet laser is irradiated toward the sacrificial layer 20 , the sacrificial layer 20 and the first substrate 110 . The interface of the first substrate 110 may be separated so that the carrier glass substrate 10 may be removed from the first substrate 110 . Accordingly, the carrier glass substrate 10 may be removed for the attaching process of the protective film 700 after the CPS process is completed.

The protective film 700 may be attached to the lower surface of the first substrate 110 . According to an example, the protective film 700 may be implemented with a material having excellent gas and moisture blocking effect and excellent light transmittance. For example, the protective film 700 may be formed of an inorganic material such as a silicon oxide layer (SiOx), aluminum oxide (AlxOy), tantalum oxide (TaxOy), or titanium oxide (TiOx). Accordingly, the protective film 700 may prevent moisture or foreign substances from being introduced into the display device, thereby improving durability of the display device.

Accordingly, in the display device according to the present application, in the process of performing the CPS process, the protective layer 300 remains to cover the surface of the first substrate 110 , thereby providing a gap between the first substrate 110 and the buffer layer 120 . Film lifting that may occur at the interface can be prevented. In addition, the display device covers the side surface 300b of the protective layer 300 through the metal layer 500 to prevent moisture permeation that may occur on the side surface of the buffer layer 120 and the interlayer insulating film 240 to form the outer edge of the display panel. It is possible to prevent the occurrence of dark spots in the department. As a result, the display device double-seals the surface of the first substrate 110 and the side of the buffer layer 120 and the thin film transistor array layer through the protective layer 300 and the metal layer 500, thereby causing film lifting and side vapor permeation. to improve the reliability of the display panel.

The present application described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this application pertains that various substitutions, modifications, and changes are possible without departing from the technical matters of the present application. It will be clear to those who have the knowledge of Therefore, the scope of the present application is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present application.

100: display device
110: first substrate 120: buffer layer
130: light blocking layer 140: pad portion
T: thin film transistor 300: protective layer
410: planarization layer 420: bank
E: organic light emitting device 460: filling layer
470: dam 500: metal layer
600: second substrate 610: color filter
630: black matrix 700: protective film

Claims (12)

a buffer layer provided on the substrate;
a thin film transistor array layer including at least one thin film transistor arranged on the buffer layer; and
and a protective layer in contact with a side surface of each of the buffer layer and the thin film transistor array layer while being in contact with the upper surface of the thin film transistor array layer,
The end portion of the protective layer is in contact with the upper surface of the outermost portion of the substrate. The method of claim 1,
The display device further comprising a metal layer surrounding the top edge, side and end of the protective layer. 3. The method of claim 2,
The metal layer is
an upper end disposed on an upper edge of the protective layer;
a side portion surrounding the side surface of the protective layer; and
and an end portion disposed on the end portion of the protective layer. 4. The method of claim 3,
An end of the metal layer is disposed lower than the thin film transistor array layer. 3. The method of claim 2,
The metal layer overlaps the edge of the substrate and surrounds the protective layer. 3. The method of claim 2,
a planarization layer provided on the passivation layer so as to overlap the at least one thin film transistor to planarize an upper end of the passivation layer; and
and a first electrode disposed on the planarization layer and electrically connected to a source electrode of the thin film transistor. 7. The method of claim 6,
The display device in which the first electrode and the metal layer are formed of the same material in the same patterning process. 3. The method of claim 2,
The buffer layer is
a first buffer layer provided on the substrate; and
and a second buffer layer covering the first buffer layer and a light blocking layer overlapping the at least one thin film transistor on the first buffer layer. 9. The method of claim 8,
The protective layer covers the side surfaces of the first and second buffer layers and the upper surface of the outermost portion of the substrate, and the metal layer double seals the side surfaces of the first and second buffer layers and the upper surface of the outermost portion of the substrate. display device. 3. The method of claim 2,
The at least one thin film transistor comprises:
a semiconductor layer provided on the buffer layer;
a gate insulating layer overlapping a portion of the semiconductor layer;
a gate electrode provided on the gate insulating layer;
an interlayer insulating film provided on the semiconductor layer and the gate electrode; and
and a source electrode and a drain electrode spaced apart from each other on the interlayer insulating layer. 11. The method of claim 10,
The protective layer covers upper surfaces of the interlayer insulating layer, the source electrode, and the drain electrode, and is in contact with a side surface of the interlayer insulating layer. 12. The method of claim 11,
The metal layer wraps the top edge, side, and end of the protective layer, thereby double sealing the top edge and side of the interlayer insulating layer.

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