KR102441670B1 - Intelligent beam intensity calculation system, and calculation method thereof - Google Patents

Abstract

An intelligent beam intensity calculation system is provided. The intelligent beam intensity calculation system comprises: a test board having a test surface with a plurality of semiconductor devices under test mounted thereon, and with beams emitted thereto; a defect rate storage module for checking and storing defect rates of the plurality of semiconductor devices under test mounted on the test surface of the test board; and a calculation module for calculating the intensity of the beam emitted to the test surface of the test board using the defect rate stored in the defect rate storage module. The intensity of the beam emitted to the test surface can be calculated and estimated using the defect rate of the plurality of semiconductor devices under test, such that when the defect rate of the semiconductor device under test is inspected, costs can be reduced and reliability can be improved.

Description

Intelligent beam intensity calculation system, and calculation method thereof

The present application relates to an intelligent beam intensity calculation method, and more particularly, to an intelligent beam intensity calculation system for calculating the beam intensity for each region using a defect rate of a semiconductor device under test and a calculation method thereof.

Semiconductors are widely used not only in computers, mobile phones, and TVs, but also in home electronic products, and are now permeating every corner of our lives. TVs and mobile phones are capable of video and audio communication through semiconductors, and semiconductors in home appliances such as rice cookers, microwave ovens, air conditioners, refrigerators and washing machines are controlled so that they can operate optimally with simple operation.

These semiconductors are also used in automobiles by as little as several hundred to as many as thousands. In particular, in the fields of autonomous vehicles and unmanned aerial vehicles, the reliability of operation is directly related to life and safety, so the reliability evaluation of semiconductors is very important. recognized as one of the processes.

The reliability evaluation of semiconductors is performed to predict errors and reliability of semiconductors exposed to specific environments by conducting tests on whether they operate well without errors in the worst environmental conditions such as high pressure, high temperature, and high humidity, and how long the lifespan is due to environmental changes. is to quantify Conventional semiconductors have only evaluated reliability according to environments in which temperature, humidity, pressure, etc. change, but in recent years, as semiconductor defects due to atmospheric radiation are caused, reliability problems are being raised accordingly.

Accordingly, devices for evaluating the reliability of semiconductors in a radiation environment are being developed, and in Japanese Patent Application Laid-Open No. 2021-063836 as an embodiment of the prior art, a DC power supply for applying a DC voltage to at least one semiconductor element under test; In a test circuit including the at least one semiconductor element under test, a current detector for detecting a leakage current due to radiation incident, a measuring instrument for recording a pulse-type temporal change of a leakage current due to the radiation incident, and the recorded pulse time Disclosed is an apparatus for evaluating reliability of a semiconductor device including an analyzer that analyzes a failure probability of the at least one test target semiconductor device included in the test circuit based on a response waveform.

However, it is difficult to calculate the radiation intensity incident on the semiconductor device and predict the defect rate of the semiconductor device, so there is a problem in that it is difficult to evaluate the reliability of the semiconductor device according to the distance from the radiation source and the radiation intensity.

One technical problem to be solved by the present application is to provide a highly reliable beam intensity calculation system and a beam intensity calculation method.

Another technical problem to be solved by the present application is to provide an intelligent beam intensity calculation system and a beam intensity calculation method capable of calculating and estimating the intensity of each region of a beam.

Another technical problem to be solved by the present application is to provide an intelligent beam intensity calculation system and a beam intensity calculation method capable of calculating and estimating the intensity of each region of a beam by using a defect rate of a semiconductor device under test.

Another technical problem to be solved by the present application is to calculate an estimated defect rate of an unmounted area in which a semiconductor device under test is not disposed, and use it to calculate and estimate the intensity of a beam area corresponding to the unmounted area. An object of the present invention is to provide a beam intensity calculation system and a beam intensity calculation method.

The technical problem to be solved by the present application is not limited to the above.

In order to solve the above technical problem, the present application provides a beam intensity calculation system, and a beam intensity calculation method.

According to an exemplary embodiment, the beam intensity calculation system includes a test board having a test surface on which a plurality of semiconductor devices under test are mounted and irradiated with beams, and a plurality of semiconductors under test mounted on the test surface of the test board. A defective rate storage module for checking and storing the defective rate of the device, and a calculation module for calculating the intensity of the beam irradiated to the test surface of the test board by using the defective rate stored in the defective rate storing module, in the calculation module, The intensity of the beam irradiated to the test surface may include calculating a defect rate of the plurality of semiconductor devices under test.

According to an embodiment, the test surface of the test board includes an unassembled region in which the plurality of semiconductor devices under test are not mounted, and a mounting region in which the plurality of semiconductor devices under test are mounted. The intensity of the irradiated beam may include calculating an estimated defective rate by interpolating the defective rate of the semiconductor device under test in the mounting region adjacent to the unmounted region, and calculating the estimated defective rate using the estimated defective rate.

According to an embodiment, the unmounted area may include a plurality of pixels formed by being divided into a virtual grid.

According to an embodiment, the beam intensity calculation system includes a first test board on which a plurality of first semiconductor devices under test are mounted and having a first test surface to which a beam is irradiated, and the first test board interposed therebetween. A second test board spaced apart from a beam emitting source, a plurality of second semiconductor devices under test mounted thereon, the second test board having a second test surface to which the beam is irradiated, the first test surface, and the second test surface A defect rate storage module for checking and storing defective rates of the mounted first and second semiconductor devices under test, and a virtual defined between the first test board and the second test board using the defective rate stored in the defective rate storage module It may include a calculation module for calculating the intensity of the beam irradiated to the (virtual) intermediate plane (intermediate plane).

According to an embodiment, in the calculation module, the intensity of the beam irradiated to the first test surface and the second test surface is, respectively, a defect rate of the first semiconductor element under test and the second semiconductor element under test. It may include calculating using

According to an embodiment, the intensity of the beam irradiated to the intermediate plane may include a defect rate of the first semiconductor element under test, a distance between the first test board and the intermediate plane, and a defect rate of the second semiconductor element under test. , and calculating an estimated defective rate using a distance between the second test board and the intermediate plane, and calculating using the estimated defective rate.

In order to solve the above technical problem, the present application provides a beam intensity calculation method.

According to an embodiment, the method for calculating the beam intensity includes mounting a plurality of semiconductor devices under test on a test surface of a test board, irradiating beams to the test surface, and mounting on the test surface of the test board. The method may include checking and storing the defective rates of the plurality of semiconductor devices under test, and calculating the intensity of the beam irradiated to the test surface of the test board by using the defective rates of the semiconductor devices under test.

According to an embodiment, the method for calculating the beam intensity includes mounting a plurality of first semiconductor devices under test on a first test surface of a first test board, and emitting the beam with the first test board interposed therebetween. Mounting a plurality of second semiconductor devices under test on a second test surface of a second test board spaced apart from a radiation source, irradiating beams to the first test surface and the second test surface, the first checking and storing defective rates of the first semiconductor device under test and the second semiconductor device under test mounted on the test surface and the second test surface, and the first test board and the first test board using the stored defective rate The method may include calculating the intensity of the beam irradiated to a virtual intermediate plane defined between the second test boards.

According to an embodiment of the present application, the intelligent beam intensity calculation system includes a test board on which a plurality of semiconductor devices under test are mounted, a test board having a test surface to which a beam is irradiated, and a plurality of the test boards mounted on the test surface of the test board. A defective rate storage module for checking and storing the defective rate of the semiconductor device may be included.

The intelligent beam intensity calculation system may include a calculation module for calculating the intensity of the beam irradiated to the test surface of the test board by using the defective rate of the semiconductor device under test stored in the defective rate storage module.

In this case, the test surface of the test board includes an unassembled region in which the plurality of semiconductor devices under test are not mounted, and a mounting region in which the plurality of semiconductor devices under test are mounted, wherein the irradiated regions are irradiated to the unassembled region. The intensity of the beam may be calculated by interpolating the defective rate of the semiconductor device under test in the mounting area adjacent to the unmounted area to calculate the estimated defective rate.

Accordingly, the intensity of each region of the beam may be calculated and estimated using the defective rate of the semiconductor device under test mounted in the mounting region, and the estimated defect rate of the unassembled region in which the semiconductor device under test is not mounted is determined by the unmounted region. It can be calculated using the defective rate of the semiconductor device under test adjacent to . From this, it is possible to calculate and estimate the intensity of the beam region corresponding to the mounting region, so that the number of the semiconductor device under test used for measuring the beam intensity is reduced, thereby reducing the cost of measuring the intensity of the beam, Reliability of the calculated beam intensity value may be improved.

In addition, according to another embodiment of the present application, the intelligent beam intensity calculation system includes a first test board having a first test surface on which a plurality of first semiconductor devices under test are mounted, a first test surface to which a beam is irradiated, and the first test board. a second test board spaced apart from the source for emitting the beam and having a second test surface on which a plurality of second semiconductor devices under test are mounted, the second test surface having a second test surface to which the beam is irradiated, and the first test surface and the first test surface and a defective rate storage module for checking and storing defective rates of the first and second semiconductor devices under test mounted on the second test surface.

The intelligent beam intensity calculation system uses a virtual (virtual) defined between the first test board and the second test board by using the defective rates of the first semiconductor under test and the second under test stored in the defective rate storage module. ) may include a calculation module for calculating the intensity of the beam irradiated to the intermediate plane (intermediate plane).

In this case, the intensity of the beam irradiated to the intermediate plane may include a defect rate of the first semiconductor element under test, a distance between the first test board and the intermediate plane, a defect rate of the second semiconductor element under test, and the An estimated defective rate may be calculated using a distance between the second test board and the intermediate plane, and the estimated defective rate may be used to calculate the estimated defective rate.

Accordingly, it is possible to estimate and calculate the intensity of each area of the beam according to the distance from the source to which the beam is irradiated, and the intensity of each area of the beam in an imaginary intermediate plane located between the first test board and the second test board. An estimated defect rate is calculated using the defect rates of the first semiconductor element under test mounted on the first test board and the second semiconductor element under test mounted on the second test board, and from this, the area of the beam in the imaginary intermediate plane Calculate and estimate star strength. That is, since the number of test boards and semiconductor devices under test used for measuring the beam intensity is reduced, the cost of measuring the intensity of the beam may be reduced, and reliability of the calculated intensity value of the beam may be improved.

1 is a flowchart illustrating an intelligent beam intensity calculation method according to a first embodiment of the present application.
2 is a block diagram illustrating an intelligent beam intensity calculation system according to a first embodiment of the present application.
3 is a perspective view illustrating an intelligent beam intensity calculation system according to a first embodiment of the present application.
4 is a diagram for explaining that the calculation module of the intelligent beam intensity calculation system according to the first embodiment predicts a defective rate that may occur when a semiconductor device under test is disposed in a virtual pixel.
5 is a diagram for explaining calculation of a weight for an area when a calculation module of an intelligent beam intensity calculation system according to a first modified example of the first embodiment of the present application calculates an estimated defective rate of an overlapping area.
6 and 7 are perspective views for explaining a process of moving the test board by further including a movement control module in the beam intensity calculation system according to the second modified example of the first embodiment of the present application.
8 is a flowchart illustrating an intelligent beam intensity calculation method according to a second embodiment of the present application.
9 is a block diagram illustrating an intelligent beam intensity calculation system according to a second embodiment of the present application.
10 is a perspective view illustrating an intelligent beam intensity calculation system according to a second embodiment of the present application.
11 is a view for explaining a process in which the calculation module of the intelligent beam intensity calculation system according to the second embodiment of the present application calculates the intensity of a beam irradiated to a virtual intermediate plane.
12A is a view showing the defective rate of the first semiconductor device under test measured by the defective rate storage module of the intelligent beam intensity calculation system according to the first modified example of the second embodiment of the present application by arranging the first test board alone. It is a diagram for explaining storage.
12 (b) shows the defective rate of the second semiconductor device under test measured by the defective rate storage module of the intelligent beam intensity calculation system according to the first modified example of the second embodiment of the present application by arranging the second test board alone. It is a diagram for explaining storage.
12( c ) shows a first semiconductor device under test measured by an intelligent beam intensity calculation system calculation module according to a first modified example of the second embodiment of the present application by arranging a first test board and a second test board at the same time; A diagram for explaining a process of calculating the corrected defect rate by using the defect rate of the second semiconductor device under test.
13 is a view for explaining a process in which the calculation module of the intelligent beam intensity calculation system according to a second modification of the second embodiment of the present application calculates the intensity of a beam irradiated to an unmounted area and a mounted area on a virtual intermediate plane to be.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

Also, in various embodiments of the present specification, terms such as first, second, third, etc. are used to describe various components, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Accordingly, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes a complementary embodiment thereof. In addition, in this specification, 'and/or' is used in the sense of including at least one of the elements listed before and after.

In the specification, the singular expression includes the plural expression unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to designate that a feature, number, step, element, or a combination thereof described in the specification exists, and one or more other features, numbers, steps, or configurations It should not be construed as excluding the possibility of the presence or addition of elements or combinations thereof. In addition, in the following description of the present invention, if it is determined that a detailed description of a related well-known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

In the present application, "beam" includes radiation and radiation particles, and may be interpreted as including radiation particles such as alpha particles, neutrons, protons, heavy ions, alpha particles, gamma rays, and X-rays, and in the present application Errors occurring in the semiconductor device under test can be interpreted as a general meaning including soft errors such as single bit upset (SBU), multi bit upset (MBU), and multi cell upset (MCU) among single event upset (SEU). have.

In addition, the semiconductor device under test described in the specification of the present application includes SRAM, flash memory, DRAM, cache memory, logic IC, image sensor device, display device, power IC, RF IC, SSD, RRAM, PRAM, MRAM, etc. It is obvious that various analog and/or digital semiconductor devices not specified may be included.

A general semiconductor device inspection apparatus is for inspecting various defects occurring in a production process. On the other hand, according to an embodiment of the present application, an apparatus for inspecting a defect caused by radiation in a semiconductor device that passes through all evaluation processes after being manufactured and operates normally is provided.

1 is a flowchart for explaining an intelligent beam intensity calculation method according to a first embodiment of the present application, FIG. 2 is a block diagram for explaining an intelligent beam intensity calculation system according to a first embodiment of the present application, FIG. 3 is a perspective view for explaining an intelligent beam intensity calculation system according to a first embodiment of the present application, and FIG. 4 is a calculation module of the intelligent beam intensity calculation system according to the first embodiment of the semiconductor device under test in a virtual pixel It is a diagram for explaining the prediction of the defective rate that may occur in the case of arrangement.

1 to 4 , an intelligent beam intensity calculation system and an intelligent beam intensity calculation method according to the first embodiment of the present application including a test board 110 , a defective rate storage module 120 , and a calculation module 130 . This is explained.

A plurality of semiconductor devices under test 100 are mounted on the test surface 111 of the test board 110 (S110).

The semiconductor device under test 100 may be a semiconductor device to be subjected to a defect rate test through an irradiation test of the beam 51 irradiated from the source 50 . In addition, the beam 51 may be directly or indirectly irradiated to the semiconductor device under test 100 .

The test board 110 may include the test surface 111 . The test surface 111 may be defined as one surface of the test board 110 on which the semiconductor device under test 100 is disposed. According to an embodiment, the semiconductor device under test 100 may be mounted on the test surface 111 of the test board 110 through a socket (not shown).

According to an embodiment, the test surface 111 may include a mounting area 112 and a non-mounting area 114 .

The unmounted region 114 may be defined as a region in which the plurality of semiconductor devices under test 100 are not mounted. The mounting region 112 may be defined as a region in which the plurality of semiconductor devices under test 100 are mounted. In other words, the test surface 111 includes a region (the mounting region 112 ) of the test surface 111 on which the plurality of semiconductor devices under test 100 are mounted, and the semiconductor device under test 100 . may be divided into a region (the non-mounted region 114 ) of the test surface 111 on which is not mounted.

As will be described later, the intensity of the beam 51 region corresponding to the mounting region 112 may be calculated and estimated based on the defect rate of the semiconductor device under test 100 mounted in the mounting region 112 . In addition, the intensity of the region of the beam 51 corresponding to the unassembled region 114 is determined by interpolating defect rates of the plurality of semiconductor devices under test 100 mounted in the plurality of adjacent mounting regions 112 to determine the unmounted region. The estimated defective rate of the virtual semiconductor device under test mounted in the region 114 may be calculated and calculated and estimated using the estimated defective rate.

The semiconductor device under test 100 may be mounted on the test surface 111 to be spaced apart from each other. Accordingly, the non-mounting region 114 may be defined between the mounting regions 112 .

For example, as shown in FIG. 4 , the first to fourth mounting regions 112a to 112d in which the first to fourth semiconductor devices under test, which are spaced apart from each other, are mounted on the test surface 111 are spaced apart from each other. to be provided in the test surface 111 , and the unmounted region 114 may be provided between the first to fourth mounting regions 112a to 112d.

In this case, according to an embodiment, the unmounted area 114 may be divided into a plurality of pixels in a grid shape. In other words, the unmounted region 114 may include a plurality of the pixels formed by being divided into a virtual grid. More specifically, as shown in FIG. 4 , the unmounted region 114 includes a first pixel 114a between the first mounting region 112a and the second mounting region 112b, and a first mounting region 112a. ) and a second pixel 114b between the third mounting region 112c, a third pixel 114c between the third mounting region 112c and the fourth mounting region 112d, a second mounting region 112b, and It may include a fourth pixel 114d between the fourth mounting regions 112d and a fifth pixel 114e between the first to fourth mounting regions 112a to 112d.

The beam 51 is irradiated to the test surface 111 (S120).

The source 50 may irradiate the beam 51 to the test board 110 . Specifically, the source 50 may irradiate the beam 51 to the semiconductor device under test 100 disposed on the test surface 111 of the test board 110 .

The beam 51 is emitted from the source 50 and may be irradiated to the test board 110 , the test surface 111 , and the semiconductor device under test 100 . In addition, the beam 51 may include radiation and radiation particles such as alpha particles, neutrons, protons, heavy ions, alpha particles, gamma rays, and X-rays, but is not limited thereto.

Defect rates of the plurality of semiconductor devices under test 100 mounted on the test surface 111 of the test board 110 are checked and stored ( S130 ).

Defect rate data of the plurality of semiconductor devices under test 100 may be checked and stored through the defect rate storage module 120 illustrated in FIG. 2 . Specifically, the beam 51 may be irradiated from the source 50 to the plurality of semiconductor devices under test 100 , and errors occur in the plurality of semiconductor devices under test 100 by the beam 51 . may occur. Errors occurring in the plurality of semiconductor devices under test 100 , that is, defective rates may be checked and stored in the defective rate storage module 120 .

The defective rate storage module 120 may transmit data on the defective rates of the plurality of semiconductor devices under test 100 mounted on the test surface 111 of the test board 110 to the calculation module 130 . have.

The intensity of the beam 51 irradiated to the test surface 111 of the test board 110 is calculated using the defect rate of the semiconductor device under test 100 ( S140 ).

The intensity of the beam 51 irradiated to the plurality of semiconductor devices under test 100 may be calculated through the calculation module 130 illustrated in FIG. 2 . Specifically, by using the defective rate of the semiconductor device under test 100 stored in the defective rate storage module 120 , the intensity of the beam 51 irradiated to the plurality of semiconductor devices under test 100 is calculated and estimated can do. For example, when the defect rate of the semiconductor device under test 100 disposed on the first region of the test surface 111 is relatively high, the calculation module 130 may generate the beam irradiated to the first region. (51) can be calculated and estimated to be relatively strong. That is, the region corresponding to the first region in the beam 51 may be calculated and estimated to have a relatively strong intensity. On the other hand, when the defective rate of the semiconductor device under test 100 disposed on the first region of the test surface 111 is relatively low, the calculation module 130 generates the beam ( 51) can be calculated and estimated to be relatively weak. That is, the area corresponding to the first area in the beam 51 may be calculated and estimated as having a relatively weak intensity.

According to an embodiment, the calculation module 130 may calculate the intensity of the beam 51 irradiated to the unmounted area 114 . 4 , the unmounted region 114 may include a plurality of the pixels 114a to 114e. The intensity of the beam 51 irradiated to the unmounted region 114 is determined using the estimated defect rate, which is a value obtained by estimating the defect rate that occurs when the semiconductor device under test 100 is mounted on the pixels 114a to 114e. can be calculated

For example, the estimated defective rate of the first pixel 114a is the number of semiconductor devices under test mounted in the first mounting region 112a and the second mounting region 112b adjacent to the first pixel 114a. It can be calculated by interpolating the defective rate.

Specifically, for example, the estimated defective rate of the first pixel 114a is the semiconductor under test mounted in the first mounting region 112a and the second mounting region 112b adjacent to the first pixel 114a. It can be defined and calculated as an average value of the defective rates of the devices. The intensity of the beam 51 irradiated to the first pixel 114a is obtained as an average value of defective rates of the semiconductor devices under test mounted in the first mounting region 112a and the second mounting region 112b. It can be calculated using the estimated defective rate of the first pixel 114a.

Similarly, the estimated defective rate of the second pixel 114b is an average value of the defective rates of the semiconductor devices under test mounted in the first mounting region 112a and the third mounting region 112c adjacent to the second pixel 114b. can be defined and calculated as The estimated defective rate of the third pixel 114c is defined as an average value of the defective rates of the semiconductor devices under test mounted in the third mounting region 112c and the fourth mounting region 112d adjacent to the third pixel 114c. and can be calculated. The estimated defective rate of the fourth pixel 114d is defined as an average value of the defective rates of the semiconductor devices under test mounted in the second mounting region 112b and the fourth mounting region 112d adjacent to the fourth pixel 114d. and can be calculated. The estimated defective rate of the fifth pixel 114e is defined and calculated as an average value of the defective rates of the semiconductor devices under test mounted in the first to fourth mounting regions 112a to 112d adjacent to the fifth pixel 114e. can

As a result, the estimated defect rate of the unmounted region 114 may be defined and calculated as an average value of the defect rates of the semiconductor device under test 100 mounted in the adjacent mounting region 112 .

The intensity of the beam 51 irradiated to the unmounted area 114 may also be calculated through the above-described calculation module 130 . Specifically, the unmounted area 114 is irradiated using the estimated defective rate of the unmounted area 114 calculated using the defective rates of the semiconductor devices under test 100 mounted in the adjacent mounting area 112 . The intensity of the beam 51 that is to be can be calculated. For example, when the estimated defective rate of the non-mounted area 114 is relatively high, the calculation module 130 may calculate that the intensity of the beam 51 irradiated to the non-mounted area 114 is relatively high. .

The estimated defect rate of the non-mounted area 114 calculated by the calculation module 130 and/or the intensity of the beam 51 irradiated to the non-mounted area 114 may be transmitted to a display device (not shown) or the like.

The display device (not shown) visually shows the estimated defect rate of the non-mounted area 114 calculated by the calculation module 130 and/or the intensity of the beam 51 irradiated to the non-mounted area 114 . can For example, the display device (not shown) may be a monitor, but is not limited thereto.

Unlike the beam intensity calculation system according to the first embodiment described above, according to the beam intensity calculation system according to the first modified example of the first embodiment, the unmounted region 114 may be divided into a plurality of fine pixels, and the An estimated defective rate of the fine pixel may be calculated and estimated. Hereinafter, a beam intensity calculation system according to a first modified example of the first embodiment will be described with reference to FIG. 5 .

5 is a diagram for explaining calculation of a weight for an area when a calculation module of an intelligent beam intensity calculation system according to a first modified example of the first embodiment of the present application calculates an estimated defective rate of an overlapping area.

Referring to FIG. 5 , the first to fourth pixels 114a - e of the unmounted area 114 may be divided into a plurality of fine pixels, respectively. For example, the fourth pixel 114d includes a 4-1 th fine pixel 114d1 , a 4-2 th fine pixel 114d2 , a 4-3 th fine pixel 114d3 , and a 4-4th fine pixel 114d4 . ) can be divided into Similarly, the first pixel 114a, the second pixel 114b, the third pixel 114c, and the fifth pixel 114e may be divided into fine pixels (not shown).

The calculation module 130 may calculate the intensity of the beam 51 irradiated to the plurality of fine pixels. Specifically, the intensity of the beam 51 irradiated to the plurality of micro-pixels is an estimate of the defect rate generated in the semiconductor device under test 100 when the semiconductor device under test 100 is mounted on the plurality of micro-pixels. It can be calculated and estimated using the estimated defective rate, which is a value. For example, when the estimated defective rate of the fine pixel is relatively high, the calculation module 130 may calculate and estimate that the intensity of the beam 51 irradiated to the fine pixel is relatively strong. That is, the region corresponding to the minute pixel in the beam 51 may be calculated and estimated to have a relatively strong intensity. On the other hand, when the estimated defective rate of the fine pixel is relatively low, the calculation module 130 may calculate and estimate that the intensity of the beam 51 irradiated to the fine pixel is relatively weak. That is, the region corresponding to the minute pixel in the beam 51 may be calculated and estimated as having a relatively weak intensity.

According to an embodiment, the calculation module 130 may calculate the estimated defective rate of the fine pixel. The estimated defective rate of the fine pixel is higher than the defective rate of the semiconductor device under test 100 mounted in the adjacent mounting region 112 , the estimated defective rate of the pixels 114a to 114e in the adjacent unmounted region 114 , and the fine pixel. It can be calculated and estimated using a calculation area that is large and includes the fine pixels.

Specifically, for example, the estimated defective rate of the 4-1 th fine pixel 114d1 of the fourth pixel 114d is the defective rate of the semiconductor device under test 100 mounted in the adjacent third mounting region 112c. , the estimated defective rate of the second pixel 114b in the adjacent unmounted area 114 , the estimated defective rate of the fourth pixel 114d to which the 4-1 th micropixel 114d1 belongs, and the estimated defective rate of the adjacent unmounted area 114 . The estimated defective rate of the fifth pixel 114e, the overlapping area of the calculation area 115 and the third mounting area 112c, the overlapping area of the calculation area 115 and the second pixel 114b, the It may be calculated and estimated using an overlapping area of the calculation area 115 and the fourth pixel 114d and an overlapping area of the calculation area 115 and the fifth pixel 114e.

In this case, the calculation area 115 is an arbitrary area that is larger than the 4-1 th fine pixel 114d1 and includes the 4-1 th fine pixel 114d1, and the user can set the size arbitrarily. When the estimated defective rate of the 4-1 th fine pixel 114d1 is calculated, the 4-1 th fine pixel 114d1 may be positioned at the center of the calculation area 115 .

The defective rate of the semiconductor device under test 100 mounted in the third mounting region 112c may be checked through the defective rate storage module 120 described with reference to FIGS. 1 to 4 . The estimated defective rates of the second, fourth, and fifth pixels 114b, 114d, and 114e are determined by the method described with reference to FIGS. It may be calculated and estimated using the defective rates of the plurality of semiconductor devices under test 100 .

Specifically, for example, the defective rate of the semiconductor device under test 100 mounted in the third mounting region 112c is a, the estimated defective rate of the second pixel 114b is b, and the fourth pixel ( The estimated defective rate of 114d) is c, the estimated defective rate of the fifth pixel 114e is d, the overlapping area of the calculation area 115 and the third mounting area 112c is 3s, and the calculation area ( 115) and the overlapping area of the second pixel 114b is 1s, the overlapping area of the calculation area 115 and the fourth pixel 114d is 9s, and the calculation area 115 and the fifth pixel 114d are 9s. When the overlapping area of the pixels 114e is 3s, the estimated defective rate f₁ of the 4-1 th fine pixel 114d1 may be calculated and estimated as in Equation (1).

<Equation 1>

The estimated defective rate of the 4-1 th fine pixel 114d1 is the defective rate of the third mounting region 112c and the estimated defective rate of the second, fourth, and fifth pixels 114b, 114d, and 114e in the calculation area (115) A method of multiplying the ratio of the overlapping area of each of the calculation area 115 and the third mounting area 112c and the second, fourth and fifth pixels 114b, 114d and 114e in the total area can be calculated and estimated.

In other words, the estimation rate of the 4-1 th fine pixel 114d1 is a ratio of 1 in which the calculation area 115 and the third mounting area 112c overlap the defective rate a of the third mounting area 112c. A value multiplied by /16, a value obtained by multiplying the estimated defective rate b of the second pixel 114b by a ratio 3/16 in which the calculation area 115 and the second pixel 114b overlap, the fourth pixel 114d A value obtained by multiplying the estimated defective rate c of the calculated area 115 and the fourth pixel 114d by a ratio of 9/16, and the estimated defective rate d of the fifth pixel 114e with the calculated area 115 The fifth pixel 114e may be calculated by adding a value obtained by multiplying the overlapping ratio 3/16.

Hereinafter, a beam intensity calculation system according to a second modification of the first embodiment will be described with reference to FIGS. 6 and 7 .

6 and 7 are perspective views for explaining a process of moving the test board by further including a movement control module in the beam intensity calculation system according to the second modified example of the first embodiment of the present application.

6 and 7 , the movement control module 150 of the beam intensity calculation system according to a second modification of the first embodiment controls the test board 110 on which the semiconductor device under test 100 is mounted. can be moved As the test board 110 moves, the area to which the beam 51 is irradiated may be relatively moved. That is, the test board 110 may be moved by the movement control module 150 while the area to which the beam 51 is irradiated is fixed. The movement control module 150 may include a first direction movement unit 151 and a second direction movement unit 152 .

The first direction moving part 151 is connected to the test board 110 to move the test board 110 in a first direction (±x axis) parallel to the test surface 111 of the test board 110 . direction) can be moved.

As shown in (a) of Figure 7, when the test board 110 of Figure 7 (b) moves in the -x-axis direction, the area of the beam 51 can move in the +x-axis direction. have.

7(c), when the test board 110 of FIG. 7(b) moves in the +x-axis direction, the area of the beam 51 may move in the -x-axis direction. have.

The second direction moving part 152 is connected to the test board 110 to move the test board 110 in a second direction (±y-axis direction) perpendicular to the first direction (±x-axis direction). can be moved

Although not shown, when the test board 110 moves in the +y-axis direction, the region of the beam 51 may move in the -y-axis direction, and the test board 110 moves in the -y-axis direction. In this case, the area of the beam 51 may move in the +y-axis direction.

That is, according to the movement of the test board 110 by the movement control module 150 , the beam irradiated to the semiconductor device under test 100 by relatively moving the area to which the beam 51 is irradiated. The area of (51) can be moved.

As a result, the area of the beam 51 irradiated to the semiconductor device under test 100 is automatically controlled through the movement control module 150 , and accordingly, the semiconductor device under test 100 operates under various conditions. A defect rate test may be performed in

In addition, as the test board 110 moves, the beam 51 of the same dose and intensity is irradiated to the semiconductor device under test 100 arranged in the same direction as the moving direction of the test board 110 . Accordingly, the difference in the dose of the beam 51 is minimized, and thus the reliability of the measurement of the intrinsic defect rate of the semiconductor device under test 100 may be improved. Accordingly, the intensity of the beam 51 calculated and estimated from the defective rate of the semiconductor device under test 100 may be accurately measured.

Unlike the intelligent beam intensity calculation system according to the first embodiment of the present application described above, the intelligent beam intensity calculation system according to the second embodiment of the present application includes the first test board 210 and the second test board 220 . Using the defect rates of the first semiconductor device under test 201 and the second semiconductor device under test 202 mounted thereon, a virtual space between the first test board 210 and the second test board 220 is used. It is possible to calculate the intensity of the beam 510 irradiated to the intermediate plane 205 of. Hereinafter, an intelligent beam intensity calculation system according to a second embodiment will be described with reference to FIGS. 8 to 13 .

8 is a flowchart for explaining an intelligent beam intensity calculation method according to a second embodiment of the present application, and FIG. 9 is a block diagram for explaining an intelligent beam intensity calculation system according to a second embodiment of the present application, FIG. 10 is a perspective view for explaining the intelligent beam intensity calculation system according to the second embodiment of the present application, and Figure 11 is the calculation module of the intelligent beam intensity calculation system according to the second embodiment of the present application is irradiated to a virtual intermediate plane It is a drawing for explaining the process of calculating the intensity of the beam.

8 to 11 , an intelligent according to a second embodiment of the present application including a first test board 210 , a second test board 220 , a defective rate storage module 230 and a calculation module 240 . A beam intensity calculation system and an intelligent beam intensity calculation method are described.

A plurality of first semiconductor devices under test 201 are mounted on the first test surface 211 of the first test board 210 ( S210 ).

The first semiconductor device under test 201 may be a semiconductor device to be subjected to a defect rate test through an irradiation test of the beam 51 irradiated from the source 50 . Also, the beam 51 may be directly or indirectly irradiated to the first semiconductor device under test 201 .

The first test board 210 may include the first test surface 211 . The first test surface 211 may be defined as one surface of the first test board 210 on which the first semiconductor device under test 201 is disposed. According to an embodiment, the second semiconductor device under test 201 may be mounted on the first test surface 211 of the first test board 210 through a socket (not shown).

A plurality of second objects under test are placed on the second test surface 221 of the second test board 220 spaced apart from the source 50 emitting the beam 51 with the first test board 210 interposed therebetween. The semiconductor device 202 is mounted (S220).

The second semiconductor device under test 202 may be a semiconductor device to be subjected to a defect rate test through an irradiation test of the beam 51 irradiated from the source 50 . Also, the beam 51 may be directly or indirectly irradiated to the second semiconductor device under test 202 .

In addition, the second test board 220 may include the second test surface 221 . The second test surface 221 may be defined as one surface of the second test board 220 on which the second semiconductor device under test 202 is disposed. According to an embodiment, the second semiconductor device under test 202 may be mounted on the second test surface 221 of the second test board 220 through a socket (not shown).

The beam 51 is irradiated to the first test surface 211 and the second test surface 221 ( S230 ).

The source 50 may irradiate the beam 51 to the first test board 210 and the second test board 220 . Specifically, the source 50 may irradiate the beam 51 to the first semiconductor device under test 201 disposed on the first test surface 211 of the first test board 210 . have. The beam 51 irradiated from the source 50 passes through the first test board 210 and the second blood is disposed on the second test surface 221 of the second test board 220 . It can be irradiated with the test semiconductor device 202 .

The beam 51 is emitted from the source 50, and the first test board 210, the first test surface 211, the first semiconductor device under test 201, and the second test board ( 220 ), the second test surface 221 , and the second semiconductor device under test 202 . In addition, the beam 51 may include radiation and radiation particles such as alpha particles, neutrons, protons, heavy ions, alpha particles, gamma rays, and X-rays, but is not limited thereto.

Defect rates of the first semiconductor device under test 201 and the second semiconductor device under test 202 mounted on the first test surface 211 and the second test surface 221 are checked and stored ( S240).

Defect rate data of the plurality of first semiconductor devices under test 201 and second semiconductor devices under test 202 may be checked and stored through the defective rate storage module 230 illustrated in FIG. 9 . Specifically, the beam 51 may be irradiated from the source 50 to the plurality of first semiconductor devices under test 201 and second semiconductor devices under test 202 , and by the beam 51 , An error may occur in the plurality of first semiconductor devices under test 201 and second semiconductor devices under test 202 . Errors occurring in the plurality of first semiconductor devices under test 201 and second semiconductor devices under test 202 , that is, defective rates, may be checked and stored in the defective rate storage module 230 .

The defective rate storage module 230 is configured to determine the defective rate and/or the second test of the plurality of first semiconductor devices under test 210 mounted on the first test surface 211 of the first test board 210 . Data on the defective rates of the plurality of second semiconductor devices under test 220 mounted on the second test surface 221 of the board 220 may be transmitted to the calculation module 240 .

The beam 51 irradiated to a virtual intermediate plane 205 defined between the first test board 210 and the second test board 220 using the stored defect rate. ) is calculated (S250).

The intensity of the beam 51 irradiated to the virtual intermediate plane 205 may be calculated through the calculation module 240 shown in FIG. 9 . Specifically, by using the defective rates of the first semiconductor element under test 201 and the second semiconductor element under test 202 stored in the defect rate storage module 230 , the virtual intermediate plane 205 is irradiated. The intensity of the beam 51 may be calculated. For example, as shown in FIG. 10 , the first semiconductor device under test 201 and the second test surface 221 disposed on the first region 1 of the first test surface 221 . When the defect rate of the second semiconductor device under test 202 disposed on the second region 2 at the same position as the first region 1 of It can be calculated and estimated that the intensity of the beam 51 irradiated to the region 1 and the second region 2 is relatively strong. That is, the region corresponding to the first region 1 and the second region 2 in the beam 51 may be calculated and estimated to have relatively strong intensity. On the other hand, the first semiconductor device under test 201 disposed on the first region 1 of the first test surface 221 and the first region 1 of the second test surface 221 are identical to those of the first region 1 of the first test surface 221 . When the defective rate of the second semiconductor device under test 202 disposed on the second region 2 of the location is relatively low, the calculation module 240 is configured to generate the first region 1 and the second region ( It can be calculated and estimated that the intensity of the beam 51 irradiated with 2) is relatively weak. That is, the region corresponding to the first region 1 and the second region 2 in the beam 51 may be calculated and estimated to have relatively weak intensity.

According to an embodiment, the calculation module 240 may calculate the intensity of the beam 51 irradiated to the virtual intermediate plane 205 . The intensity of the beam 51 irradiated to the virtual intermediate plane 205 is generated when the semiconductor devices under test 201 and 202 are mounted on the target region 3 of the virtual intermediate plane 205 . It can be calculated and estimated using the estimated defective rate, which is a value obtained by estimating the defective rate.

For example, the estimated defective rate of the target region 3 in the virtual intermediate plane 205 is the first semiconductor device under test mounted in the first region 1 of the first test surface 211 ( 201 ), the defect rate of the second semiconductor device under test 202 mounted in the second region 2 of the second test surface 221 , and the first test surface of the first test board 210 . It can be calculated using the distance between 211 and the virtual intermediate plane 205 and the distance between the second test surface 221 and the virtual intermediate plane 205 of the second test board 220 . have. The target area 3 may be an area at the same position as the first area 1 and the second area 2 , and may be an area through which one area of the beam 51 penetrates and overlaps therewith.

Specifically, for example, in the imaginary intermediate plane 205 positioned between the first test surface 211 and the second test surface 221 , the first test surface 211 and the virtual intermediate plane When the distance between the planes 205 is x and the distance between the second test plane 221 and the imaginary intermediate plane 205 is y, the first region 1 in the imaginary intermediate plane 205 is and the estimated defective rate f2 of the target area 3 at the same location as the second area 2 may be calculated as in Equation 2 below. In <Equation 2>, a is the defect rate of the first semiconductor device under test 201 mounted in the first region 1 located at the same position as the target region 3 , and b is the second region It is the defect rate of the second semiconductor device under test 202 located in (2). In other words, in the virtual intermediate plane 205 , the estimated defective rate of the target region 3 is the first semiconductor under test located in the first region 1 at the same position as the target region 3 . The defect rate of the device 201 , the defect rate of the second semiconductor device under test 202 located in the second region 2 , the distance between the target region 3 and the first region 1 , the target region ( It can be calculated and estimated using the distance between 3) and the second region 2 .

<Equation 2>

Similarly, as shown in FIG. 11 , the distance between the first test surface 211 and the imaginary intermediate plane 205 is d, and the second test surface 221 and the virtual intermediate plane 205 . When the distance between them is 2d, the estimated defective rate f₃ of the target area 3 at the same location as the first area 1 and the second area 2 on the virtual intermediate plane 205 is <Equation 3 > can be calculated as In <Equation 3>, a is the defect rate of the first semiconductor device under test 201 mounted in the first region 1 at the same position as the target region 3, and b is the second region ( The defect rate of the second semiconductor device under test 202 located in 2). In other words, in the virtual intermediate plane 205 , the estimated defective rate of the target region 3 is the first semiconductor under test located in the first region 1 at the same position as the target region 3 . The defect rate of the device 201 , the defect rate of the second semiconductor device under test 202 located in the second region 2 , the distance d between the target region 3 and the first region 1 , the It can be calculated and estimated using the distance 2d between the target area 3 and the second area 2 .

<Equation 3>

As a result, in the virtual intermediate plane 205 , the estimated defective rate of the target region 3 is the defective rate of the first semiconductor under test 201 , the defective rate of the second semiconductor under test 202 , and the virtual The calculation may be performed using a distance between the intermediate plane 205 and the first test board 210 and a distance between the virtual intermediate plane 205 and the second test board 220 .

The intensity of the beam 51 irradiated to the virtual intermediate plane 205 may also be calculated and estimated using the estimated defective rate of the virtual intermediate plane 205 . Specifically, the calculation is performed using the defective rate of the first semiconductor device under test 201 mounted in the first region 1 and the second semiconductor device 202 mounted in the second region 2 . The intensity of the beam 51 irradiated from the virtual intermediate plane 205 to the target area 3 may be calculated using the estimated defective rate of the virtual intermediate plane 205 . For example, when the estimated defective rate of the target area 3 in the intermediate plane 205 is relatively high, the calculation module 240 scans the virtual intermediate plane 205 into the target area 3 . It can be calculated that the intensity of the beam 51 is relatively strong.

In other words, the intensity of each region of the beam 51 may be calculated and estimated on the intermediate surface 205 between the first test board 210 and the second test board 220 . Accordingly, in the direction in which the beam 51 is irradiated from the source 50 , how the intensity of each area of the beam 51 changes can be easily calculated and estimated.

In addition, although it has been described that one intermediate plane 205 is provided in FIGS. 10 and 11 , the present invention is not limited thereto, and a plurality of intermediate planes are provided between the first test board 210 and the second test board 220 . can be provided, and the estimated defective rate for the target area of a plurality of intermediate planes can be calculated and estimated by the above-described method, from which the intensity for each area of the beam 51 in the plurality of intermediate planes can be calculated and estimated can be

The estimated defective rate of the virtual intermediate plane 205 calculated by the calculation module 240 and/or the intensity of the beam 51 irradiated to the virtual intermediate plane 205 is transmitted to a display device (not shown), etc. can be

The display device (not shown) calculates the estimated defective rate of the virtual intermediate plane 205 calculated by the calculation module 240 and/or the intensity of the beam 51 irradiated to the virtual intermediate plane 205 . can be shown visually. For example, the display device (not shown) may be a monitor, but is not limited thereto.

Unlike the beam intensity calculation system according to the second embodiment described above, according to the beam intensity calculation system according to the first modified example of the second embodiment, the first test board 210 and the second test board 220 overlap The defect rate caused by the can be corrected. Hereinafter, a beam intensity calculation system according to a first modification of the second embodiment will be described with reference to FIG. 12 .

12A is a view showing the defective rate of the first semiconductor device under test measured by the defective rate storage module of the intelligent beam intensity calculation system according to the first modified example of the second embodiment of the present application by arranging the first test board alone. It is a view for explaining the storage, and (b) of FIG. 12 is the defect rate storage module of the intelligent beam intensity calculation system according to the first modified example of the second embodiment of the present application measured by placing the second test board alone It is a view for explaining storing the defect rate of the second semiconductor device under test, and FIG. 12 (c) is an intelligent beam intensity calculation system calculation module according to a first modification of the second embodiment of the present application, the first test board and a diagram for explaining a process of calculating the correction defect rate using the defect rates of the first semiconductor element under test and the defect rates of the second semiconductor element under test measured by disposing the second test board at the same time.

Referring to FIG. 12 , the defective rate storage module 230 includes the first semiconductor device under test 201 installed alone and disposed on the first test board 210 and the second test board separately installed. The defective rate of each of the second semiconductor devices under test 202 disposed at 220 may be measured and stored. The defective rate storage module 230 includes the first semiconductor device under test 201 and the second semiconductor device under test of the first test board 210 and the second test board 220 arranged in a straight line. 202) Each defect rate can be measured and stored.

For example, the defective rate storage module 230 is installed alone as shown in FIG. The defect rate can be measured and stored as 200, and the defect rate of the second semiconductor device under test 202 installed alone and disposed on the second test board 220 as shown in FIG. 12(b) is set to 150. can be measured and stored.

Thereafter, as shown in FIG. 12C , in a state in which the first test board 210 and the second test board 220 are overlapped and disposed, the first semiconductor device under test 201 is The defect rate and the defect rate of the second semiconductor device under test 202 may be measured and stored. That is, in a state in which the first test board 210 is disposed at the same position as that of FIG. 12(a) and the second test board 220 is disposed at the same position as that of FIG. 12(b), the beam ( 51), the defective rates of the first semiconductor device under test 201 and the second semiconductor device under test 202 according to the irradiation may be measured and stored.

That is, as shown in (c) of FIG. 12 , the beam 51 irradiated from the source 50 penetrates the first test board 210 and passes through the second test board 220 . The second test surface 221 may be irradiated to the second semiconductor device under test 202 disposed on the test surface 221 . In this case, the beam 51 passing through the first test board 210 and irradiated to the second semiconductor device under test 202 is relatively higher than when the second test board 220 is installed alone. strength may be weakened.

The calculation module 240 calculates a correction defect rate to correct the defect rate of the second semiconductor device under test 202 of the second test board 220 arranged in a straight line with the first test board 210 . can For example, the defective rate of the first semiconductor element under test 201 installed alone is 200, and the defect rate of the second semiconductor element 202 installed alone is 150. When the defect rate of the second semiconductor device under test 202 of the second test board 220 disposed in a straight line with the first test board 210 is 100, the corrected defect rate is calculated by subtracting 100 from 150. It can be a value of 50. That is, a corrected defective rate, which is a value for reducing the defective rate according to the penetration of the beam 51 through the first test board 210 , may be calculated, and the estimated defective rate of the intermediate plane according to the embodiment described with reference to FIGS. 8 to 11 . The correction defect rate may be added to . Accordingly, the reliability of the estimated defective rate value of the intermediate plane may be improved, and the reliability of the intensity value of the beam 51 may be improved.

Unlike the beam intensity calculation system according to the second embodiment described above, according to the beam intensity calculation system according to the second modification of the second embodiment, the virtual intermediate plane 205 is the target area 206 and the non-target area. an area 208 , wherein the estimated defective rate of the non-target area 208 is calculated and estimated using the estimated defective rate of the adjacent target area 206 , whereby the non-target area 208 is The intensity of the corresponding area of the beam 51 can be calculated and estimated. Hereinafter, a beam intensity calculation system and method according to a second modified example of the second embodiment of the present application will be described with reference to FIG. 13 .

13 is a view for explaining a process in which the calculation module of the intelligent beam intensity calculation system according to a second modified example of the second embodiment of the present application calculates the intensity of the beam irradiated to the mounted area and the non-mounted area on a virtual intermediate plane; FIG. to be.

Referring to FIG. 13 , the intermediate plane 205 may include a target area 206 and a non-target area 208 .

The target region 206 includes, on the intermediate plane 205 , a mounting region 216 in which the first semiconductor device under test 201 is mounted on the first test board 210 and the second test board ( In 220 , it may be a region overlapping the mounting region 226 in which the second semiconductor device under test 202 is mounted. The estimated defective rate of the target region 206 is the defective rate of the mounting regions 216 and 226 , the distance between the intermediate plane 205 and the first test board 210 , and the intermediate plane 205 and the second test board 210 . Using the distance between the two test boards 220, it can be calculated and estimated by the method described with reference to FIGS. 8 to 11 .

The non-target region 208 includes an unmounted region 218 in which the first semiconductor device under test 201 is not mounted on the first test board 210 and the second test board 210 on the intermediate plane 205 . The board 220 may be a region overlapping an unmounted region 228 in which the second semiconductor device under test 202 is not mounted.

According to an embodiment, the estimated defective rate of the non-target area 208 may be calculated and estimated using the estimated defective rate of the target area 206 calculated and estimated by the above-described method. In other words, as described with reference to FIGS. 1 to 4 , it may be calculated and estimated using the estimated defective rate of the target area 206 adjacent to the non-target area 208 .

Alternatively, according to another embodiment, the estimated defective rate of the non-target area 208 is estimated and calculated by the method described with reference to FIGS. 1 to 4 for the unmounted areas 218 and 228, The defective rate of the non-mounted regions 218 and 228 , the distance between the intermediate plane 205 and the first test board 210 , and the distance between the intermediate plane 205 and the second test board 220 are measured Using, it can be calculated and estimated in the method described with reference to FIGS. 8 to 11 .

Also, according to an embodiment, in the above-described embodiments, the size of the beam 51 may be larger than the size of the test boards 110 , 210 , and 220 . Accordingly, the dose difference for each region of the beam 51 may be minimized, and as a result, the reliability of the estimation and calculation of the intensity of the beam 51 may be increased.

In general, the difference between the dose at the center and the edge of the beam 51 may be large, and if, as described above, the size of the beam 51 is smaller than the size of the test boards 110 , 210 , 220 or Alternatively, in the same case, when the estimated defective rates of the non-mounted areas at various locations are calculated using the same interpolation method (eg, an average value), a large error may occur depending on the location of the non-mounted area.

However, as described above, according to an embodiment, the size of the beam 51 may be larger than the size of the test boards 110 , 210 , and 220 , and thus, the intensity of the beam 51 for each area. Reliability of estimation and calculation results may be improved.

As mentioned above, although the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to specific embodiments and should be construed according to the appended claims. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present invention.

1: first area
2: second area
3: Target area
50: sailor
51: beam
100: semiconductor element under test
110: test board
120: defective rate storage module
130: calculation module
150: movement control module
201: first semiconductor element under test
202: second semiconductor element under test
205: virtual midplane
210: first test board
220: second test board
230: defective rate storage module
240: calculation module

Claims (8)

a test board on which a plurality of semiconductor devices under test are mounted, the test board having a test surface to which a beam is irradiated;
a defective rate storage module for checking and storing defective rates of the plurality of semiconductor devices under test mounted on the test surface of the test board; and
A calculation module for calculating the intensity of the beam irradiated to the test surface of the test board by using the defective rate stored in the defective rate storage module,
and calculating, in the calculation module, the intensity of the beam irradiated to the test surface by using a defective rate of the plurality of semiconductor devices under test.
The method of claim 1,
The test surface of the test board includes an unmounted region on which the plurality of semiconductor devices under test are not mounted, and a mounting region on which the plurality of semiconductor devices under test are mounted.
The intensity of the beam irradiated to the unmounted area is calculated by interpolating the defective rate of the semiconductor device under test in the mounting area adjacent to the unmounted area to calculate an estimated defective rate, and calculating using the estimated defective rate. century counting system.
3. The method of claim 2,
The intelligent beam intensity calculation system including a plurality of pixels formed by dividing the unmounted area into a virtual grid.
a first test board on which a plurality of first semiconductor devices under test are mounted, the first test board having a first test surface to which a beam is irradiated;
a second test board spaced apart from a source emitting the beam with the first test board interposed therebetween and having a second test surface on which a plurality of second semiconductor devices under test are mounted and irradiated with the beam;
a defective rate storage module for checking and storing defective rates of the first and second semiconductor devices under test mounted on the first test surface and the second test surface; and
A calculation module for calculating the intensity of the beam irradiated to a virtual intermediate plane defined between the first test board and the second test board by using the defective rate stored in the defective rate storage module Intelligent beam intensity calculation system.
5. The method of claim 4,
In the calculation module,
Intelligent beam intensity comprising calculating the intensity of the beam irradiated to the first test surface and the second test surface using the defective rates of the first semiconductor element under test and the second semiconductor element under test, respectively calculation system.
6. The method of claim 5,
The intensity of the beam irradiated to the intermediate plane is,
Estimated using the defective rate of the first semiconductor element under test, the distance between the first test board and the intermediate plane, the defect rate of the second semiconductor element under test, and the distance between the second test board and the intermediate plane An intelligent beam intensity calculation system comprising calculating a defective rate and calculating using the estimated defective rate.
mounting a plurality of semiconductor devices under test on a test surface of a test board;
irradiating a beam to the test surface;
checking and storing defective rates of the plurality of semiconductor devices under test mounted on the test surface of the test board; and
and calculating the intensity of the beam irradiated to the test surface of the test board by using the defect rate of the semiconductor device under test.
mounting a plurality of first semiconductor devices under test on a first test surface of a first test board;
mounting a plurality of second semiconductor devices under test on a second test surface of a second test board spaced apart from a source emitting the beam with the first test board interposed therebetween;
irradiating a beam to the first test surface and the second test surface;
checking and storing defective rates of the first semiconductor device under test and the second semiconductor device under test mounted on the first test surface and the second test surface; and
Intelligent beam intensity calculation comprising the step of calculating the intensity of the beam irradiated to a virtual intermediate plane defined between the first test board and the second test board by using the stored defect rate Way.

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