KR102435395B1 - Sampling switch for high dynamic input range and method for operating the same - Google Patents

Abstract

Disclosed are a sampling switch for a high dynamic input range and a driving method thereof, which can resolve the problem of body leakage which can occur in the process of sampling input between a negative power voltage and a positive power voltage. According to one embodiment of the present application, the sampling switch for a high dynamic input range comprises: a positive voltage charging unit including a first capacitor provided to charge a positive power voltage in a hold mode; a negative charging unit including a second capacitor provided to charge a negative power voltage in a sample mode; and a main switch turned on by the positive power voltage charged in the first capacitor in the sample mode to sample an input signal, and turned off by the negative power voltage charged in the second capacitor in the hold mode to hold the input signal.

Description

Sampling switch for high dynamic input range and its driving method

The present application relates to a sampling switch for a high dynamic input range and a method of driving the same. For example, the present application relates to a symmetric bootstrap switch switch capable of operating over a wide input range from a negative supply voltage to a positive supply voltage through a symmetric circuit for charging a negative supply voltage, and a method for driving the same. it's about

The sampling switch occupies an important part of performing a Sample & Hold operation in an analog-digital converter (ADC). In particular, as miniaturized and high-speed devices have recently appeared, low-power analog-to-digital converters that can keep pace with them have received attention.

On the other hand, as the power (supply) voltage of the analog-to-digital converter gradually decreases, a problem may occur that the high voltage of the clock may not sufficiently provide the voltage difference between the gate and the source necessary to turn on the MOS switch. .

In this regard, FIG. 1 is a diagram illustrating a conventional bootstrap switch. Referring to FIG. 1 , in a conventional bootstrap switch, a predetermined voltage is charged to a capacitor when in a hold mode, and a voltage charged to a capacitor at the gate of a MOS switch when in a sample mode. By supplying a voltage greater than the input voltage based on

However, in the conventional bootstrap switch, 0V voltage is supplied to the gate of the MOS switch to turn off the MOS switch in the hold mode, so a lower negative voltage compared to the threshold voltage value When an input voltage is applied, an off operation may not be smoothly performed, so there is a problem in that an input range is limited.

The background technology of the present application is disclosed in Korean Patent Publication No. 10-1994800.

The present application is intended to solve the problems of the prior art described above, and unlike the conventional bootstrap switch having a limited input range by mounting a capacitor for charging a negative power supply voltage, a high voltage from a negative supply voltage to a positive supply voltage is provided. An object of the present invention is to provide a sampling switch having a high dynamic input range.

However, the technical problems to be achieved by the embodiments of the present application are not limited to the technical problems as described above, and other technical problems may exist.

As a technical means for achieving the above technical problem, a sampling switch for a high dynamic input range according to an embodiment of the present application is a positive voltage charging unit including a first capacitor provided to charge a positive power supply voltage in a hold mode , a negative voltage charging unit including a second capacitor provided to charge a negative power voltage in the sample mode, and the positive power voltage charged in the first capacitor in the sample mode to be turned on to sample the input signal and a main switch that is turned off by the negative power voltage charged in the second capacitor in the hold mode to hold the input signal.

In addition, the sampling switch for a high dynamic input range according to an exemplary embodiment of the present disclosure may include a clock generation circuit that is alternately switched to a high or low state.

In addition, the sampling switch may be driven in synchronization with the clock generation circuit.

Also, the sample mode may correspond to the low-state clock, and the hold mode may correspond to the high-state clock.

In addition, the power supply voltage is represented by V _DD , and the positive voltage charging unit is a PMOS transistor having a source connected to a V _DD /2 node, a drain connected to the top node of the first capacitor, and a gate connected to the gate of the main switch A first switch, a source connected to the top node of the first capacitor, a drain connected to the gate of the main switch, and a second switch that is a PMOS transistor having a gate connected to the clock generation circuit, a source connected to a -V _DD /2 node , a third switch which is an NMOS transistor having a drain connected to the bottom node of the first capacitor and a gate connected to the clock generation circuit, a source connected to the bottom node of the first capacitor, and a source connected to the main switch and the input signal and a fourth switch which is an NMOS transistor having a drain connected to an input node, which is a node to which is applied, and a gate connected to the gate of the main switch.

In addition, the negative voltage charging unit may include a fifth switch that is an NMOS transistor having a source connected to the top node of the second capacitor, a drain connected to the gate of the main switch, and a gate connected to the clock generation circuit, -V _DD /2 node A sixth switch that is an NMOS transistor having a source connected to the second capacitor, a drain connected to the top node of the second capacitor, and a gate connected to the gate of the main switch, a source connected to the bottom node of the second capacitor, and a source connected to the main switch and a seventh switch which is a PMOS transistor having a drain connected to an input node that is a node to which the input signal is applied and a gate connected to the gate of the main switch, and a source connected to a V _DD /2 node, and a bottom node of the second capacitor and an eighth switch which is a PMOS transistor having a drain and a gate connected to the clock generation circuit.

In addition, the sampling switch for a high dynamic input range according to an embodiment of the present application includes a source connected to the V _{DD /2 node between the V DD /} 2 node and the first switch, and a source connected to the first switch. a first additional switch which is a PMOS transistor including a drain and a gate connected in a reverse direction to the clock generation circuit and a source connected to the -V _DD /2 node between the -V _DD /2 node and the sixth switch; A second additional switch which is an NMOS transistor including a drain connected to the source of the 6-switch and a gate connected in a reverse direction to the clock generation circuit may be included.

In addition, the sampling switch for a high dynamic input range according to an embodiment of the present application is connected to the channel of the first switch to apply 2*V _DD in a high state, and V _DD in a low state The first clock generator circuit for applying /2 and the sixth switch are connected to the channel of the sixth switch to apply -V _DD /2 in a high state and -2*V DD to apply -2*V _DD in a low state. It may include a two-clock generation circuit.

Also, a channel of the first switch may be connected to a top node of the first capacitor, and a channel of the sixth switch may be connected to a top node of the second capacitor.

Meanwhile, in the method of driving a sampling switch for a high dynamic input range according to an embodiment of the present application, (a) the negative voltage charging unit charges the second capacitor with the negative power supply voltage in the sample mode, and the first sampling an input signal by turning on the main switch by the positive power supply voltage charged in a capacitor; and (b) charging the positive power supply voltage to the first capacitor by the positive voltage charging unit in the hold mode and turning off the main switch by the negative power voltage charged in the second capacitor to hold the input signal.

Meanwhile, the analog-to-digital converter including a sampling switch for a high dynamic input range according to an embodiment of the present application includes a comparator for outputting a digital signal corresponding to the sampling switch and the input signal sampled by the sampling switch. may include

The above-described problem solving means are merely exemplary, and should not be construed as limiting the present application. In addition to the exemplary embodiments described above, additional embodiments may exist in the drawings and detailed description.

According to the above-described problem solving means of the present application, a high dynamic input range (from a negative power supply voltage to a positive power supply voltage ( A sampling switch with a High Dynamic Input Range) can be provided.

According to the above-described problem solving means of the present application, the power supply voltage range and the range of the bias voltage for switching the low and high states of the clock are maintained at V _DD through a structure in which the conventional bootstrap switch is symmetrical. , the input range can be extended to 2*V _DD .

According to the above-described problem solving means of the present application, it is possible to solve a body leakage problem that may occur in the process of sampling an input between the negative power supply voltage (-V _DD ) and the positive power supply voltage (V _DD ).

However, the effects obtainable herein are not limited to the above-described effects, and other effects may exist.

1 is a diagram illustrating a conventional bootstrap switch.
2 is a circuit diagram of a sampling switch for a high dynamic input range according to an embodiment of the present disclosure including a positive voltage charging unit, a negative voltage charging unit, and a main switch.
3 is a circuit diagram of a sampling switch for high dynamic input range according to an embodiment of the present disclosure including a first additional switch and a second additional switch.
FIG. 4 is a graph illustrating voltages charged over time in a first capacitor and a second capacitor of the sampling switch shown in FIG. 3 .
5 is a circuit diagram of a sampling switch for a high dynamic input range according to an embodiment of the present disclosure including a first clock generation circuit and a second clock generation circuit.
6 is a circuit diagram of a sampling switch for a high dynamic input range according to an embodiment of the present application in which the channels of the first switch and the sixth switch are connected to the top node of the first capacitor and the second capacitor, respectively.
FIG. 7 is a graph illustrating voltages charged over time in a first capacitor and a second capacitor of the sampling switch shown in FIG. 6 .
8A to 8E are diagrams for explaining the reformation of input/output waveforms of a sampling switch for a high dynamic input range according to an embodiment of the present application.
9 is a diagram illustrating a comparison of output waveforms of a sampling switch for a high dynamic input range according to an embodiment of the present application and a conventional bootstrap switch corresponding to a predetermined input waveform.
10 is a flowchart illustrating a method of driving a sampling switch for a high dynamic input range according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art to which the present application pertains can easily implement them. However, the present application may be implemented in several different forms and is not limited to the embodiments described herein. And in order to clearly explain the present application in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

Throughout this specification, when a part is said to be “connected” to another part, it is not only “directly connected” but also “electrically connected” or “indirectly connected” with another element interposed therebetween. "Including cases where

Throughout this specification, when it is said that a member is positioned "on", "on", "on", "under", "under", or "under" another member, this means that a member is located on the other member. It includes not only the case where they are in contact, but also the case where another member exists between two members.

Throughout this specification, when a part "includes" a component, it means that other components may be further included, rather than excluding other components, unless otherwise stated.

The present application relates to a sampling switch for a high dynamic input range and a method of driving the same. For example, the present application relates to a symmetric bootstrap switch switch capable of operating over a wide input range from a negative supply voltage to a positive supply voltage through a symmetric circuit for charging a negative supply voltage, and a method for driving the same. it's about

Hereinafter, the limitation on the input range generated by the conventional bootstrap switch shown in FIG. 1 will be described below, and for the high dynamic input range disclosed herein with reference to FIGS. 2 to 7 . The function and operation of the sampling switch 10 will be described in detail.

Specifically, in the conventional bootstrap switch shown in FIG. 1 , in the sample mode, M ₂ , M ₆ is turned on, and M ₁ , M ₃ , M ₄ , and M ₅ are turned off, which results in the voltage of the bottom node of the C ₁ capacitor. is equal to V _in , and since V _DD is charged in C ₁ , the voltage at the top node of the C ₁ capacitor becomes V _in +V _DD . Accordingly, the gate-source voltage difference of M ₀ is maintained at V _DD regardless of V _in , so that the output V _out samples the input signal V _in .

Conversely, in the hold mode, in the conventional bootstrap switch shown in FIG. 1 , M ₂ is turned off and M ₅ is turned on. In addition, as M ₃ and M ₄ are turned on, the X node becomes ground, so that M ₁ is turned on and M ₆ is turned off. Accordingly, the bottom node of the C ₁ capacitor is grounded, and the voltage of the top node becomes V _DD , so that the C ₁ capacitor is charged with V _DD . Also, since the X node is the ground, the gate-source voltage difference of M ₀ becomes negative regardless of V _in and turns off, so the previous value is held.

However, in the hold mode, when the input signal (V _in ) has a negative value, the gate-source voltage difference of M ₀ may be greater than the threshold value (V _th ) even if the X node is grounded. There is a problem that can lead to sampling values that do not exist.

2 is a circuit diagram of a sampling switch for a high dynamic input range according to an embodiment of the present disclosure including a positive voltage charging unit, a negative voltage charging unit, and a main switch.

2, the sampling switch 10 (hereinafter, referred to as 'sampling switch 10') for a high dynamic input range according to an embodiment of the present application is a positive voltage charging unit 110, a negative voltage charging unit ( 120 ) and a main switch 130 . Also, referring to FIG. 2 , the main switch 130 may be indicated as M ₀ .

The positive voltage charging unit 110 may include a first capacitor C ₁ provided to charge the positive power supply voltage V _DD in the hold mode. Meanwhile, in the description of the embodiment of the present application, the power supply voltage may be represented by V _DD .

The negative voltage charging unit 120 may include a second capacitor C ₂ provided to charge the negative power voltage -V _DD in the Sample mode.

The main switch 130 may be turned on by the positive power voltage V _DD charged in the first capacitor C ₁ in the sample mode to sample the input signal V _in . Also, the main switch 130 may be turned off by the negative power voltage -V _DD charged in the second capacitor C ₂ in the hold mode to hold the input signal V _in .

Meanwhile, in relation to the hold mode and the sample mode, the sampling switch 10 may include a clock generation circuit CK that is alternately switched to a high or low state. In this regard, the sampling switch 10 is driven in synchronization with the clock generation circuit CK, the sample mode corresponds to a low-state clock, and the hold mode corresponds to a high-state clock. can

및

를 서로 맞바꾼 형태의 회로로 이해될 수 있다.However, the combination between the high-low state of the clock generation circuit CK and the sample mode-hold mode of the sampling switch 10 may be implemented contrary to the above description according to an embodiment of the present application. For example, according to another exemplary embodiment of the present disclosure, when the clock generation circuit CK is in a high state, the sampling switch 10 operates in a sample mode, and the clock generation circuit CK is in a low state. When , the sampling switch 10 may operate in a hold mode, and this other embodiment of the present application is shown in FIGS. 2 , 3 , 5 and 6 .

and

can be understood as a type of circuit in which .

Comparing FIGS. 1 and 2 with each other, compared to the conventional bootstrap switch ( FIG. 1 ), the sampling switch ( FIG. 2 ) according to an exemplary embodiment of the present invention shows that the main switch of the conventional bootstrap switch has a negative input voltage in the hold mode. _In order to solve the problem that the sampling operation, not the holding operation, occurs undesirably by being turned on by the It can be seen that the second capacitor (C ₂ ) for charging (-V _DD ) is additionally included in the circuit.

Specifically, referring to FIG. 2 , the positive voltage charging unit 110 includes a source connected to a V _DD /2 node, a drain connected to the top node of the first capacitor C ₁ , and a main switch 130 . It may include a first switch (M ₁ ) which is a PMOS transistor having a gate connected to the gate (Gate) of the PMOS transistor.

In addition, the positive voltage charging unit 110 is a second PMOS transistor having a source connected to the top node of the first capacitor C ₁ , a drain connected to the gate of the main switch 130 , and a gate connected to the clock generation circuit CK. It may include a switch (M ₂ ).

In addition, the positive voltage charging unit 110 is a third switch which is an NMOS transistor having a source connected to the -V _DD /2 node, a drain connected to the bottom node of the first capacitor C ₁ , and a gate connected to the clock generation circuit CK. (M ₃ ) may be included.

In addition, the positive voltage charging unit 110 has a source connected to the bottom node of the first capacitor (C ₁ ), a drain connected to the source of the main switch 130 and connected to an input node that is a node to which the input signal (V _in ) is applied, and A fourth switch M ₄ that is an NMOS transistor having a gate connected to the gate of the main switch 130 may be included.

In addition, referring to FIG. 2 , the negative voltage charging unit 120 includes a source connected to the top node of the second capacitor C ₂ , a drain connected to the gate of the main switch 130 , and a gate connected to the clock generation circuit CK. It may include a fifth switch (M ₅ ) which is an NMOS transistor having a

In addition, the negative voltage charging unit 120 is a sixth NMOS transistor having a source connected to the -V _DD /2 node, a drain connected to the top node of the second capacitor C ₂ , and a gate connected to the gate of the main switch 130 . It may include a switch (M ₆ ).

In addition, the negative voltage charging unit 120 has a source connected to the bottom node of the second capacitor (C ₂ ), a drain connected to the source of the main switch 130 and connected to an input node that is a node to which the input signal (V _in ) is applied, and A seventh switch M ₇ which is a PMOS transistor having a gate connected to the gate of the main switch 130 may be included.

In addition, the negative voltage charging unit 120 is a PMOS transistor having a source connected to the V _DD /2 node, a drain connected to the bottom node of the second capacitor C ₂ , and a gate connected to the clock generation circuit CK, an eighth switch ( M ₈ ) may be included.

In summary, the sampling switch 10 disclosed herein charges the positive power supply voltage (V _DD ) to the first capacitor (C ₁ ) in the hold mode, and thus the positive power of the charged first capacitor (C ₁ ) The voltage (V _DD ) is applied to the gate-source of the main switch 130 in the sample mode to turn on the main switch 130, and vice versa in the sample mode, _a negative power supply voltage ( -V _DD ) is charged, and the negative power supply voltage (-V _DD ) of the second capacitor C ₂ charged in this way is applied to the gate-source of the main switch 130 in the hold mode to close the main switch 130 . can be turned off.

In other words, the sampling switch 10 is a first capacitor (C ₁ ) for charging the positive power supply voltage (V _DD ) and a second capacitor (C ₂ ) for charging the negative power supply voltage (-V _DD ) Using The top plate (top node) of the two capacitors is boosted by the voltage charged in each capacitor from the input voltage, and the boosted voltage is synchronized with the clock generation circuit and supplied to the gate voltage side of the main switch 130 to provide an input signal ( Regardless of the size of V _in ), when the gate-source voltage of the main switch 130 is on, it is a positive power voltage (V _DD ), and when it is off, a negative power supply voltage (-V _DD ) It can operate so that this is applied.

Meanwhile, the sampling switch 10 disclosed herein may be a module mounted on an analog-to-digital converter (ADC). In this regard, an analog-to-digital converter (ADC) including a sampling switch for a high dynamic input range disclosed herein is a digital signal corresponding to the sampling switch 10 and the input signal sampled by the sampling switch 10 described above. It may include a comparator for outputting a signal. Illustratively, the analog-to-digital converter (ADC) may be a sequential comparison type ADC (SAR ADC), but is not limited thereto, and the sampling switch 10 disclosed herein is a conventional analog analog converter such as a flash ADC. - It can be widely applied not only to digital converters, but also to various types of ADC circuits that are newly developed in the future. On the other hand, the sampling switch 10 disclosed herein extends the input range from the negative power supply voltage (-V _DD ) to the positive power supply voltage (V _DD ), so that the power supply voltage is relatively small at the front end of the low-power ADC. It can operate as a more suitable sampling circuit.

As another example, the sampling switch 10 disclosed herein may be a module mounted on a switched-capacitor filter.

3 is a circuit diagram of a sampling switch for high dynamic input range according to an embodiment of the present disclosure including a first additional switch and a second additional switch.

Referring to FIG. 3 , the positive voltage charging unit 110 is disposed between the V _DD /2 node and the first switch M ₁ , a source connected to the V _DD /2 node, and a drain connected to the source of the first switch M ₁ . and a first additional switch M _{1 ′} that is a PMOS transistor including a gate connected in a reverse direction to the clock generation circuit CK.

Also, referring to FIG. 3 , the negative voltage charging unit 120 is connected between the -V _DD /2 node and the sixth switch M ₆ , the source connected to the -V _DD /2 node, and the sixth switch M ₆ . A second additional switch M _{6 ′} which is an NMOS transistor including a drain connected to the source and a gate connected in a reverse direction to the clock generation circuit CK may be included.

In this regard, the sampling switch 10 having the structure shown in FIG. 2 is a first capacitor (C ₁ ) when a large negative input (eg, a low voltage close to -V _DD ) is applied in the sample mode. Since a low voltage close to 0V may be applied to the voltage of the top node of , a problem in which the first switch M ₁ that should be turned off is turned on may occur.

In consideration of this, the sampling switch 10 shown in FIG. 3 additionally arranges a first additional switch (M _{1 ′} ) and a second additional switch (M _{6 ′} ) in the circuit to form the top of the first capacitor (C ₁ ). Even when the voltage of the node is low, the first switch M ₁ may be turned off so that a normal sampling operation may be performed. If the first switch (M ₁ ) is removed and replaced with the first additional switch (M _{1 ′} ), the voltage of the top node of the first capacitor (C ₁ ) in the input signal (V _in ) close to the positive supply voltage (V _DD ) As the value of this 2*V _DD approaches the value of the first additional switch (M _1' ), it may cause a problem that the first switch (M ₁ ) and the first additional switch (M _1' ) are placed side by side to complement each other It can be designed to do the job.

In addition, the first additional switch (M _{1 '} ) when the voltage of the top node of the first capacitor (C ₁ ) increases to 2*V _DD , the first switch (M ₁ ) and the first additional switch (M _{1 '} ) There is also an effect of alleviating the stress applied to the drain-source, and similarly, the second additional switch M _{6 ′} may be disposed in parallel with the sixth switch M ₆ .

According to an embodiment of the present application, in the sample mode in which the clock is low (Low) state, the first additional switch (M _{1 ′} ) and the third switch (M ₃ ) are turned off, the second additional switch (M _{6 ′} ) and the second 8 switch (M ₈ ) is turned on. In addition, in the sample mode, the second switch (M ₂ ) is turned on and the fifth switch (M ₅ ) is turned off. Due to this, the voltage of the X node (ie, the gate node of the main switch 130 ) increases, so that the fourth switch (M ₄ ) ) and the sixth switch (M ₆ ) are turned on, and the first switch (M ₁ ) and the seventh switch (M ₇ ) are turned off in the sample mode. Due to this, in the sample mode, the voltage of the bottom node of the first capacitor C ₁ becomes equal to the input signal V _in , and since the positive power voltage V _DD is charged in the first capacitor C ₁ , the first The voltage at the top node of the capacitor C ₁ becomes V _in +V _DD .

Accordingly, the gate-source voltage difference of the main switch 130 becomes a positive power supply voltage V _DD regardless of the input signal V _in , so that the output V _out samples the input signal V _in . At this time, the top node of the second capacitor C2 is connected to -V _DD /2 and the bottom node is connected to V _DD /2 so that the second capacitor C2 charges the negative power voltage (-VDD) during the sample mode. do.

In addition, in the hold mode in which the clock is high, the second additional switch M _{6 ′} and the eighth switch M ₈ are turned off, and the first additional switch M _{1 ′} and the third switch M ₃ are turns on In addition, the fifth switch (M ₅ ) is turned on, the second switch (M ₂ ) is turned off due to this lowering the voltage of the X node, the fourth switch (M ₄ ) and the sixth switch (M ₆ ) are turned off, the first The switch M ₁ and the seventh switch M ₇ are turned on in the hold mode. In addition, due to this, in the hold mode, the voltage of the bottom node of the second capacitor C ₂ becomes equal to the input signal V _in , and the negative power voltage (-V _DD ) is charged to the second capacitor C ₂ . Therefore, the voltage of the top node of the second capacitor (C ₂ ) becomes V _in -V _DD .

Accordingly, the gate-source voltage difference of the main switch 130 becomes -V _DD regardless of the input signal V _in , so that the output V _out holds the input signal V _in . At this time, the top node of the first capacitor C ₁ is connected to V _DD /2 and the bottom node is connected to -V _DD /2 so that the first capacitor C1 is charged with the positive power supply voltage V _DD during the hold mode. will do

In addition, the sampling switch 10 disclosed herein has a full-scale input range including a positive input range and a negative input range, unlike the conventional bootstrap switch that operates well only in a positive input range. In order to lower the operating _point as _{a whole} to _{operate well} for It may be designed to charge.

Similarly, in the clock generation circuit CK, the high state and the low state correspond to the voltage for charging the capacitor, and the high state corresponds to the voltage value of V _DD /2, and the low state corresponds to the voltage value of V DD /2. ) state can be designed to operate to correspond to a voltage value of -V _DD /2.

FIG. 4 is a graph illustrating voltages charged over time in a first capacitor and a second capacitor of the sampling switch shown in FIG. 3 .

Referring to FIG. 4 , the sampling switch 10 according to an embodiment of the present application described with reference to FIG. 3 has a voltage charged in the first capacitor C ₁ and the second capacitor C ₂ , the first switch M ₁ . ) and a phenomenon in which a positive power supply voltage (V _DD ) or a negative power supply voltage (-V _DD ) cannot be continuously maintained due to body leakage occurring in the sixth switch (M ₆ ) may appear. In this regard, a circuit structure in consideration of body bias for improving body leakage will be described below.

5 is a circuit diagram of a sampling switch for a high dynamic input range according to an embodiment of the present disclosure including a first clock generation circuit and a second clock generation circuit.

Referring to FIG. 5 , the sampling switch 10 according to an embodiment of the present application is connected to the channel of the first switch M ₁ to apply 2*V _DD in a high state, and a low state may include a first clock generation circuit CK for applying V _DD /2.

In addition, referring to FIG. 5 , the sampling switch 10 according to an embodiment of the present application is connected to the channel of the sixth switch M ₆ to apply -V _DD /2 in a high state, and a low ( Low) state and may include a second clock generation circuit CK for applying -2*V _DD .

In this regard, the first clock generation circuit CK and the second clock generation circuit CK improve the body leakage of the above-described first switch M ₁ and the sixth switch M ₆ while improving the body leakage of the transistor ( In order not to affect the threshold value V _th of the switch), voltage values of a high state and a low state may be determined as the above-described values.

6 is a circuit diagram of a sampling switch for a high dynamic input range according to an embodiment of the present application in which the channels of the first switch and the sixth switch are connected to the top node of the first capacitor and the second capacitor, respectively.

Referring to FIG. 6 , in the sampling switch 10 according to an embodiment of the present application, the channel of the first switch M ₁ is connected to the top node of the first capacitor C ₁ , and the sixth switch M ₆ ) A channel of may be connected to the top node of the second capacitor (C ₂ ). In this regard, the sampling switch 10 shown in FIG. 6 uses the voltage of the top plate of the first capacitor (C ₁ ) or the second capacitor (C ₂ ) compared to the sampling switch 10 of the present application shown in FIG. 5 . Therefore, there is an advantage that body leakage can be improved without using an additional clock generation circuit.

FIG. 7 is a graph illustrating voltages charged over time in a first capacitor and a second capacitor of the sampling switch shown in FIG. 6 .

Referring to FIG. 7 , through improvement of body leakage using the top plate voltage of the capacitor, the voltage charged in the first capacitor ( C ₁ ) and the second capacitor ( C ₂ ) is positive power differently from the graph shown in FIG. 4 . It can be seen that the voltage (V _DD ) or the negative power supply voltage (-V _DD ) is continuously maintained.

8A to 8E are diagrams for explaining the reformation of input/output waveforms of a sampling switch for a high dynamic input range according to an embodiment of the present application.

Specifically, FIG. 8A shows the shape of the input signal V _in , FIG. 8B shows the shape of the voltage applied by the clock generation circuit CK, and FIG. 8C shows the gate-source of the main switch 130 in the circuit. The voltage V _GS is shown, FIG. 8D shows the reformation of V _GS , and FIG. 8E shows the input signal V _in and the output derived from the input signal V _in through a sample and hold operation by the sampling switch 10 . It is shown by superimposing the open shape of the signal (V _out ).

_8A to _8D , when the sampling switch 10 disclosed herein is used, the main switch ( It can be seen that a positive power voltage (V _DD ) or a negative power supply voltage (-V _DD ) is constantly applied to the gate-source of 130 .

In addition, referring to FIG. 8E , when the main switch 130 is turned on in synchronization with the clock generation circuit by the sampling switch 10 disclosed herein, the input signal V _in is sampled, and the main When the switch 130 is turned off, it can be seen that the operation of holding the input signal V _in is smoothly performed regardless of the sign or size of the input signal V _in .

9 is a diagram illustrating a comparison of output waveforms of a sampling switch for a high dynamic input range according to an embodiment of the present application and a conventional bootstrap switch corresponding to a predetermined input waveform.

Figure 9 (a) shows the waveform of the input signal (V _in ) having a frequency of 5 MHz and an amplitude of 0.8 V, and Figure 9 (b) is a conventional bootstrap when the sampling frequency is 100 MHz. The waveform of the output signal by the switch is shown, and FIG. 9(c) shows the waveform of the output signal of the symmetric bootstrap switch, which is the sampling switch 10 disclosed herein at the same sampling frequency.

9, the conventional bootstrap switch does not properly perform a holding operation for a negative input voltage smaller than the threshold voltage of the main switch, and even in the hold mode, the input signal (V _in ) On the other hand, it can be seen that the sampling switch 10 disclosed herein can normally perform a holding operation with respect to the entire negative input voltage.

Hereinafter, based on the details described above, the operation flow of the present application will be briefly reviewed.

10 is a flowchart illustrating a method of driving a sampling switch for a high dynamic input range according to an embodiment of the present disclosure.

The method of driving the sampling switch for a high dynamic input range shown in FIG. 10 may be performed by the sampling switch 10 described above. Accordingly, even if omitted below, the description of the sampling switch 10 may be equally applied to the description of FIG. 10 .

Referring to FIG. 10 , in step S11 , the main switch 130 is turned on by the positive power voltage V _DD charged in the first capacitor C ₁ to sample the input signal V _in . have.

Also, in step S12 , the negative voltage charging unit 120 may charge the negative power supply voltage -V _DD to the second capacitor C ₂ .

For reference, steps S11 and S12 may be processes performed in a state in which the sampling switch 10 is in a sample mode.

Next, in step S21 , the positive voltage charging unit 110 may charge the positive power voltage V _DD in the first capacitor C ₁ .

In addition, in step S22 , the main switch 130 may be turned off by the negative power voltage (-V _DD ) charged in the second capacitor C ₂ to hold the input signal.

For reference, steps S21 and S22 may be processes performed in a state in which the sampling switch 10 is in a hold mode.

In the above description, steps S11 to S22 may be further divided into additional steps or combined into fewer steps, according to an embodiment of the present application. In addition, some steps may be omitted if necessary, and the order between the steps may be changed.

The method of driving a sampling switch for a high dynamic input range according to an embodiment of the present application may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be specially designed and configured for the present invention, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic such as floppy disks. - includes magneto-optical media, and hardware devices specially configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

In addition, the above-described method of driving a sampling switch for a high dynamic input range may be implemented in the form of a computer program or application executed by a computer stored in a recording medium.

The foregoing description of the present application is for illustration, and those of ordinary skill in the art to which the present application pertains will understand that it can be easily modified into other specific forms without changing the technical spirit or essential features of the present application. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. For example, each component described as a single type may be implemented in a dispersed form, and likewise components described as distributed may be implemented in a combined form.

The scope of the present application is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present application.

10: Sampling switch for high dynamic input range
110: positive voltage charging unit
120: negative voltage charging unit
130: main switch

Claims (9)

A sampling switch for high dynamic input range, comprising:
a positive voltage charging unit including a first capacitor configured to charge a positive power voltage in a hold mode;
a negative voltage charging unit including a second capacitor configured to charge a negative power voltage in the sample mode; and
In the sample mode, it is turned on by the positive power voltage charged in the first capacitor to sample an input signal, and in the hold mode, it is turned off by the negative power voltage charged in the second capacitor. ) to hold the input signal, the main switch,
Including, sampling switch. According to claim 1,
A clock generator circuit that alternately switches to a High or Low state;
further comprising,
The sampling switch is driven in synchronization with the clock generation circuit,
wherein the sample mode corresponds to the low-state clock, and the hold mode corresponds to the high-state clock. 3. The method of claim 2,
The positive power supply voltage is V _DD , and the negative power supply voltage is -V _DD ,
The positive voltage charging unit,
A first PMOS transistor having a source connected to a V _DD /2 node corresponding to a voltage value corresponding to half of the positive power supply voltage, a drain connected to the top node of the first capacitor, and a gate connected to the gate of the main switch switch;
a second switch which is a PMOS transistor having a source connected to the top node of the first capacitor, a drain connected to a gate of the main switch, and a gate connected to the clock generating circuit;
A third NMOS transistor having a source connected to a -V _DD /2 node corresponding to a voltage value corresponding to half of the negative power supply voltage, a drain connected to the bottom node of the first capacitor, and a gate connected to the clock generation circuit switch; and
A fourth switch which is an NMOS transistor having a source connected to the bottom node of the first capacitor, a drain connected to an input node connected to the source of the main switch and to which the input signal is applied, and a gate connected to the gate of the main switch;
A sampling switch comprising a.. 4. The method of claim 3,
The negative voltage charging unit,
a fifth switch which is an NMOS transistor having a source connected to the top node of the second capacitor, a drain connected to a gate of the main switch, and a gate connected to the clock generation circuit;
a sixth switch that is an NMOS transistor having a source connected to a -V _DD /2 node, a drain connected to the top node of the second capacitor, and a gate connected to the gate of the main switch;
a seventh switch which is a PMOS transistor having a source connected to a bottom node of the second capacitor, a drain connected to an input node connected to a source of the main switch and to which the input signal is applied, and a gate connected to a gate of the main switch; and
an eighth switch which is a PMOS transistor having a source connected to a V _DD /2 node, a drain connected to the bottom node of the second capacitor, and a gate connected to the clock generation circuit;
A sampling switch comprising a. 5. The method of claim 4,
A first PMOS transistor comprising a source connected to the V _{DD /2 node between the V DD /} 2 node and the first switch, a drain connected to the source of the first switch, and a gate connected in a reverse direction to the clock generation circuit. 1 additional switch; and
An NMOS transistor comprising a source connected to the -V _{DD /2 node between the -V DD /} 2 node and the sixth switch, a drain connected to the source of the sixth switch, and a gate connected in a reverse direction to the clock generation circuit a second additional switch, which is
Which will further include, the sampling switch. 5. The method of claim 4,
a first clock generation circuit connected to the channel of the first switch to apply 2*V _DD in a high state and V _DD /2 in a low state; and
a second clock generation circuit connected to the channel of the sixth switch to apply -V _DD /2 in a high state and -2*V _DD in a low state;
Which will further include, the sampling switch. 5. The method of claim 4,
a channel of the first switch is connected to a top node of the first capacitor,
Sampling switch, characterized in that the channel of the sixth switch is connected to the top node of the second capacitor. A method of driving a sampling switch for a high dynamic input range, comprising:
The sampling switch is
A positive voltage charging unit including a first capacitor provided to charge a positive power supply voltage, a negative voltage charging unit including a second capacitor provided to charge a negative power supply voltage, and a main switch,
(a) In the sample mode, the negative voltage charging unit charges the negative power voltage to the second capacitor, and the main switch is turned on by the positive power voltage charged to the first capacitor to turn on an input signal sampling; and
(b) in the hold mode, the positive voltage charging unit charges the positive power voltage to the first capacitor, and the main switch is turned off by the negative power voltage charged in the second capacitor to turn off the input holding the signal,
Including, a driving method. An analog-to-digital converter comprising a sampling switch for high dynamic input range, comprising:
A sampling switch according to any one of claims 1 to 7;
a comparator for outputting a digital signal corresponding to the input signal sampled by the sampling switch;
Including, analog-to-digital converter.

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