KR102432550B1 - Method and System of manufacturing Wafer type Solar Cell - Google Patents

Abstract

The present invention provides a process for forming a concave-convex structure on the upper surface of the wafer by etching the upper surface of the wafer using a reaction gas; and removing impurities remaining in the concave-convex structure of the upper surface of the wafer, wherein the step of removing the impurities is a dry etching process.

Description

The manufacturing method and manufacturing system of a solar cell {Method and System of manufacturing Wafer type Solar Cell}

The present invention relates to a solar cell, and more particularly, to a wafer-type solar cell.

A solar cell is a device that converts light energy into electrical energy using the properties of semiconductors.

A solar cell has a PN junction structure in which a P (positive) type semiconductor and an N (negative) type semiconductor are bonded. When sunlight is incident on a solar cell having such a structure, holes and electrons are generated in the semiconductor by the incident solar energy. At this time, by the electric field generated in the PN junction, the holes (+) move toward the P-type semiconductor and the electrons (-) move toward the N-type semiconductor, thereby generating an electric potential, thereby producing power.

Such a solar cell can be divided into a thin film type solar cell and a wafer type solar cell.

The thin film solar cell is manufactured by forming a semiconductor in the form of a thin film on a substrate such as glass, and the wafer type solar cell is manufactured using a silicon wafer itself as a substrate.

The wafer-type solar cell has a disadvantage in that it is thicker than the thin-film solar cell and needs to use an expensive material, but has an advantage of excellent cell efficiency.

Hereinafter, a conventional wafer-type solar cell will be described with reference to the drawings.

1 is a cross-sectional view of a conventional wafer-type solar cell.

As can be seen from FIG. 1 , the conventional wafer-type solar cell has a P-type semiconductor layer 10 , an N-type semiconductor layer 20 , an anti-reflection layer 30 , a front electrode 40 , and a P ⁺ type semiconductor layer 50 . , and a rear electrode 60 .

The P-type semiconductor layer 10 and the N-type semiconductor layer 20 formed on the P-type semiconductor layer 10 form a PN junction structure of a solar cell.

The anti-reflection layer 30 is formed on the upper surface of the N-type semiconductor layer 20 to prevent reflection of incident sunlight.

The P ⁺ type semiconductor layer 50 is formed on the lower surface of the P-type semiconductor layer 10 to prevent carriers formed by sunlight from recombination and annihilation.

The front electrode 40 extends from an upper portion of the anti-reflection layer 30 to the N-type semiconductor layer 20 , and the rear electrode 60 is formed on a lower surface of the P ⁺ type semiconductor layer 50 . .

In such a conventional wafer-type solar cell, when sunlight is incident therein, electrons and holes are generated in the PN junction structure, and the generated electrons pass through the N-type semiconductor layer 20 to the front surface. The holes move to the electrode 40 , and the generated holes move to the rear electrode 60 through the P ⁺ type semiconductor layer 50 to generate power.

The conventional wafer-type solar cell described above is manufactured through the following process.

2A to 2G are cross-sectional views illustrating a manufacturing process of a conventional wafer-type solar cell.

First, as can be seen from FIG. 2A , a P-type wafer 10a is prepared.

Next, as shown in FIG. 2B , the upper surface of the P-type wafer 10a is etched to form a concave-convex structure on the upper surface of the wafer 10a.

The process of etching the top surface of the P-type wafer 10a may use a dry etching process, specifically, reactive ion etching (RIE). The reactive ion etching method is a process of etching an object using a predetermined reactive gas in a high-pressure plasma state.

When the top surface of the P-type wafer 10a is etched using the reactive ion etching method, a self mask 1 including a reactive gas material is generated on the top surface of the P-type wafer 10a.

The region in which the self mask 1 is generated is not etched, and the region in which the self mask 1 is not generated is etched to form a concave-convex structure on the upper surface of the wafer 10a as shown.

In this case, a portion of the self-mask 1 may remain on the upper surface of the P-type wafer 10a in a state in which the etching process is completed. As the etching process proceeds, the size of the self-mask 1 also gradually decreases, but at the time when the etching process is completed, a portion of the self-mask 1 is not removed and remains.

Next, as shown in FIG. 2C , the self-mask 1 remaining on the top surface of the P-type wafer 10a is removed.

The process of removing the self-mask 1 is performed using a wet etching process. That is, the self-mask 1 is removed using an etchant.

Next, as shown in FIG. 2D , a PN junction is formed by doping an N-type dopant on the upper surface of the P-type wafer 10a.

That is, when the upper surface of the P-type wafer 10a is doped with an N-type dopant, a region undoped by the dopant constitutes the P-type semiconductor layer 10 , and the region doped with the dopant is the N-type semiconductor layer. (20) is formed.

Next, as shown in FIG. 2E , an anti-reflection layer 30 is formed on the upper surface of the N-type semiconductor layer 20 .

Next, as can be seen in FIG. 2F , a front electrode material 40a is applied to the upper surface of the anti-reflection layer 30 , and a rear electrode material 60a is applied to the lower surface of the P-type semiconductor layer 10 .

Next, as can be seen from FIG. 2G , a wafer-type solar cell as shown in FIG. 1 is completed by performing a heat treatment at a high temperature.

When heat treatment is performed at a high temperature, the front electrode material 40a penetrates through the antireflection layer 30 and penetrates to the N-type semiconductor layer 20 to form the front electrode 40 .

In addition, when heat treatment is performed at a high temperature, the rear electrode material 60a penetrates into the lower surface of the P-type semiconductor layer 10 to form a P ⁺ type semiconductor layer 50 on the lower surface of the P-type semiconductor layer 10 . formed and a rear electrode 60 is formed thereunder.

Such a conventional wafer-type solar cell has the following disadvantages because the self-mask 1 is removed through the wet etching process in the process of FIG. 2C described above.

First, there is a disadvantage in that a wet etching equipment and a wet etching solution are additionally required to perform the wet etching process, thereby increasing the manufacturing cost.

In addition, since wastewater is generated after the wet etching process, an environmental pollution problem occurs, and a wastewater treatment facility is additionally required for wastewater treatment, thereby increasing the manufacturing cost.

The present invention is devised to solve the above disadvantages of the prior art, and the present invention can remove the self mask remaining on the upper surface of the wafer after etching the upper surface of the wafer using a reactive ion etching method through a dry etching process. An object of the present invention is to provide a manufacturing method and manufacturing system for a wafer-type solar cell.

In order to achieve the above object, the present invention includes a process of forming a concave-convex structure on the upper surface of the wafer by etching the upper surface of the wafer using a reaction gas; and removing impurities remaining in the concave-convex structure of the upper surface of the wafer, wherein the step of removing the impurities is a dry etching process.

The dry etching process may be an ashing process.

The ashing process may be performed using oxygen (O ₂ ) plasma.

The oxygen (O ₂ ) content may be in the range of 250 sccm to 400 sccm.

The ashing process may be performed in a pressure range of 20mTorr to 50mTorr and a temperature range of 50°C to 100°C.

The process of forming the concave-convex structure may be performed by forming at least one material constituting the reactive gas on the upper surface of the wafer as a self-mask.

The reaction gas may include a mixed gas of SF ₆ , Cl ₂ , and O ₂ .

The process of forming the concave-convex structure and the ashing process may be performed as a continuous process in the same dry etching equipment.

forming a first semiconductor layer undoped with the dopant and a second semiconductor layer doped with the dopant on an upper surface of the first semiconductor layer by doping the upper surface of the wafer with a dopant; forming an antireflection layer on an upper surface of the second semiconductor layer; forming a first electrode material on an upper surface of the anti-reflection layer and a second electrode material on a lower surface of the first semiconductor layer; and heat-treating the first electrode material and the second electrode material so that the first electrode material penetrates through the anti-reflection layer to the second semiconductor layer, and the second electrode material is applied to the first semiconductor layer. It may further include a process of penetrating into the lower surface.

The present invention also includes a reactive ion etching equipment for forming a concave-convex structure on the upper surface of the wafer by etching the upper surface of the wafer using a reactive gas; and an ashing processing device positioned at the rear of the reactive ion etching device to remove impurities remaining in the concave-convex structure of the upper surface of the wafer.

The reactive ion etching equipment and the ashing processing equipment may be arranged in an in-line structure.

The reactive ion etching equipment and the ashing processing equipment may be arranged in a cluster structure.

The reactive ion etching equipment and the ashing equipment may be formed of one and the same dry etching equipment.

Doping equipment, anti-reflective layer coating (ARC) equipment, printing (Printing) equipment, and heat treatment (Firing) equipment may be further included in the rear of the ashing equipment.

According to the present invention as described above, there are the following effects.

According to an embodiment of the present invention, since impurities remaining after forming the concave-convex structure on the upper surface of the wafer are removed by an ashing process without using a wet etching process, wet etching equipment and a wet etching solution are not required, and Since wastewater is not generated after the etching process, there is an advantage in that environmental pollution problems caused by wastewater and wastewater treatment facilities are not additionally required.

In addition, according to an embodiment of the present invention, the process of forming the concave-convex structure on the upper surface of the wafer and the process of removing impurities remaining on the upper surface of the concave-convex structure can be performed as a continuous process in one and the same dry etching equipment. . Therefore, the cost is reduced because a total of two equipment such as a dry etching equipment and a wet etching equipment are not required as in the prior art, and the process time can be shortened because there is no need to continuously move the dry etching equipment and the wet etching equipment. have.

1 is a cross-sectional view of a conventional wafer-type solar cell.
2A to 2G are cross-sectional views illustrating a manufacturing process of a conventional wafer-type solar cell.
3A to 3G are cross-sectional views illustrating a manufacturing process of a wafer-type solar cell according to an embodiment of the present invention.
4 is a schematic diagram illustrating a system for manufacturing a wafer-type solar cell according to an embodiment of the present invention.
5 is a schematic diagram illustrating a system for manufacturing a wafer-type solar cell according to another embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described as 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

3A to 3G are cross-sectional views illustrating a manufacturing process of a wafer-type solar cell according to an embodiment of the present invention.

First, as can be seen from FIG. 3A , a wafer 100a is prepared.

The wafer 100a may be a silicon wafer, for example, a P-type silicon wafer.

As the silicon wafer, single crystal silicon or polycrystalline silicon can be used. Single crystal silicon has high purity and low crystal defect density, so the efficiency of the solar cell is high, but the price is too high and thus economical efficiency is lowered, and polycrystalline silicon is relatively efficient It is suitable for mass production because the production cost is low because low-cost materials and processes are used.

Next, as shown in FIG. 3B , the upper surface of the wafer 100a is etched to form a concave-convex structure on the upper surface of the wafer 100a.

The process of etching the upper surface of the wafer 100a may use a dry etching process, specifically, reactive ion etching (RIE). The reactive ion etching method is a process of etching an object using a predetermined reactive gas in a high-pressure plasma state.

When the upper surface of the wafer 100a is etched using the reactive ion etching method, a self mask 101 including at least one material constituting a reactive gas is generated on the upper surface of the wafer 100a. .

The region in which the self mask 101 is generated is not etched, and the region in which the self mask 101 is not generated is etched to form a concave-convex structure on the upper surface of the wafer 100a as shown.

As described above, the process of etching the upper surface of the wafer 100a to form the concave-convex structure on the upper surface of the wafer 100a is performed using the self-mask 101 containing a reactive gas material without forming a separate mask. A material capable of forming the self-mask 101 is selected as a reaction gas for the etching process. Specifically, the reaction gas for etching the upper surface of the wafer 100a includes a mixed gas of SF ₆ , Cl ₂ , and O ₂ .

In this case, a portion of the self-mask 101 may remain as impurities on the upper surface of the wafer 100a in a state in which the etching process is completed. As the etching process proceeds, the size of the self-mask 101 also gradually decreases, but at the time when the etching process is completed, a portion of the self-mask 101 is not removed and remains.

Next, as shown in FIG. 3C , the self-mask 101 remaining on the upper surface of the concave-convex structure of the wafer 100a is removed.

The process of removing the self-mask 101 remaining on the upper surface of the concave-convex structure of the wafer 100a is performed using a dry etching process, in particular, an ashing process. More specifically, the ashing process may be performed using oxygen (O ₂ ) plasma.

The ashing process is generally used to etch a thin film made of an organic material. However, the present inventor has completed the present invention by confirming that the self-mask 101 can be removed through the ashing process even though it is made of an inorganic material rather than an organic material.

The processes of FIGS. 3B and 3C as described above may be performed as a continuous process while only changing process conditions such as the type of process gas and plasma treatment in one and the same dry etching equipment.

Therefore, the cost is reduced because a total of two equipment such as a dry etching equipment and a wet etching equipment are not required as in the prior art, and the process time can be shortened because there is no need to continuously move the dry etching equipment and the wet etching equipment. have.

In addition, since the present invention does not use a wet etching process as in the prior art, there is an advantage in that environmental pollution problems due to wastewater and wastewater treatment facilities are not additionally required.

The content of oxygen (O ₂ ) used in the ashing process is preferably in the range of 250 sccm to 400 sccm. When oxygen within the above range is used, the self-mask 101 may be more easily removed.

In addition, the ashing process may be preferably performed in a pressure range of 20mTorr to 50mTorr and a temperature range of 50°C to 100°C. The self-mask 101 may be more easily removed within the pressure range and temperature range.

Next, as shown in FIG. 3D , a PN junction layer including the first semiconductor layer 100 and the second semiconductor layer 200 is formed by doping the upper surface of the wafer 100a with a dopant.

When the upper surface of the wafer 100a is doped with a dopant, a region undoped by the dopant constitutes the first semiconductor layer 100 , and the region doped by the dopant constitutes the second semiconductor layer 200 . .

For example, when the wafer 100a is made of a P-type wafer, the first semiconductor layer 100 made of the P-type wafer and an N-type wafer on the upper surface of the first semiconductor layer 100 by doping with an N-type dopant The second semiconductor layer 200 made of may be formed.

The upper surface of the second semiconductor layer 200 has a concave-convex structure as in FIG. 3C described above. When the dopant is doped with the same thickness, the top surface of the first semiconductor layer 100 may also have the same uneven structure as the top surface of the second semiconductor layer 200 . However, the present invention is not limited thereto, and if the dopant is not doped with the same thickness, the upper surface of the first semiconductor layer 100 may have a different concave-convex structure from the upper surface of the second semiconductor layer 200 . have.

The process of doping the dopant may be performed using a high-temperature diffusion method or a plasma ion doping method.

In the process of doping the N-type dopant using the high-temperature diffusion method, POCl ₃ in a state in which the wafer 100a is placed in a high-temperature diffusion furnace of approximately 800° C. or higher. Alternatively, an N-type dopant gas such as PH ₃ may be supplied to diffuse the N-type dopant onto the surface of the wafer 100a.

In the process of doping the N-type dopant using the plasma ion doping method, POCl ₃ in a state in which the wafer 100a is placed in a plasma generator Alternatively, a process of generating plasma while supplying an N-type dopant gas such as PH ₃ may be performed. When the plasma is generated in this way, phosphorus (P) ions in the plasma are accelerated by the RF electric field and incident on the upper surface of the wafer 100a to be ion-doped.

Next, as shown in FIG. 3E , the anti-reflection layer 300 is formed on the upper surface of the second semiconductor layer 200 .

As the upper surface of the second semiconductor layer 200 has a concave-convex structure, the anti-reflection layer 300 is also formed with a similar concave-convex structure.

The anti-reflection layer 300 may be formed of silicon nitride or silicon oxide using plasma CVD.

Next, as shown in FIG. 3F , a first electrode material 400a is formed on the upper surface of the anti-reflection layer 300 , and a second electrode material 600a is formed on the lower surface of the first semiconductor layer 100 . .

The forming process of the first electrode material 400a and the second electrode material 600a is performed using Ag, Al, Ti, Mo, Ni, Cu, a mixture of two or more thereof, or an alloy paste of two or more thereof. It may be made by a printing process.

Since the first electrode material 400a is formed on the surface on which sunlight is incident, it is formed in a predetermined pattern without being formed on the entire upper surface of the anti-reflection layer 300 .

Since the second electrode material 600a is formed on a surface opposite to the surface on which sunlight is incident, it may be formed on the entire lower surface of the first semiconductor layer 100 . However, in some cases, in order to allow reflected sunlight to be incident into the solar cell, the second electrode material 600a may be formed in a predetermined pattern.

Next, as can be seen from FIG. 3G , a solar cell according to an embodiment of the present invention is manufactured by performing a heat treatment at a high temperature.

When heat treatment is performed at a high temperature, the first electrode material 400a penetrates through the anti-reflection layer 300 and penetrates to the second semiconductor layer 200 , so that the first electrode material 400a is in contact with the second semiconductor layer 200 . The electrode 400 may be formed.

In addition, when heat treatment is performed at a high temperature, the second electrode material 600a penetrates into the lower surface of the first semiconductor layer 100 , so that the first semiconductor layer 100 has a dopant concentration higher than that of the first semiconductor layer 100 . A third semiconductor layer 500 is formed on a lower surface of the first semiconductor layer 100 , and a second electrode 600 is formed on a lower surface of the third semiconductor layer 500 .

For example, when the first semiconductor layer 100 is formed of a P-type semiconductor, the third semiconductor layer 500 is formed of a P ⁺ type semiconductor layer.

The above has been described with respect to a method of doping a P-type wafer with an N-type dopant to form a PN junction structure and then proceeding with a subsequent process, but the present invention is not necessarily limited thereto. A method of performing a subsequent process after forming the PN junction structure is also included.

A manufacturing system for implementing the manufacturing process of a wafer-type solar cell according to an embodiment of the present invention will be described as follows.

4 and 5 are views illustrating a manufacturing system for a wafer-type solar cell according to various embodiments of the present invention, each of which is a manufacturing system for implementing the manufacturing process according to FIGS. 3B to 3G described above.

4 is a schematic diagram illustrating a system for manufacturing a wafer-type solar cell according to an embodiment of the present invention.

As can be seen in Figure 4, the manufacturing system of the wafer-type solar cell according to an embodiment of the present invention, reactive ion etching equipment (RIE), ashing equipment (Ashing), doping (Doping) equipment, anti-reflection layer coating (ARC) ) equipment, printing equipment, and heating equipment.

The reactive ion etching equipment (RIE) is an equipment for performing the above-described process of FIG. 3B , that is, the process (Texuring) of etching the upper surface of the wafer 100a to form a concave-convex structure. The reactive ion etching (RIE) equipment may use a variety of equipment known in the art capable of forming a concave-convex structure on a wafer using a reactive gas.

The ashing equipment (Ashing) is located behind the reactive ion etching equipment (RIE). In the present specification, the fact that a certain equipment is located behind another equipment means that the process in the certain equipment is performed first and then the subsequent process is made in the other equipment.

The ashing processing equipment (Ashing) is equipment for performing the above-described process of FIG. 3C , that is, a process of removing the self mask 101 remaining on the upper surface of the wafer 100a. The ashing treatment equipment (Ashing) may use a variety of equipment known in the art using oxygen (O ₂ ) plasma.

The doping equipment is located behind the ashing equipment (Ashing). The doping equipment is equipment for performing the process of FIG. 3D , that is, the dopant doping process. Such doping equipment may use equipment known in the art capable of doping by supplying a dopant gas in a plasma atmosphere, or equipment known in the art capable of doping by supplying a dopant gas to a high temperature diffusion furnace. can also be used.

The anti-reflective layer coating (ARC) equipment is located behind the doping equipment. The anti-reflection layer coating (ARC) equipment is the process of FIG. 3E described above, that is, equipment for coating the anti-reflection layer. Such anti-reflection layer coating (ARC) equipment may use PECVD equipment known in the art.

The printing equipment is located behind the anti-reflection layer coating (ARC) equipment. The printing equipment is an equipment for printing the above-described process of FIG. 3f , that is, an electrode material, and various printing equipment known in the art, such as screen printing equipment, may be used.

The heat treatment (Firing) equipment is located in the rear of the printing (Printing) equipment. The heat treatment (Firing) equipment is equipment for performing the process of FIG. 3G described above, and various heat treatment equipment known in the art may be used.

Although FIG. 4 shows that the reactive ion etching equipment (RIE) and the ashing equipment (Ashing) are provided as separate process equipment, in some cases, the reactive ion etching equipment (RIE) and the ashing equipment (Ashing) are one The same dry etching equipment may be used. In this case, by changing only the process conditions such as the type of process gas and plasma treatment, the process of forming the uneven structure (Texuring) and the process of removing the self mask 101 are continuously performed in one and the same dry etching equipment. It is also possible

5 is a schematic diagram illustrating a system for manufacturing a wafer-type solar cell according to another embodiment of the present invention.

5 is the same as FIG. 4 described above, except that the reactive ion etching equipment (RIE) and the ashing processing equipment (Ashing) have a cluster structure.

That is, according to the manufacturing system according to FIG. 4 described above, the reactive ion etching equipment (RIE), the ashing equipment (Ashing), the doping equipment, the anti-reflection layer coating (ARC) equipment, and the printing (Printing) equipment ) equipment and the heating equipment are arranged in a line in order, so that each process can be made as a continuous process.

In contrast, according to the manufacturing system according to FIG. 5 , the reactive ion etching equipment (RIE) and the ashing equipment (Ashing) are configured in a cluster structure, and the remaining doping equipment and the anti-reflection layer coating (ARC) Equipment, the printing (Printing) equipment, and the heat treatment (Firing) equipment is configured in an in-line structure arranged in a line in order, each process can be made as a continuous process.

In the cluster structure, the ashing processing equipment (Ashing) is located behind the reactive ion etching equipment (RIE). In addition, the cluster structure is connected to the load lock chamber (LRC).

Meanwhile, although not shown, when the doping equipment is configured of equipment capable of doping by supplying a dopant gas in a plasma atmosphere, the doping equipment may also be included in the cluster structure. In this case, the doping equipment is located behind the ashing equipment. In addition, when the doping equipment is included in the cluster structure, the anti-reflection layer coating (ARC) equipment may also be included in the cluster structure. In this case, the anti-reflection layer coating (ARC) equipment is located behind the doping equipment.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to illustrate, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

101: self mask 100a: wafer
100: first semiconductor layer 200: second semiconductor layer
300: anti-reflection layer 400a, 400: first electrode material, first electrode
500: a third semiconductor layer 600a, 600: a second electrode material, a second electrode

Claims (14)

SF ₆ , Cl ₂ , and O ₂ forming a concave-convex structure on the upper surface of the wafer by etching the upper surface of the wafer using a reaction gas containing a mixed gas; and
and removing impurities made of inorganic materials including at least one material constituting the reaction gas remaining in the concave-convex structure of the upper surface of the wafer,
The process of removing the impurities made of the inorganic material is made of a dry etching process,
The dry etching process is a method of manufacturing a solar cell comprising an ashing process performed using oxygen (O ₂ ) plasma. delete delete The method of claim 1,
The oxygen (O ₂ ) content is in the range of 250 sccm to 400 sccm. delete The method of claim 1,
The process of forming the concave-convex structure and the dry etching process are performed as a continuous process in the same dry etching equipment. Reactive ion etching equipment for forming an uneven structure on the upper surface of the wafer by etching the upper surface of the wafer using a reaction gas containing a mixed gas of SF ₆ , Cl ₂ , and O ₂ ;
It is located at the rear of the reactive ion etching equipment and uses oxygen (O ₂ ) plasma to remove impurities made of inorganic materials including at least one material constituting the reactive gas remaining in the uneven structure of the upper surface of the wafer. ashing processing equipment to perform; and
The solar cell manufacturing system is located at the rear of the ashing processing equipment and comprises a doping equipment for doping a dopant on the upper surface of the wafer. 8. The method of claim 7,
The reactive ion etching equipment and the ashing processing equipment are a solar cell manufacturing system consisting of one and the same dry etching equipment. delete delete delete delete delete delete

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