KR102425395B1 - Layout of semiconductor device - Google Patents

Abstract

The arrangement structure of a semiconductor memory device according to an embodiment of the present application includes a first region including a plurality of transistors, a second region including a plurality of transistors and disposed adjacent to the first region in a first direction; and a third region disposed adjacent to the first region and the second region in the second direction and including a plurality of transistors connected in a three-stage series structure.

Description

Layout structure of semiconductor memory device {LAYOUT OF SEMICONDUCTOR DEVICE}

Various embodiments of the present invention relate to an arrangement structure of a semiconductor memory device.

In general, a semiconductor device includes drivers for driving various signals therein. For example, in the case of a semiconductor memory device, various signals are internally driven to select a specific memory cell to store or read data. For this purpose, a plurality of drivers must be arranged in a limited space as efficiently as possible.

In general, various drivers are integrated in a peripheral circuit region disposed around the memory cell region. When integrating various drivers using the same power in the peripheral circuit area, it is important to efficiently arrange the drivers in a limited space.

Various embodiments of the present invention are directed to providing an arrangement structure of a semiconductor memory device capable of improving area efficiency of an active region and metal wiring formed in a peripheral circuit region of the semiconductor memory device.

In order to achieve the above object, an arrangement structure of a semiconductor memory device according to an embodiment of the present application includes a first region including a plurality of transistors, a plurality of transistors, and adjacent to the first region in a first direction. It is characterized in that it includes a second region arranged in the above position, and a third region disposed adjacent to the first region and the second region in the second direction and including a plurality of transistors connected in a three-stage series structure.

Further, the first region and the second region are characterized in that each is a PMOS region or an NMOS region.

Furthermore, the third region is characterized as a sub word line driver region.

Furthermore, it is characterized in that the first direction and the second direction are perpendicularly intersecting directions.

Furthermore, the transistors in the first region are arranged in a two-stage structure, and the transistors in the second region are arranged in a one-stage structure.

Further, the first region and the second region include a first unit, a second unit, a third unit, and a fourth unit, the first unit and the second unit are symmetrical, the third unit and the fourth unit It is characterized in that it has a symmetrical structure.

Furthermore, the first to fourth units each include three transistors positioned in the first region and three transistors positioned in the second region, wherein the three transistors positioned in the first region are in the first stage. Two transistors are positioned, and it is characterized in that it is arranged in a two-stage structure in which one transistor is positioned in a second stage.

Furthermore, the three transistors located in the second region are arranged side by side in the second direction.

Furthermore, it is characterized in that it includes a first transistor region including one transistor, a second transistor region including four transistors, and a third transistor region including five transistors.

Further, the first transistor region, the second transistor region, and the third transistor region are characterized in that they are disposed adjacent to each other in the first direction.

Furthermore, the first transistor region is composed of one active region and a plurality of gate electrodes passing through the active region, and includes one transistor.

Further, the second transistor region includes a plurality of active regions and a plurality of gate electrodes passing through the active regions, and includes first to fourth transistors, and the third transistor region includes a plurality of active regions and a plurality of gate electrodes passing through the active regions. It is composed of a gate electrode of , characterized in that it includes first to fifth transistors.

In addition, the first to fourth transistors of the second transistor region are respectively connected in series with the first to fourth transistors of the third transistor region through a bit line, and the transistors of the first transistor region are The first to fourth transistors in the second transistor region and the fifth transistor in the third transistor region are connected in series through a bit line.

The first transistor of the second transistor region is connected to the fourth unit through the first node of the metal wiring M1, and the second transistor of the second transistor region is connected to the third unit through the second node of the metal wiring M1. connected to the unit.

In addition, the third transistor of the second transistor region is connected to the second unit through the third node of the metal wiring M1, and the fourth transistor of the second transistor region is connected to the second unit through the fourth node of the metal wiring M1. It is characterized in that it is connected to one unit.

According to various embodiments of the present invention, the following effects can be obtained by rearranging the sub word line driver region.

First, according to the present invention, the area of the active region can be reduced by disposing the sub word line driver region including a plurality of transistors connected in a three-stage series structure on the side of the main region.

Second, according to the present invention, as the sub word line driver region is disposed on the side of the main region, metal wiring required to connect the main region and the sub word line driver region can be minimized.

In addition, the embodiments of the present invention are for illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the technical spirit and scope of the appended claims, and such modifications and changes fall within the scope of the following claims. should be seen as

1 is a layout diagram illustrating an arrangement structure of a semiconductor memory device according to an exemplary embodiment of the present invention.
2 is a circuit diagram corresponding to an arrangement structure of a semiconductor memory device according to an embodiment of the present invention.
3A to 3C are layout views illustrating an arrangement structure of a semiconductor memory device according to an exemplary embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to the components of each drawing, it should be noted that the same components are given the same reference numerals as much as possible even though they are indicated on different drawings. In addition, in describing an embodiment of the present application, if it is determined that a detailed description of a related known configuration or function interferes with the understanding of the embodiment of the present application, the detailed description thereof will be omitted.

1 is a layout diagram illustrating an arrangement structure of a semiconductor memory device according to an exemplary embodiment of the present invention.

The peripheral circuit region of the semiconductor memory device includes various devices required for an access operation of the memory cell of the semiconductor memory device, such as transistors in the PMOS region, transistors in the NMOS region, and metal wires.

A peripheral circuit region of a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIG. 1 .

The peripheral circuit region of the semiconductor memory device includes a PMOS region (A), an NMOS region (B), and a sub word line driver region (C).

The PMOS region A and the NMOS region B are arranged in a line along the first direction (Y-axis).

In addition, the sub word line driver region C is disposed adjacent to one side of the PMOS region A and the NMOS region B, that is, along the second direction (X-axis). The sub word line driver region C may be an NMOS region.

Each of the PMOS region A and the NMOS region B includes a plurality of active regions 10 and 50 , and a plurality of gate electrodes 20 and 60 are disposed on the active regions 10 and 50 . The PMOS region A and the NMOS region B include a plurality of transistors P1 , P2 , P3 , N1 , N2 , N3 , etc. configured with active regions 10 and 50 and gate electrodes 20 and 60 .

In this example, the peripheral circuit region is composed of a plurality of unit units, and the unit unit includes some transistors in the PMOS region (A) and some transistors in the NMOS region (B). Here, the plurality of unit units have a structure in which adjacent unit units are symmetrical.

For example, one unit may include three PMOS region (A) transistors (P1, P2, P3) and three NMOS region (B) transistors (N1, N2, N3). The peripheral circuit area may have a structure in which a plurality of unit units are repeatedly arranged in the second direction.

In addition, the first unit (Unit1) and the second unit (Unit2), the third unit (Unit3) and the fourth unit (Unit4) have a structure symmetrical to each other. Herein, the description is divided into four unit units, but the present invention is not limited thereto.

The configuration of the unit unit will be described in more detail as follows.

First, the transistor arrangement structure of the PMOS region A will be described. A transistor P1 is disposed at a first stage, and two transistors P2 and P3 are disposed at a second stage adjacent to the transistor P1 in the first direction. can be placed side by side. That is, the transistors in the PMOS region may be arranged in a two-stage structure.

Meanwhile, in the NMOS region B, the three transistors N1 , N2 , and N3 may be arranged side by side in the second direction. That is, the transistors in the NMOS region may be arranged in a single-stage structure.

The transistors configured as one unit share a source power line, and thus the area of the active region may be minimized.

In addition, a sub word line driver region C is provided on one side of the PMOS region A and the NMOS region B. In the sub word line driver region C, a plurality of transistors are arranged in a three-stage series structure.

For example, one first active region 100 is provided at the first end. A plurality of gate electrodes 110 are disposed on the first active region 100 , and the plurality of gate electrodes 110 are connected to one another to form one transistor N4 .

In addition, a plurality of second active regions 200 are provided at the second end, which is the upper end of the first active region 100 . A plurality of gate electrodes 210 are disposed on the second active region 200 , and the plurality of gate electrodes 210 are connected two by two to form a total of four transistors N5-1, N5-2, N5-3, and N5. -4) is formed.

In addition, a plurality of third active regions 300 are provided at the third end, which is the upper end of the second active region 200 . A plurality of gate electrodes 310 are disposed on the third active region 300 , and a total of five transistors N6-1, N6-2, N6-3, N6-4, and N6-5 are formed.

A bit line 400 for connecting transistors disposed at different stages is disposed in the sub word line driver region C. As shown in FIG. The bit line 400 is generally formed together with the formation of the bit line 400 for the cell array region of the semiconductor memory device.

The bit line 400 may be elongated in a direction in which the gate electrode is extended.

The bit line 400 is connected to the transistors N5-1, N5-2, N5-3, and N5-4 of the second stage and the transistors N6-1 and N6 of the third stage through the contact 410 formed on the transistor. -2, N6-3, N6-4).

The transistors N5-1, N5-2, N5-3, N5-4, and N6-5 of the sub word line driver region C are arranged in a series structure, and the transistors arranged in the series structure are arranged in the bit line 400 . connected through In addition, transistors arranged in a series structure are connected through the bit line 400 at the drain terminal of the transistor N4 .

As described above, in the sub word line driver region C, transistors to which the NMOS control signal is applied are arranged in a three-stage series structure, and as each transistor is connected to the bit line 400, there is a delay caused by the RC component of the transistor. ) was minimized.

And, a metal line connecting the transistors N5-1, N5-2, N5-3, and N5-4 of the sub word line driver region C and unit units of the PMOS region A and the NMOS region B, respectively. (M1, 420a, 420b, 420c, 420d) is arranged. The metal wiring M1 is disposed to extend along a direction crossing the gate electrodes 110 , 210 , and 310 and the bit line 400 , that is, in the second direction (X-axis).

The first node 400a of the metal wiring M1 is connected to the fourth unit Unit4 through the contact 430 formed on the transistor N5 - 1 . The second node 400b of the metal wire M1 is connected to the third unit Unit 3 through the contact 430 formed on the transistor N5 - 2 .

Also, the third node 400c of the metal wire M1 is connected to the second unit Unit 2 through the contact 430 formed on the transistor N5 - 3 . The fourth node 400d of the metal wiring M1 is connected to the first unit Unit 1 through the contact 430 formed on the transistor N5 - 4 .

As described above, as the transistors of the sub word line driver region C and the unit units including the PMOS region A and the NMOS region B are connected through the metal wiring M1, the conventional method used to connect them It became possible to omit the metal wiring M2. Accordingly, the metal wiring to be formed in the peripheral circuit region of the semiconductor memory device is minimized.

FIG. 2 is a circuit diagram corresponding to the arrangement structure of the semiconductor memory device shown in FIG. 1 . Referring to FIG. 2 , the connection relationship between the sub word line driver region C, the PMOS region A, and the NMOS region B, and the connection relationship of the transistors disposed in the sub word line driver region C will be briefly described. If you do:

First, the sub word line driver region (C) includes transistors N4, N5, and N6 arranged in a three-stage series structure.

The first transistor N4 operates by receiving the upper address signal BAX1<1>, and the drain terminal of the first transistor N4 is connected to the second transistor N5-1 through the bit line BL. N5-2, N5-3, N5-4) and the third transistor N6-5 are vertically connected in series.

The second transistors N5-1, N5-2, N5-3, and N5-4 receive the lower address signal BAX23<0:3>, and the first transistor N4 and the third transistor N6-1 , N6-2, N6-3, N6-4).

The third transistors N6-1, N6-2, N6-3, N6-4, and N6-5 receive the selection signal FX and selectively drive to the high voltage VPP.

In addition, the PMOS region and the NMOS region each include a plurality of transistors. The PMOS region and the NMOS region may be divided into a plurality of units. Each unit unit may include some transistors P1 , P2 , and P3 in the PMOS region and some transistors N1 , N2 , and N3 in the NMOS region.

The transistors P1 , P2 , P3 , N1 , N2 , and N3 of the first unit are adjacent to each other through the node 4 Node4 of the metal line M1 and the second transistor N5 of the sub word line driver region is disposed. -1) is connected.

The transistors P1 , P2 , P3 , N1 , N2 , and N3 of the second unit are adjacent to each other through the node 3 Node3 of the metal line M1 and the second transistor N5 of the sub word line driver region. -2) is connected.

The transistors P1 , P2 , P3 , N1 , N2 , and N3 of the third unit are adjacent to each other through the node 2 Node2 of the metal line M1 and the second transistor N5 of the sub word line driver region. -3) is connected.

The transistors P1 , P2 , P3 , N1 , N2 , and N3 of the fourth unit are adjacent to each other through the node 1 Node1 of the metal wiring M1 and the second transistor N5 of the sub word line driver region. -4) is connected.

When the transistors P1, P2, and P3 in the PMOS region enter the active mode, they are driven at the high voltage VPP according to the selection signal FX.

On the other hand, when the transistors N1 , N2 , and N3 of the NMOS region enter the precharge mode, they are driven at the low voltage VBBW according to the inversion selection signal FXB<0:3>.

3A to 3C are diagrams illustrating an arrangement structure of a semiconductor memory device according to an order of formation of a gate electrode, a bit line, and a metal wiring according to an exemplary embodiment of the present invention. FIG. 3B is a view in which a bit line is added to FIG. 3A, and FIG. 3C is a view in which a metal wire is added to FIG. 3B. This is to more clearly explain the positional relationship between the gate electrode, the bit line, and the metal wire, so it must be a drawing It is not necessary to form them in the order shown.

First, referring to FIG. 3A , the PMOS region A and the NMOS region B are arranged in a line along the first direction (Y-axis).

In addition, the sub word line driver region C is disposed adjacent to one side of the PMOS region A and the NMOS region B, that is, along the second direction (X-axis). The sub word line driver region C may be an NMOS region.

Each of the PMOS region A and the NMOS region B includes a plurality of active regions 10 and 50 , and a plurality of gate electrodes 20 and 60 are disposed on the active regions 10 and 50 . The PMOS region A and the NMOS region B include a plurality of transistors P1 , P2 , P3 , N1 , N2 , N3 , etc. configured with active regions 10 and 50 and gate electrodes 20 and 60 .

In this example, the peripheral circuit region is composed of a plurality of unit units, and the unit unit includes some transistors in the PMOS region (A) and some transistors in the NMOS region (B). Here, the plurality of unit units have a structure in which adjacent unit units are symmetrical.

For example, one unit may include three PMOS region (A) transistors (P1, P2, P3) and three NMOS region (B) transistors (N1, N2, N3). The peripheral circuit area may have a structure in which a plurality of unit units are repeatedly arranged in the second direction.

In addition, the first unit (Unit1) and the second unit (Unit2), the third unit (Unit3) and the fourth unit (Unit4) have a structure symmetrical to each other. Herein, the description is divided into four unit units, but the present invention is not limited thereto.

The configuration of the unit unit will be described in more detail as follows.

First, the transistor arrangement structure of the PMOS region A will be described. A transistor P1 is disposed at a first stage, and two transistors P2 and P3 are disposed at a second stage adjacent to the transistor P1 in the first direction. can be placed side by side. That is, the transistors in the PMOS region may be arranged in a two-stage structure.

Meanwhile, in the NMOS region B, the three transistors N1 , N2 , and N3 may be arranged side by side in the second direction. That is, the transistors in the NMOS region may be arranged in a single-stage structure.

The transistors configured as one unit share a source power line, and thus the area of the active region may be minimized.

In addition, a sub word line driver region C is provided on one side of the PMOS region A and the NMOS region B. In the sub word line driver region C, a plurality of transistors are arranged in a three-stage series structure.

For example, one first active region 100 is provided at the first end. A plurality of gate electrodes 110 are disposed on the first active region 100 , and the plurality of gate electrodes 110 are connected to one another to form one transistor N4 .

In addition, a plurality of second active regions 200 are provided at the second end, which is the upper end of the first active region 100 . A plurality of gate electrodes 210 are disposed on the second active region 200 , and the plurality of gate electrodes 210 are connected two by two to form a total of four transistors N5-1, N5-2, N5-3, and N5. -4) is formed.

In addition, a plurality of third active regions 300 are provided at the third end, which is the upper end of the second active region 200 . A plurality of gate electrodes 310 are disposed on the third active region 300 , and a total of five transistors N6-1, N6-2, N6-3, N6-4, and N6-5 are formed.

Next, referring to FIG. 3B , in the sub word line driver region C, a bit line 400 for connecting transistors disposed at different stages is disposed. The bit line 400 is generally formed together with the formation of the bit line 400 for the cell array region of the semiconductor memory device.

The bit line 400 may be elongated in a direction in which the gate electrode is extended.

The bit line 400 is connected to the transistors N5-1, N5-2, N5-3, and N5-4 of the second stage and the transistors N6-1 and N6 of the third stage through the contact 410 formed on the transistor. -2, N6-3, N6-4).

The transistors N5-1, N5-2, N5-3, N5-4, and N6-5 of the sub word line driver region C are arranged in a series structure, and the transistors arranged in the series structure are arranged in the bit line 400 . connected through In addition, transistors arranged in a series structure are connected through the bit line 400 at the drain terminal of the transistor N4 .

As described above, in the sub word line driver region C, transistors to which the NMOS control signal is applied are arranged in a three-stage series structure, and as each transistor is connected to the bit line 400, there is a delay caused by the RC component of the transistor. ) was minimized.

Referring to FIG. 3C , the transistors N5-1, N5-2, N5-3, and N5-4 of the sub word line driver region C and unit units of the PMOS region A and the NMOS region B are respectively formed. Connecting metal wires M1, 420a, 420b, 420c, and 420d are disposed. The metal wiring M1 is disposed to extend along a direction crossing the gate electrodes 110 , 210 , and 310 and the bit line 400 , that is, in the second direction (X-axis).

The first node 400a of the metal wiring M1 is connected to the fourth unit Unit4 through the contact 430 formed on the transistor N5 - 1 . The second node 400b of the metal wire M1 is connected to the third unit Unit 3 through the contact 430 formed on the transistor N5 - 2 .

Also, the third node 400c of the metal wire M1 is connected to the second unit Unit 2 through the contact 430 formed on the transistor N5 - 3 . The fourth node 400d of the metal wiring M1 is connected to the first unit Unit 1 through the contact 430 formed on the transistor N5 - 4 .

As described above, as the transistors of the sub word line driver region C and the unit units including the PMOS region A and the NMOS region B are connected through the metal wiring M1, the conventional method used to connect them It became possible to omit the metal wiring M2. Accordingly, the metal wiring to be formed in the peripheral circuit region of the semiconductor memory device is minimized.

The above description is merely illustrative of the technical idea of the present application, and various modifications and variations will be possible without departing from the essential characteristics of the present application by those of ordinary skill in the art to which the present application belongs.

Accordingly, the embodiments disclosed in the present application are for explanation rather than limiting the technical spirit of the present application, and the scope of the technical spirit of the present application is not limited by these embodiments.

The protection scope of the present application should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

10, 50: active region 13, 60: gate electrode
100: first active region 110, 210, 310: gate electrode
200: second active region 300: third active region
400: bit line 410, 430: contact
420a: first node of metal wiring 420b: second node of metal wiring
420c: third node of metal wiring 420d: fourth node of metal wiring

Claims (18)

a first region comprising a plurality of transistors;
a second region including a plurality of transistors and disposed adjacent to the first region in a first direction; and
and a third region disposed adjacent to the first region and the second region in a second direction and including a plurality of transistors connected in a three-stage series structure;
The arrangement structure of a semiconductor memory device, wherein the transistors in the first region and the transistors in the second region are configured as one unit, and the transistors configured as one unit share a source power line. ◈Claim 2 was abandoned when paying the registration fee.◈ The method according to claim 1,
The arrangement structure of the semiconductor memory device, characterized in that the first region and the second region are a PMOS region or an NMOS region, respectively. ◈Claim 3 was abandoned when paying the registration fee.◈ The method according to claim 1,
and the third region is a sub word line driver region. ◈Claim 4 was abandoned when paying the registration fee.◈ The method according to claim 1,
The arrangement structure of the semiconductor memory device, wherein the first direction and the second direction are perpendicular to each other. ◈Claim 5 was abandoned when paying the registration fee.◈ The method according to claim 1,
The arrangement structure of the semiconductor memory device, wherein the transistors in the first region are arranged in a two-stage structure. ◈Claim 6 was abandoned when paying the registration fee.◈ The method according to claim 1,
The arrangement structure of the semiconductor memory device, wherein the transistors in the second region are arranged in a single-stage structure. ◈Claim 7 was abandoned when paying the registration fee.◈ The method according to claim 1,
The first region and the second region include a first unit, a second unit, a third unit and a fourth unit, wherein the first unit and the second unit are symmetrical, and the third unit and the The arrangement structure of the semiconductor memory device, characterized in that the fourth unit has a symmetrical structure. ◈Claim 8 was abandoned when paying the registration fee.◈ 8. The method of claim 7,
The third area is
a first transistor region comprising one transistor;
a second transistor region comprising four transistors; and
An arrangement structure of a semiconductor memory device comprising a third transistor region including five transistors. ◈Claim 9 was abandoned at the time of payment of the registration fee.◈ 9. The method of claim 8,
The arrangement structure of the semiconductor memory device, wherein the first transistor region, the second transistor region, and the third transistor region are disposed adjacent to each other in the first direction. ◈Claim 10 was abandoned when paying the registration fee.◈ 9. The method of claim 8,
The first transistor region is
one first active region; and
and a plurality of gate electrodes passing through the first active region and including one transistor. ◈Claim 11 was abandoned when paying the registration fee.◈ 9. The method of claim 8,
The second transistor region is
a plurality of second active regions; and
and a plurality of gate electrodes passing through the second active region and including first to fourth transistors. ◈Claim 12 was abandoned when paying the registration fee.◈ 9. The method of claim 8,
The third transistor region is
a plurality of third active regions;
and a plurality of gate electrodes passing through the third active region and including first to fifth transistors. ◈Claim 13 was abandoned when paying the registration fee.◈ 9. The method of claim 8,
The arrangement structure of the semiconductor memory device, wherein the first to fourth transistors of the second transistor region are connected in series with the first to fourth transistors of the third transistor region through a bit line, respectively. ◈Claim 14 was abandoned when paying the registration fee.◈ 9. The method of claim 8,
The transistor of the first transistor region is connected in series with the first to fourth transistors of the second transistor region and the fifth transistor of the third transistor region through a bit line. . ◈Claim 15 was abandoned when paying the registration fee.◈ 12. The method of claim 11,
and the first transistor of the second transistor region is connected to the fourth unit through a first node of a metal wiring (M1). ◈Claim 16 has been abandoned at the time of payment of the registration fee.◈ 12. The method of claim 11,
and the second transistor of the second transistor region is connected to the third unit through a second node of a metal wiring (M1). ◈Claim 17 was abandoned when paying the registration fee.◈ 12. The method of claim 11,
and the third transistor of the second transistor region is connected to the second unit through a third node of a metal wiring (M1). ◈Claim 18 was abandoned when paying the registration fee.◈ 12. The method of claim 11,
and the fourth transistor of the second transistor region is connected to the first unit through a fourth node of a metal wiring (M1).

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