JP7417293B2 - Logic integrated circuit and control method using logic integrated circuit - Google Patents

Description

The present invention relates to a logic integrated circuit and a control method using the logic integrated circuit.

Programmable logic integrated circuits such as FPGAs (Field Programmable Gate Arrays) are used in various fields.
Patent Document 1 discloses a technology related to a rewritable logic circuit as a related technology.

Japanese Patent Application Publication No. 2017-033616

Incidentally, in programmable logic integrated circuits, there is a need for a technology that can arrange a large number of wiring lines while keeping the chip area small.

Each aspect of the present invention aims to provide a logic integrated circuit and a control method using the logic integrated circuit that can solve the above problems.

In order to achieve the above object, according to one aspect of the present invention, a logic integrated circuit includes a switch cell array including a resistance change element, read/write control wiring for the resistance change element, a logic element, and a first circuit. , a second circuit, the read/write control wiring is connected to a first terminal of the first circuit and a first terminal of the second circuit, and the switch cell array is connected to the first terminal of the first circuit. 2 terminals, the logic element is connected to a second terminal of the second circuit, and in a first mode, the first circuit transmits a signal between the read/write control wiring and the switch cell array. The second circuit does not transmit a signal between the read/write control wiring and the logic element, and in the second mode, the first circuit transmits a signal between the read/write control wiring and the switch cell array. The second circuit transmits a signal between the read/write control wiring and the logic element.

In order to achieve the above object, according to another aspect of the present invention, a control method using a logic integrated circuit includes a switch cell array including a resistance change element, read/write control wiring for the resistance change element, a logic element, a first circuit and a second circuit, the read/write control wiring is connected to a first terminal of the first circuit and a first terminal of the second circuit, and the switch cell array is connected to the first circuit. A control method using a logic integrated circuit connected to a second terminal of one circuit, wherein the logic element is connected to a second terminal of the second circuit, wherein in a first mode, the lead is controlled by the first circuit. transmitting a signal between the write control wiring and the switch cell array; and not transmitting a signal between the read/write control wiring and the logic element by the second circuit in the first mode; In the second mode, the first circuit does not transmit a signal between the read/write control wiring and the switch cell array; and in the second mode, the second circuit causes the read/write control wiring to communicate with the switch cell array. This includes transmitting signals to and from the logic element.

According to each aspect of the present invention, it is possible to arrange many wiring lines while keeping the chip area of the programmable logic integrated circuit small.

FIG. 1 is a diagram showing the configuration of a programmable logic integrated circuit according to a first embodiment of the present invention. FIG. 3 is a diagram showing the configuration of a programmable logic integrated circuit according to a second embodiment of the present invention. FIG. 3 is a diagram showing the configuration of a programmable logic core according to a second embodiment of the present invention. FIG. 7 is a diagram showing the configuration of a logic cell according to a second embodiment of the present invention. FIG. 7 is a diagram illustrating an example of a memory device according to a second embodiment of the present invention. FIG. 7 is a diagram showing an example of a three-terminal resistance change switch according to a second embodiment of the present invention. It is a figure which shows another example of the 3-terminal resistance change switch by the 2nd Embodiment of this invention. FIG. 7 is a diagram showing the configuration of a programmable logic core according to a third embodiment of the present invention. 1 is a diagram showing the configuration of a programmable logic core using technology related to the present invention. 1 is a diagram showing the configuration of a logic cell using technology related to the present invention. 1 is a diagram showing a programmable logic integrated circuit with a minimum configuration according to an embodiment of the present invention; FIG. FIG. 1 is a schematic block diagram showing the configuration of a computer according to at least one embodiment.

Embodiments of the present invention will be described in detail below with reference to the drawings. Note that although the embodiments described below include technically preferable limitations for implementing the present invention, the scope of the invention is not limited to the following.

<First embodiment>
FIG. 1 is a block diagram showing the configuration of a programmable logic integrated circuit 1 according to a first embodiment of the present invention. The programmable logic integrated circuit 1 of this embodiment includes a variable resistance element 10, a switch cell array 20 including the variable resistance element 10, a read/write control wiring 30 for the variable resistance element 10, a logic element 40, and a first circuit. 50 and a second circuit 60. Further, the read/write control wiring 30 is connected to one end of the first circuit 50, the read/write control wiring 30 is connected to one end of the second circuit 60, the switch cell array 20 is connected to the other end of the first circuit 50, and the logic The input/output terminal of the element 40 is connected to the other end of the second circuit 60. Further, when reading or writing from the variable resistance element 10 in the first mode, the first circuit 50 transmits a signal between the read/write control wiring 30 and the switch cell array 20, and the second circuit 60 transmits a signal between the read/write control wiring 30 and the switch cell array 20. No signals are transmitted between the input and output terminals of the logic element 40. Furthermore, during application operation in the second mode, the first circuit 50 does not transmit signals between the read/write control wiring 30 and the switch cell array 20, and the second circuit 60 transmits signals between the read/write control wiring 30 and the logic element 40. Transmits signals between output terminals.

The programmable logic integrated circuit 1 according to the first embodiment has been described above.
In the programmable logic integrated circuit 1, the read/write control wiring 30 used for reading and writing the variable resistance element 10 in the first mode is also used as a wiring resource as a connection element during application operation. This embodiment has a disadvantage that data in the configuration memory cannot be verified in the background during the second mode, as in Patent Document 1. However, in this embodiment, data reliability can be improved by using the resistance change switch 70 with high error tolerance.
Therefore, the programmable logic integrated circuit 1 becomes a highly reliable circuit that has many wiring resources as connection elements while maintaining a small chip area.

<Second embodiment>
FIG. 2 is a block diagram showing the configuration of a programmable logic integrated circuit 1 according to a second embodiment of the present invention. The programmable logic integrated circuit 1 of this embodiment includes a programmable logic core 21, a configuration circuit 22, a general-purpose port 23, and a configuration port 24.

The programmable logic core 21 includes a resistance change switch 70. The resistance change switch 70 connects or disconnects wires to each other based on configuration information of the logic circuit. This enables configuration and reconfiguration of the logic of the programmable logic core 21. The programmable logic core 21 inputs input data from the general-purpose port 23 to a logic circuit configured based on configuration information, and outputs a logical operation result to the general-purpose port 23.

The configuration circuit 22 receives a signal including configuration information input from the configuration port 24, outputs a control signal to the programmable logic core 21, and inputs and outputs data. When writing to the resistance change switch 70, the configuration circuit 22 writes input data D to the resistance change switch 70 at address A by setting the write enable signal WE to a high level. When reading from the resistance change switch 70, the configuration circuit 22 receives the data output Q as data read from the resistance change switch 70 at address A by setting the read enable signal RE to a high level. During application operation, the configuration circuit 22 sets the application enable signal AE to a high level, so that the programmable logic core 21 inputs the input data from the general-purpose port 23 to the logic circuit, and sends the logical operation result to the general-purpose port 23. Output.

FIG. 3 is a block diagram showing the configuration of the programmable logic core 21 of the programmable logic integrated circuit 1 of this embodiment. The programmable logic core 21 includes a control circuit 211 , a column driver 212 , a row driver 213 , a column selection circuit 214 , a row selection circuit 215 , a readout circuit 216 , and a logic cell 217 .
In FIG. 3, as an example of the configuration of the programmable logic core 21, 4×2 logic cells 217 are arranged in a matrix.

The programmable logic core 21 further includes a global column selection line group GCSEL0, GCSEL1 extending in the column direction, a row selection line group RSEL0, RSEL1, RSEL2, RSEL3 extending in the row direction, and wiring PH0, PH1 extending in the column direction. and wirings PV0, PV1, PV2, PV3, PB0, PB1, PB2, and PB3 extending in the row direction.
The programmable logic core 21 further includes wirings WX0, WX1, WX2, and WX3 as connection elements extending in the row direction.

First, the connection relationship between the control circuit 211 and each circuit component will be explained. The control circuit 211 receives an address A, a data input D, a write enable signal WE, a read enable signal RE, and an application enable signal AE as input signals, and outputs a data output Q. Control circuit 211 outputs an address signal to column selection circuit 214 and row selection circuit 215 based on address A. The control circuit 211 outputs a driver setting signal for writing input data to the column driver 212 and the row driver 213 when the write enable signal WE is at a high level.

When the read enable signal RE is at a high level, the control circuit 211 outputs a driver setting signal for reading to the column driver 212 and the row driver 213, and outputs a read circuit control signal to the read circuit 216. The control circuit 211 then receives the data output IQ from the readout circuit 216 and outputs the data output Q to the outside.

Next, the connection relationship of each circuit component will be explained. The column selection circuit 214 selects a desired global column selection line (GCSEL0[0] or GCSEL0[1]) based on the address signal. Further, the column selection circuit 214 outputs a decode signal for selecting the wiring PH to the column driver 212. The row selection circuit 215 selects a desired row selection line (RSEL0 or RSEL1) based on the address signal. Furthermore, the row selection circuit 215 outputs a decode signal for selecting the wirings PV and PB to the row driver 213.

The column driver 212 supplies a write voltage or a read voltage to the switch cells via wirings PH0 and PH1. The row driver 213 supplies a write voltage or a read voltage to the switch cells via wirings PV0, PV1, PV2, and PV3. The row driver 213 supplies a write voltage via wirings PB0, PB1, PB2, and PB3. The row driver 213 connects a selected one of the wirings PB0, PB1, PB2, and PB3 to the wiring PB.
The readout circuit 216 senses the resistance state of the switch cell via the wiring PB.

Next, the connection relationship of the logic cells 217 will be explained. The logic cell LC00 includes a global column selection line group GCSEL0, a row selection line group RSEL0, a wiring PH0 extending in the column direction, a wiring PV0 extending in the row direction, a wiring PB0, a wiring WY0, and a wiring WX0. Connecting. Further, in the logic cells LC10, LC20, LC30, LC01, LC11, LC21, and LC31, wirings corresponding to each matrix are connected to each other in the same way as in the logic cell LC00.

FIG. 4 is a schematic diagram showing the configuration of the logic cell 217 of the programmable logic integrated circuit 1 of this embodiment. The logic cell 217 includes a plurality of switch cell arrays 20 and a plurality of logic elements 40. FIG. 4 illustrates a case where the logic cell 217 includes one switch cell and one logic element 40. The logic cell 217 in FIG. 4 further includes a column selection subcircuit 80, a row selection subcircuit 90, and an input/output circuit 100.

The logic cell 217 in FIG. 4 further includes global column selection lines GCSEL0[0] and GCSEL0[1] extending in the column direction, column selection lines CSEL0 and CSEL1 extending in the column direction, and row selection lines extending in the row direction. It includes lines RSEL0 and RSEL1, a wiring PH extending in the column direction, wiring PV and PB extending in the row direction, and WX0[0] extending in the row direction.

The logic cell 217 in FIG. 4 further includes a group of N vertical lines (N is an integer of 2 or more) extending in the column direction, and a group of M horizontal lines (M is an integer of 2 or more) extending in the row direction. has a group. FIG. 4 illustrates two horizontal lines HL0 and HL1 extending in the row direction, two vertical lines VL0 and VL1 extending in the column direction, and two vertical lines BL0 and BL1 extending in the column direction. There is.

The switch cell array 20 is provided at the intersection of a vertical line and a horizontal line, and has a maximum of N×M switch cells that switch between connecting and disconnecting the vertical line and the horizontal line. FIG. 4 shows an example of the configuration of the switch cell array 20, which includes switch cells SC00, SC01, SC10, and SC11 arranged at each intersection of a vertical line and a horizontal line. Switch cells SC00, SC01, SC10, and SC11 each include first resistance change switches U00, U01, U10, and U11, second resistance change switches L00, L01, L10, and L11, and NMOS transistors N00, N01, N10, and N11. and.

The logic element 40 includes a plurality of input terminals, a plurality of input/output terminals, and various logic circuits such as look-up tables and flip-flops that perform desired logic operations. FIG. 4 illustrates two input terminals T0, T1 and three input/output terminals T2, T3, T4.

The column selection subcircuit 80 includes the first circuit 50 and NMOS (Negative-channel Metal Oxide Semiconductor) transistors NV0, NV1, NB0, and NB1 arranged in the row direction. The first circuit 50 of this embodiment includes an AND circuit.

The row selection subcircuit 90 includes NMOS transistors NH0 and NH1 arranged in the column direction.
The input/output circuit 100 includes a second circuit 60 and a plurality of tri-state buffers. The second circuit 60 of this embodiment includes a tri-state buffer.

Next, the connection relationship of the logic cells 217 will be explained. Vertical line VL0 is connected to wiring PV via NMOS transistor NV0. The gate of NMOS transistor NV0 is connected to column selection line CSEL0. Vertical line VL1 is connected to wiring PV via NMOS transistor NV1. The gate of NMOS transistor NV1 is connected to column selection line CSEL1. When the read/write signal RW is at a high level, the column selection circuit 214 drives the global column selection line (GCSEL0[0] or GCSEL0[1]) and uses the first circuit 50 to select the column selection line (CSEL0 or CSEL1). ) is set to high level, a desired NMOS transistor (NV0 or NV1) is made conductive, and the wiring PV and the vertical line (VL0 or VL1) are connected. The read/write signal RW may be, for example, the logical sum of the write enable signal WE and the read enable signal RE. The read/write signal RW may further be logically ANDed with a partially decoded address signal.

Horizontal line HL0 is connected to wiring PH via NMOS transistor NH0. The gate of NMOS transistor NH0 is connected to row selection line RSEL0. Horizontal line HL1 is connected to wiring PH via NMOS transistor NH1. The gate of NMOS transistor NH1 is connected to row selection line RSEL1. The row selection circuit 215 uses the row selection line (RSEL0 or RSEL1) to turn on a desired NMOS transistor (NH0 or NH1) and connects the wiring PH and the horizontal line (HL0 or HL1).

Bit line BL0 is connected to wiring PB via NMOS transistor NB0. The gate of NMOS transistor NB0 is connected to column selection line CSEL0. Bit line BL1 is connected to wiring PB via NMOS transistor NB1. The gate of NMOS transistor NB1 is connected to column selection line CSEL1. When the read/write signal RW is at a high level, the column selection circuit 214 drives the global column selection line (GCSEL0[0] or CSEL0[1]) and uses the first circuit 50 to select the column selection line (CSEL0 or CSEL1). ) is set to high level, a desired NMOS transistor (NB0 or NB1) is made conductive, and the wiring PB and the bit line (BL0 or BL1) are connected.

Next, the connection relationship of the logic elements 40 will be explained. Input terminal T0 of logic element 40 is connected to horizontal line HL0. Input terminal T1 of logic element 40 is connected to horizontal line HL1.

The input/output terminal T2 of the logic element 40 is connected to a pair of tri-state buffers of the second circuit 60. One of the pair of tri-state buffers transmits the signal of the global column selection line GCSEL0[0] to the input/output terminal T2 of the logic element 40 when the input enable signal IE0 is at a high level, and when the input enable signal IE0 is at a low level. At this time, the signal of the global column selection line GCSEL0[0] is not transmitted to the input/output terminal T2 of the logic element 40. When the output enable signal OE0 is at a high level, the other pair of tri-state buffers transmits the signal of the input/output terminal T2 of the logic element 40 to the global column selection line GCSEL0[0], and the output enable signal OE0 is at a low level. At this time, the signal of the input/output terminal T2 of the logic element 40 is not transmitted to the global column selection line GCSEL0[0].

The input/output terminal T3 of the logic element 40 is connected to a pair of tri-state buffers of the second circuit 60. One of the pair of tri-state buffers transmits the signal of the global column selection line GCSEL0[1] to the input/output terminal T3 of the logic element 40 when the input enable signal IE1 is at a high level, and when the input enable signal IE1 is at a low level. At this time, the signal of the global column selection line GCSEL0[1] is not transmitted to the input/output terminal T3 of the logic element 40. When the output enable signal OE1 is at a high level, the other pair of tri-state buffers transmits the signal of the input/output terminal T3 of the logic element 40 to the global column selection line GCSEL0[1], and the output enable signal OE1 is at a low level. At this time, the signal of the input/output terminal T3 of the logic element 40 is not transmitted to the global column selection line GCSEL0[1].

Input/output terminal T4 of logic element 40 is connected to a pair of tri-state buffers of input/output circuit 100. One of the pair of tri-state buffers transmits the signal on the wiring WX0[0] to the input/output terminal T4 of the logic element 40 when the input enable signal IE2 is at a high level, and when the input enable signal IE2 is at a low level, the signal on the wiring WX0[0] is transmitted to the input/output terminal T4 of the logic element 40. The signal of WX0[0] is not transmitted to the input/output terminal T4 of the logic element 40. The other of the pair of tri-state buffers transmits the signal of the input/output terminal T4 of the logic element 40 to the wiring WX0[0] when the output enable signal OE2 is at a high level, and when the output enable signal OE2 is at a low level, The signal of the input/output terminal T4 of the logic element 40 is not transmitted to the wiring WX0[0].

The input enable signals IE0, IE1, and IE2 may be, for example, the logical product of the application enable signal AE and a setting value that enables the input of the input/output terminal of the logic element 40.
The output enable signals OE0, OE1, and OE2 may be, for example, the logical product of the application enable signal AE and a setting value that enables the output of the input/output terminal of the logic element 40.
Note that the tri-state buffer may be composed of a high voltage transistor. In a configuration in which the global column selection line (GCSEL0[0] or GCSEL0[1]) is driven with a high voltage required for writing to the resistance change switch 70, it is recommended that the tristate buffer also be configured with a high voltage transistor. This is effective for avoiding destruction of the transistors forming the buffer.

Next, the connection relationship of switch cells will be explained. Here, switch cell SC00 will be explained as an example. The configurations of switch cell SC01, switch cell SC10, and switch cell SC11 are similar to switch cell SC00. The switch cell SC00 includes a first resistance change switch U00, a second resistance change switch L00, and an NMOS transistor N00.

One terminal of the first resistance change switch U00 is connected to the horizontal line HL0. The other terminal is connected to one terminal of the second resistance change switch L00, forming a shared node. The other terminal of the second resistance change switch L00 is connected to the vertical line VL0. The common node is connected to the source or drain of NMOS transistor N00, and the drain or source of NMOS transistor N00 is connected to bit line BL0. The gate of the NMOS transistor is connected to the row selection line RSEL0. The row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor N00 to connect the common node and the bit line BL0. The first resistance change switch U00 and the second resistance change switch L00 connected in series function as a three-terminal resistance change switch.

A variable resistance nonvolatile memory element used in a CBRAM (Conductive Bridge Random Access Memory) can be used as the first and second variable resistance switches U00 and L00. The memory element of the CBRAM can be a metal-bridged bipolar variable resistance element 10 shown in FIG. 5 in which an ion conductor is used for the variable resistance layer.

In the resistance change switch 70 using an ion conductor, when the second electrode 502 of the inactive electrode is grounded and a positive voltage is applied to the first electrode 501 of the active electrode, the metal of the active electrode becomes a metal ion and the ion conductive layer is It is dissolved in the variable resistance layer 503. The metal ions in the ion conductive layer become metal and precipitate in the ion conductive layer, and the deposited metal forms a metal bridge connecting the inert electrode and the active electrode. This metal bridge connects both electrodes and creates a low resistance state. On the other hand, when the inactive electrode is grounded in a low resistance state and a negative voltage is applied to the active electrode, the metal bridge is dissolved in the variable resistance layer 503 and a part of the metal bridge is cut. This breaks the connection between both electrodes, resulting in a high resistance state. To return from a high resistance state to a low resistance state, the inactive electrode may be grounded again and a positive voltage may be applied to the active electrode. Using the above-mentioned low resistance state and high resistance state, the resistance change switch 70 can realize an ON state and an OFF state of the switch.

Note that before the connection is made by metal bridge, a transient state occurs, such as the resistance between the two electrodes gradually decreasing and the capacitance between the electrodes changing, and eventually the two electrodes are connected. It becomes a low resistance state. Additionally, before the connection due to the metal bridge is broken, a transient state occurs, such as the resistance between the two electrodes gradually increasing and the capacitance between the electrodes changing, which ultimately causes the connection between the two electrodes to break. It breaks and becomes a high resistance state. It is also possible to provide an intermediate state between a low resistance state and a high resistance state using the above transient states.

Furthermore, a variable resistance nonvolatile memory element used in PRAM (Phase Change Random Access Memory), ReRAM (Resistance Random Access Memory), etc. can also be used for the first and second resistance change switches U00 and L00.

The first and second resistance change switches U00 and L00 have two resistance states: a low resistance state and a high resistance state. A low resistance state is defined as an ON state, and a high resistance state is defined as an OFF state. When the resistance change switch is in the ON state, a signal applied at a voltage level passes through the resistance change switch. On the other hand, when the resistance change switch is in the OFF state, the signal is cut off by the resistance change switch and does not pass through the resistance change switch.

Furthermore, the resistance states of the first and second resistance change switches U00 and L00 are associated with data 1 and 0 of the configuration information (referred to as data 1 and data 0, respectively), and the low resistance state is set to data 1 and the high resistance state is is defined as data 0.

The switch cell SC00 shown in FIG. 4 is realized by a switch cell having the configuration shown in the three-terminal resistance change switch 50A shown in FIG. The first electrode (corresponding to 511A) of the first resistance change switch U00 (corresponding to 510A) and the first electrode (corresponding to 521A) of the second resistance change switch L00 (corresponding to 520A) are connected, and the common node (53A ) is formed. That is, the first resistance change switch U00 and the second resistance change switch L00 have symmetrical polarities with respect to the common node.

Furthermore, the second electrode (corresponding to 512A) of the first resistance change switch U00 is connected to the horizontal line HL0. A second electrode (corresponding to 522A) of the second resistance change switch L00 is connected to the vertical line VL0.

The switch cell SC00 is turned ON when the first resistance change switch U00 and the second resistance change switch L00 are in the ON state, and is turned OFF when the first resistance change switch U00 and the second resistance change switch L00 are in the OFF state. do.

Note that the configuration shown in the three-terminal resistance change switch 50B shown in FIG. 7 can also be used. In this case, in writing to the switch cell described below, a voltage corresponding to the polarity of the resistance change switch may be set.

Next, a method of writing into the switch cell will be explained. The read/write signal RW is at a high level, and the first circuit 50 transmits the signal of the global column selection line (GCSEL0[0] or GCLSEL0[1]) to the column selection line (CSEL0 or CSEL1) of the switch cell. Here, an example will be described in which the switch cell SC00 is set from OFF to ON. First, the first resistance change switch U00 is set from the OFF state to the ON state. The column driver 212 applies a low voltage (VL) to the wiring PH. The row driver 213 applies a high voltage (VH) higher than the set voltage to the wiring PB. Then, the row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor NH0 and apply the low voltage VL to the horizontal line HL0. Column selection circuit 214 drives global column selection line GCSEL0[0], uses first circuit 50 to turn on NMOS transistor NB0, and applies high voltage VH to bit line BL0. The row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor N00 and apply the high voltage VH to the first electrode (common node) of the first resistance change switch U00. As a result, the first resistance change switch U00 is turned on.

Note that the row driver 213 may set the wiring PV to an intermediate voltage (VH+VL)/2 or high impedance. At this time, the column selection circuit 214 drives the global column selection line GCSEL0[0], uses the first circuit 50 to turn on the NMOS transistor NV0, and connects the wiring PV and the vertical line VL0. Since a voltage lower than the set voltage is applied to the second resistance switch L00, L00 remains in the OFF state and does not change.

Subsequently, the second resistance change switch L00 is set from the OFF state to the ON state. The row driver 213 applies a low voltage (VL) to the wiring PV, and applies a high voltage (VH) higher than the set voltage to the wiring PB. Then, the column selection circuit 214 uses the global column selection line GCSEL0[0] to conduct the NMOS transistors NV0 and NB0, and applies the low voltage VL to the vertical line VL0 and the high voltage VH to the bit line BL0. The row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor N00 and apply the high voltage VH to the first electrode (common node) of the second resistance change switch L00. As a result, the second resistance change switch L00 is turned on.

Note that the column driver 212 may set the wiring PH to an intermediate voltage (VH+VL)/2 or high impedance. At this time, the row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor NH0 to connect the wiring PH and the horizontal line HL0. A voltage lower than the set voltage is applied to the first resistance switch U00. U00 remains in the ON state and does not change.

By the above operation, the first resistance change switch U00 and the second resistance change switch L00 are set, and the switch cell SC00 is turned on.

The operation when the switch cell SC00 is reset from ON to OFF will be described next. The read/write signal RW is at a high level, and the first circuit 50 transmits the signal of the global column selection line (GCSEL0[0] or GCLSEL0[1]) to the column selection line (CSEL0 or CSEL1) of the switch cell. First, the first resistance change switch U00 is reset from the ON state to the OFF state. The column driver 212 applies a high voltage (VH) higher than the reset voltage to the wiring PH. The row driver 213 applies a low voltage (VL) to the wiring PB. Then, the row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor NH0 and apply the high voltage VH to the horizontal line HL0. The column selection circuit 214 drives the global column selection line GCSEL0[0], uses the first circuit 50 to turn on the NMOS transistor NB0, and applies the low voltage VL to the bit line BL0. The row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor N00 and apply the low voltage VL to the first electrode (common node) of the first resistance change switch U00. As a result, the first resistance change switch U00 is turned off.

Note that the row driver 213 may set the wiring PV to an intermediate voltage (VH+VL)/2 or high impedance. At this time, the column selection circuit 214 drives the global column selection line GCSEL0[0], uses the first circuit 50 to turn on the NMOS transistor NV0, and connects the wiring PV and the vertical line VL0. Since a voltage lower than the reset voltage is applied to the second resistance change switch L00, L00 remains in the ON state and does not change.

Subsequently, the second resistance change switch L00 is reset from the ON state to the OFF state. The row driver 213 applies a high voltage (VH) higher than the reset voltage to the wiring PV and a low voltage (VL) to the wiring PB. Then, the column selection circuit 214 uses the global column selection line GCSEL0[0] to conduct the NMOS transistors NV0 and NB0, and applies the high voltage VH to the vertical line VL0 and the high voltage VL to the bit line BL0. The row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor N00 and apply the low voltage VL to the first electrode (common node) of the second resistance change switch L00. As a result, the second resistance change switch L00 is turned off.

Note that the column driver 212 may set the wiring PH to an intermediate voltage (VH+VL)/2 or high impedance. At this time, the row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor NH0 to connect the wiring PH and the horizontal line HL0. A voltage lower than the reset voltage is applied to the first resistance switch U00. U00 remains in the OFF state and does not change.

By the above operation, the first resistance change switch U00 and the second resistance change switch L00 are reset, and the switch cell SC00 is turned OFF.

Next, a method for reading out the switch cell will be explained. The read/write signal RW is at a high level, and the first circuit 50 transmits the signal of the global column selection line (GCSEL0[0] or GCLSEL0[1]) to the column selection line (CSEL0 or CSEL1) of the switch cell. Here, a method for reading out a switch cell will be described using an example of reading out the state of the switch cell SC00. First, the resistance state of the first resistance change switch U00 is read. For this purpose, the column driver 212 applies a low voltage (VL) to the wiring PH. The read circuit 216 applies a sense voltage VS to the wiring PB. The row driver 213 makes the wiring PV high impedance. Then, the row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor NH0 and apply the low voltage VL to the horizontal line HL0. The column selection circuit 214 drives the global column selection line GCSEL0[0], uses the first circuit 50 to turn on the NMOS transistor NB0, and applies the sense voltage VS to the bit line BL0. The row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor N00 and apply the sense voltage VS to the first electrode (common node) of the first resistance change switch U00. As a result, a sense current flows depending on the resistance state of the first resistance change switch U00.

For example, the readout circuit 216 converts the sense current into a voltage and then compares it with a reference voltage to determine the resistance state of the first resistance change switch U00. When the resistance value is smaller than a predetermined value, data 1 is output as output data IQ, and when it is larger than the predetermined value, data 0 is output as output data IQ.

Subsequently, the resistance state of the second resistance change switch L00 is read. The row driver 213 applies a low voltage VL to the wiring PV. The read circuit 216 applies a sense voltage VS to the wiring PB. The column driver 212 makes the wiring PH high impedance. Then, the column selection circuit 214 drives the global column selection line GCSEL0[0], uses the first circuit 50 to conduct the NMOS transistors NV0 and NB0, applies the low voltage VL to the vertical line VL0, and applies the low voltage VL to the bit line BL0. Apply sense voltage VS. The row selection circuit 215 uses the row selection line RSEL0 to turn on the NMOS transistor N00 and apply the sense voltage VS to the first electrode (common node) of the second resistance change switch L00. As a result, a sense current flows depending on the resistance state of the second resistance change switch L00.

For example, the readout circuit 216 converts the sense current into a voltage and then compares it with a reference voltage to determine the resistance state of the second resistance change switch L00. When the resistance value is smaller than a predetermined value, data 1 is output as output data IQ, and when it is larger than the predetermined value, data 0 is output as output data IQ.

Next, the application operation of the programmable logic integrated circuit 1 will be explained. When the application enable signal AE is at a high level and the input enable signals IE0, IE1, and IE2 are, for example, the AND of the application enable signal AE and the setting value that enables the input of the input/output terminal of the logic element 40. , the corresponding tri-state buffer transmits the signal of the global column selection line (GCSEL0[0] or GCSEL0[1]) and the wiring WX0[0] to the logic element 40. In addition, if the output enable signals OE0, OE1, and OE2 are, for example, the logical product of the application enable signal AE and a setting value that enables the output of the input/output terminal of the logic element 40, the corresponding tri-state buffer transmits the signal of the input/output terminal of the logic element 40 to the global column selection line (GCSEL0[0] or GCSEL0[1]) or the wiring WX0[0].

The column selection circuit 214 puts the global column selection lines (GCSEL0[0] and GCSEL0[1]) into a high impedance state. Furthermore, global column selection lines (GCSEL[0] and GCSEL[1]) that are not used as connection elements may be set to a low level. Whether or not each global wiring is used as a connection element may be stored in a setting memory.

The read/write signal RW is at a low level, and the first circuit 50 does not transmit the signal of the global column selection line (GCSEL0[0] or GCLSEL0[1]) to the column selection line (CSEL0 or CSEL1) of the switch cell. , set the column selection line to low level. As a result, the NMOS transistors NV0 and NV1 in the column selection subcircuit 80 become non-conductive, and the wiring PV is electrically disconnected from the vertical lines VL0 and VL1. Further, the NMOS transistors NB0 and NB1 in the column selection subcircuit 80 become non-conductive, and the wiring PB is electrically disconnected from the bit lines BL0 and BL1.

The row selection circuit 215 sets the row selection lines RSEL0 and RSEL1 to low level. As a result, the NMOS transistors NH0 and NH1 in the row selection subcircuit 90 become non-conductive, and the wiring PH is electrically disconnected from the horizontal lines HL0 and HL1. Further, NMOS transistors N00, N01, N10, and N11 become non-conductive.

The logic cell 217 transmits the input signals input to the vertical lines VL0 and VL1 to the logic element 40 via the horizontal lines HL0 and HL1 depending on the conduction state/non-conduction state of the switch cell. Furthermore, the logic cell 217 uses the input/output circuit 100 to input signals from the global column selection line (GCSEL0[0] or GCSEL0[1]) and the wiring WX to the logic element 40. The logic element 40 performs a desired logical operation and outputs the result to the global column selection line (GCSEL0[0] or GCSEL0[1]) or the wiring WX via the input/output circuit 100.

As described above, in the programmable logic integrated circuit 1, the read/write control wiring 30 used for reading and writing the variable resistance element 10 during read/write in the first mode is also used as a wiring resource as a connection element during application operation. ing. This embodiment has a disadvantage that data in the configuration memory cannot be verified in the background during the second mode, as in Patent Document 1. However, in this embodiment, data reliability can be improved by using a resistance change switch with high error tolerance.

Therefore, according to this embodiment, it is possible to provide a highly reliable logic integrated circuit that has many wiring resources as connection elements while maintaining a small chip area.

Although the programmable logic core 21 of this embodiment is configured so that the global column selection line (GCSEL0[0] or GCSEL0[1]) can be used as the read/write control wiring 30 during application, this is not the case. .
For example, the global row selection line (RSEL0 or RSEL1) may also be used as the read/write control wiring 30 during application. At this time, the first circuit 50 including an AND gate may be added to the row selection sub-circuit 90.
Furthermore, a driver line may also be used as the read/write control wiring 30 during application. At this time, the NMOS transistors in the column selection subcircuit 80 and the row selection subcircuit 90 may be used as the first circuit 50.

<Third embodiment>
FIG. 8 is a block diagram showing the configuration of the programmable logic core 21 according to the third embodiment of the present invention. The programmable logic core 21 of this embodiment includes a control circuit 211, a column driver 212, a row driver 213, a column selection circuit 214, a row selection circuit 215, a readout circuit 216, a logic cell 217, a switch SW0, Equipped with SW1.

The programmable logic core 21 of this embodiment differs from the programmable logic core 21 of the second embodiment in that the global column selection line groups GCSEL0 and GCSEL1 are divided by switches SW0 and SW1. The rest is the same as the programmable logic core 21 of the second embodiment, so the explanation of the overlapping parts will be omitted.

The switch SW0 receives a logical sum signal of the write enable signal WE and the read enable signal RE, and when the signal is at a high level, the switch SW0 becomes conductive, and the global column selection line group GCSEL0 is electrically divided by the switch SW0. Not done.
The switch SW0 receives a logical sum signal of the write enable signal WE and the read enable signal RE, and when the signal is at a low level, the switch SW0 becomes non-conductive, and the global column selection line group GCSEL0 is electrically disconnected by the switch SW0. be divided. Thus, for example, when global column selection line GCSEL0 is used for signal routing between logic cells LC00 and LC10 and signal routing between logic cells LC20 and LC30, the routing can be performed without interfering with each other.
The switch SW1, like the switch SW0, divides or undivides the global column selection line group GCSEL1.
For the switches SW0 and SW1, for example, NMOS transistors or the like can be used.
The programmable logic core 21 of this embodiment divides the global column selection line groups GCSEL0 and GCSEL1 to limit routing between neighboring logic cells 217 during application, increasing available wiring resources and increasing wiring resources. The parasitic capacitance of can be reduced.

Therefore, according to this embodiment, it is possible to provide a highly reliable logic integrated circuit that has many wiring resources as connection elements while maintaining a small chip area.

<Related technology>
Here, a logic integrated circuit 1 using technology related to the present invention will be described with reference to the drawings. In the following description, descriptions of structures and functions similar to those of the logic integrated circuits of the embodiments of the present invention described above will be omitted.

FIG. 9 is a block diagram showing the configuration of the programmable logic core 21 of the logic integrated circuit 1 using technology related to the present invention. Logic integrated circuit 1 is a programmable logic integrated circuit. The programmable logic core 21 includes a control circuit 211 , a column driver 212 , a row driver 213 , a column selection circuit 214 , a row selection circuit 215 , a readout circuit 216 , and a logic cell 217 .

The programmable logic core 21 is characterized in that the global column selection line group GCSEL0, GCSEL1 of the programmable logic core 21 of the second embodiment is separated into a column selection line group CSEL0, CSEL1 and a wiring group WY0, WY1. This is different from the programmable logic core 21 of the second embodiment. The rest is the same as the programmable logic core 21 of the second embodiment, so the explanation of the overlapping parts will be omitted.

FIG. 10 is a schematic diagram showing the configuration of the logic cell 217 of the programmable logic integrated circuit 1 using technology related to the present invention. FIG. 10 includes a plurality of switch cell arrays 20, one logic element 40, a column selection subcircuit 80, a row selection subcircuit 90, and an input/output circuit 100.

The logic cell 217 in FIG. 10 further includes column selection lines CSEL0 and CSEL1 extending in the column direction, row selection lines RSEL0 and RSEL1 extending in the row direction, wiring PH extending in the column direction, and It includes wirings PV and PB, WY0[0] and WY0[1] extending in the column direction, and WX0[0] extending in the row direction.

The logic cell 217 in FIG. 10 further includes a group of N vertical lines (N is an integer of 2 or more) extending in the column direction, and a group of M horizontal lines (M is an integer of 2 or more) extending in the row direction. has a group. FIG. 10 illustrates two horizontal lines HL0 and HL1 extending in the row direction, two vertical lines VL0 and VL1 extending in the column direction, and two vertical lines BL0 and BL1 extending in the column direction. There is.

In the programmable logic core 21 using the technology related to the present invention, the global column selection line group GCSEL0, GCSEL1 of the programmable logic core 21 of the second embodiment is connected to the column selection line group CSEL0, CSEL1 and the wirings WY0, WY1. The separated and related column selection subcircuit 80 and connection relationships are different from the programmable logic core 21 of the second embodiment. The rest is the same as the programmable logic core 21 of the second embodiment, so the explanation of the overlapping parts will be omitted.

Column selection subcircuit 80 includes NMOS transistors NV0, NV1, NB0, and NB1 arranged in the row direction.

Next, the connection relationship of the logic cells 217 will be explained. Vertical line VL0 is connected to wiring PV via NMOS transistor NV0. The gate of NMOS transistor NV0 is connected to column selection line CSEL0. Vertical line VL1 is connected to wiring PV via NMOS transistor NV1. The gate of NMOS transistor NV1 is connected to column selection line CSEL1. The column selection circuit 214 uses a column selection line (GCSEL0[0] or CSEL0[1]) to conduct a desired NMOS transistor (NV0 or NV1) and connects the wiring PV and the vertical line (VL0 or VL1). .

Next, the connection relationship of the logic elements 40 will be explained. Input terminal T0 of logic element 40 is connected to horizontal line HL0. Input terminal T1 of logic element 40 is connected to horizontal line HL1.

The input/output terminal T2 of the logic element 40 is connected to a pair of tri-state buffers of the input/output circuit 100. One of the pair of tri-state buffers transmits the signal on the wiring WY0[0] to the input/output terminal T2 of the logic element 40 when the input enable signal IE0 is at a high level, and when the input enable signal IE0 is at a low level, the signal on the wiring WY0[0] is transmitted to the input/output terminal T2 of the logic element 40. The signal of WY0[0] is not transmitted to the input/output terminal T2 of the logic element 40. The other pair of tri-state buffers transmits the signal of the input/output terminal T2 of the logic element 40 to the wiring WY0[0] when the output enable signal OE0 is at a high level, and when the output enable signal OE0 is at a low level, The signal of the input/output terminal T2 of the logic element 40 is not transmitted to the wiring WY0[0].

The input/output terminal T3 of the logic element 40 is connected to a pair of tri-state buffers of the input/output circuit 100. One of the pair of tri-state buffers transmits the signal on the wiring WY0[1] to the input/output terminal T3 of the logic element 40 when the input enable signal IE1 is at a high level, and when the input enable signal IE1 is at a low level, the signal on the wiring WY0[1] is transmitted to the input/output terminal T3 of the logic element 40. The signal of WY0[1] is not transmitted to the input/output terminal T3 of the logic element 40. The other pair of tri-state buffers transmits the signal of the input/output terminal T3 of the logic element 40 to the wiring WY0[1] when the output enable signal OE1 is at a high level, and when the output enable signal OE1 is at a low level, The signal of the input/output terminal T3 of the logic element 40 is not transmitted to the wiring WY0[1].

Input/output terminal T4 of logic element 40 is connected to a pair of tri-state buffers of input/output circuit 100. One of the pair of tri-state buffers transmits the signal on the wiring WX0[0] to the input/output terminal T4 of the logic element 40 when the input enable signal IE2 is at a high level, and when the input enable signal IE2 is at a low level, the signal on the wiring WX0[0] is transmitted to the input/output terminal T4 of the logic element 40. The signal of WX0[0] is not transmitted to the input/output terminal T4 of the logic element 40. The other of the pair of tri-state buffers transmits the signal of the input/output terminal T4 of the logic element 40 to the wiring WX0[0] when the output enable signal OE2 is at a high level, and when the output enable signal OE2 is at a low level, The signal of the input/output terminal T4 of the logic element 40 is not transmitted to the wiring WX0[0].

In the programmable logic core 21 of the programmable logic integrated circuit 1 using the technology related to the present invention, the wiring GCSEL0 and GCSEL1 are connected to the column selection line group CSEL0 and CSEL1 and the wiring WY0 and WY1 compared to the second embodiment. Separated.

For example, the programmable logic integrated circuit 1 according to the first to third embodiments of the present invention has a smaller chip area than the programmable logic integrated circuit 1 using the technology related to the present invention, and can be used as a connection element. A highly reliable logic integrated circuit with many wiring resources can be provided.
Specifically, in the programmable logic integrated circuit 1 using the technology related to the present invention, as shown in FIG. 9, the wirings CSEL0 and WY0 are separated. On the other hand, in the programmable logic integrated circuit 1 according to the first to third embodiments of the present invention, as shown in FIG. 3, the wiring GCSEL0 (read/write control wiring) serves as both the wiring CSEL0 and the wiring WY0. .
As a result, the area occupied by the wiring in the programmable logic integrated circuit 1 according to the first to third embodiments of the present invention is approximately half of the area occupied by the wiring in the programmable logic integrated circuit 1 using the technology related to the present invention. Become. Further, when the chip area is constant, the programmable logic integrated circuit 1 according to the first to third embodiments of the present invention requires more wiring than the programmable logic integrated circuit 1 using the technology related to the present invention. can be placed. Such an effect can be obtained by using the wiring GCSEL0 in a time-division manner. Specifically, the programmable logic integrated circuit 1 includes a first circuit 50 and a second circuit 60. It is only necessary to operate the second circuit 60.

The present invention is not limited to the embodiments described above, and various modifications can be made within the scope of the invention described in the claims, and these are also included within the scope of the present invention.

A programmable logic integrated circuit 1 with a minimum configuration according to an embodiment of the present invention will be described.
As shown in FIG. 11, the programmable logic integrated circuit 1 with the minimum configuration according to the embodiment of the present invention includes a switch cell array 20 including a variable resistance element, read/write control wiring 30 for the variable resistance element, and a logic element 40. It includes a first circuit 50 and a second circuit 60.
The read/write control wiring 30 is connected to a first terminal of the first circuit 50 and a first terminal of the second circuit 60. Switch cell array 20 is connected to the second terminal of first circuit 50 . Logic element 40 is connected to a second terminal of second circuit 60 . In the first mode, the first circuit 50 transmits a signal between the read/write control wiring 30 and the switch cell array 20. Furthermore, in the first mode, the second circuit 60 does not transmit signals between the read/write control wiring 30 and the logic element 40 . Furthermore, in the second mode, the first circuit 50 does not transmit signals between the read/write control wiring 30 and the switch cell array 20. Further, in the second mode, the second circuit 60 transmits a signal between the read/write control wiring 30 and the logic element 40.
According to this programmable logic integrated circuit 1, many wiring lines can be arranged while keeping the chip area small.

Note that the order of the processing in the embodiment of the present invention may be changed as long as appropriate processing is performed.

Although the embodiments of the present invention have been described, the programmable logic integrated circuit 1 and other control devices described above may have a computer device inside. The above-described processing steps are stored in a computer-readable recording medium in the form of a program, and the above-mentioned processing is performed by reading and executing this program by the computer. A specific example of a computer is shown below.
FIG. 12 is a schematic block diagram showing the configuration of a computer according to at least one embodiment.
The computer 5 includes a CPU 6, a main memory 7, a storage 8, and an interface 9, as shown in FIG.
For example, each of the programmable logic integrated circuit 1 and other control devices described above is implemented in the computer 5. The operations of each processing section described above are stored in the storage 8 in the form of a program. The CPU 6 reads the program from the storage 8, expands it to the main memory 7, and executes the above processing according to the program. Further, the CPU 6 reserves storage areas corresponding to each of the above-mentioned storage units in the main memory 7 according to the program.

Examples of the storage 8 include HDD (Hard Disk Drive), SSD (Solid State Drive), magnetic disk, magneto-optical disk, CD-ROM (Compact Disc Read Only Memory), and DVD-ROM (Digital Versatile D). isc Read Only Memory) , semiconductor memory, etc. Storage 8 may be an internal medium directly connected to the bus of computer 5, or may be an external medium connected to computer 5 via interface 9 or a communication line. Furthermore, when this program is distributed to the computer 5 via a communication line, the computer 5 that receives the program may develop the program in the main memory 7 and execute the above processing. In at least one embodiment, storage 8 is a non-transitory tangible storage medium.

Further, the program may realize some of the functions described above. Further, the program may be a so-called difference file (difference program), which is a file that can realize the above-described functions in combination with a program already recorded in the computer device.

Although several embodiments of the invention have been described, these embodiments are examples and do not limit the scope of the invention. Various additions, omissions, substitutions, and changes may be made to these embodiments without departing from the gist of the invention.

This application claims priority based on Japanese Patent Application No. 2019-068910 filed on March 29, 2019, and the entire disclosure thereof is incorporated herein.

According to each aspect of the present invention, it is possible to arrange many wiring lines while keeping the chip area of the programmable logic integrated circuit small.

1...Programmable logic integrated circuit 5...Computer 6...CPU
7... Main memory 8... Storage 9... Interface 10... Resistance change element 20... Switch cell array 21... Programmable logic core 22... Configuration circuit 23... General purpose port 24 ...Configuration port 30...Read/write control wiring 40...Logic element 50...First circuit 50A, 50B...3-terminal resistance change switch 53A...Common node 60...Second Circuit 70... Resistance change switch 80... Column selection subcircuit 90... Row selection subcircuit 100... Input/output circuit 211... Control circuit 212... Column driver 213... Row driver 214 Column selection circuit 215 Row selection circuit 216 Readout circuit 217 Logic cells 501, 511A, 521A First electrode 502, 512A, 522A Second electrode 503...・Resistance change layer 510A...First resistance change switch 520A...Second resistance change switch

Claims (7)

a switch cell array including a resistance change element;
read/write control wiring for the variable resistance element;
logic element and
a first circuit;
a second circuit;
a column selection circuit;
Global column selection line and
Equipped with
The read/write control wiring is connected to a first terminal of the first circuit and a first terminal of the second circuit,
the switch cell array is connected to a second terminal of the first circuit;
the logic element is connected to a second terminal of the second circuit;
During the first mode,
The first circuit transmits a signal between the read/write control wiring and the switch cell array,
The second circuit does not transmit a signal between the read/write control wiring and the logic element,
During the second mode,
The first circuit does not transmit a signal between the read/write control wiring and the switch cell array,
The second circuit transmits a signal between the read/write control wiring and the logic element ,
The read/write control wiring includes the global column selection line,
The column selection circuit is connected to the global column selection line,
In the first mode,
The column selection circuit puts the desired global column selection line in a state where it can transmit a signal,
During the second mode,
The column selection circuit makes the global column selection line high impedance,
The first circuit includes an AND gate,
An input terminal of the AND gate is connected to the global column selection line and a wiring through which a read/write signal is propagated,
The output terminal of the AND gate is connected to a column selection line.
Logic integrated circuit. The second circuit includes a first tri-state buffer and a second tri-state buffer,
The input terminal of the first tri-state buffer is connected to a wiring through which an input enable signal is propagated and a wiring through which a global column selection signal is propagated,
an output terminal of the first tri-state buffer is connected to the logic element;
an input terminal of the second tri-state buffer is connected to a wiring through which an output enable signal is propagated and the logic element;
an output terminal of the second tri-state buffer is connected to a wiring through which the global column selection signal is propagated;
Logic integrated circuit according to claim 1 . The first tri-state buffer and the second tri-state buffer include high-voltage transistors,
The logic integrated circuit according to claim 2 . a switch capable of electrically dividing the read/write control wiring;
Equipped with
In the first mode,
The switch does not divide the read/write control wiring,
During the second mode,
the switch electrically divides the read/write control wiring;
The logic integrated circuit according to any one of claims 1 to 3 . a row selection circuit;
global row selection line,
Equipped with
The read/write control wiring includes a global row selection line,
The row selection circuit is connected to the global row selection line,
In the first mode,
The row selection circuit puts the desired global row selection line in a state where it can transmit a signal,
During the second mode,
The row selection circuit makes the global row selection line high impedance.
The logic integrated circuit according to any one of claims 1 to 4 . driver circuit;
driver wire and
Equipped with
The read/write control wiring includes the driver line,
the driver circuit is connected to the driver line,
In the first mode,
The driver circuit puts the desired driver line in a state where it can transmit a signal,
During the second mode,
the driver circuit makes the driver line high impedance;
The logic integrated circuit according to any one of claims 1 to 5 . A switch cell array including a resistance change element, read/write control wiring for the resistance change element, a logic element, a first circuit, a second circuit, a column selection circuit, and a global column selection line, A write control wiring is connected to a first terminal of the first circuit and a first terminal of the second circuit, the switch cell array is connected to a second terminal of the first circuit, and the logic element The read/write control wiring is connected to a second terminal of the second circuit, the read/write control wiring includes the global column selection line, the column selection circuit is connected to the global column selection line, and the first circuit includes an AND gate. The input terminal of the AND gate is connected to the global column selection line and a wiring through which a read/write signal is propagated, and the output terminal of the AND gate is controlled by a logic integrated circuit connected to the column selection line. A method,
During the first mode,
transmitting a signal between the read/write control wiring and the switch cell array by the first circuit;
In the first mode,
The second circuit does not transmit a signal between the read/write control wiring and the logic element;
During the second mode,
The first circuit does not transmit a signal between the read/write control wiring and the switch cell array;
During the second mode,
transmitting a signal between the read/write control wiring and the logic element by the second circuit;
In the first mode,
placing a desired global column selection line in a state in which a signal can be transmitted by the column selection circuit;
During the second mode,
making the global column selection line high impedance by the column selection circuit;
A control method using a logic integrated circuit including.

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