KR19980082523A - Row decoder device and method thereof for semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low decoder device and a method of a semiconductor memory device. TECHNICAL FIELD The present invention relates to a low-order decoder device and a method of a semiconductor memory device. The design area of the semiconductor memory device is reduced, and the word-line is turned on immediately after receiving the low-address signal. It is faster.

Description

Row decoder device and method thereof for semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low decoder device and a method thereof of a semiconductor memory device. In particular, a single main decoder device having a global connection is commonly connected to each sub decoder and the sub decoder is controlled by a low address signal, thereby reducing design area and word. The present invention relates to a row decoder device of a semiconductor memory device and a method thereof for shortening a line turn-on time.

In general, when an external lath signal is enabled, an address signal is input to perform a row decoder operation. The row decoder for driving a word line includes a main decoder that receives a precharge and an address signal, and a sub decoder that operates on the output signal of the main decoder to enable the word line.

FIG. 1 is a circuit diagram illustrating a conventional row decoder device, in which a first gate transistor decoder precharge signal is applied and connected between a power supply voltage terminal Vcc and a first node N1. And a main decoder 10 connected between the first node N1 and a ground voltage terminal Vss, a gate connected to a second node N2, and a power supply voltage terminal Vcc, and the first node. 2nd PMOS transistor MP2 connected between N1, the 1st inverter IV1 connected between the said 1st node N1, and the 2nd node N2, and the said 1st, 1st The sub decoder 20 receives potentials on two nodes N2 as two inputs and selectively selects first, second, third, and fourth word lines.

The main decoder 10 is connected in series between the first node N1 and the ground voltage terminal Vss, and the first, second, and third to which the row address signals AX32, AX54, and AX76 are applied as gates, respectively. It consists of NMOS type transistors MN1, MN2, and MN3.

The sub decoder 20 includes a fourth NMOS transistor MN4 connected with a reference voltage Vxg as a gate and connected between the second node N2 and a gate terminal of an eighth NMOS transistor MN8. An eighth NMOS transistor MN8 having a gate connected to a source terminal of the fourth NMOS transistor MN4 and connected between a first word line boosting signal input terminal and a first word line connection terminal; A ninth NMOS transistor MN9 connected to the first node N1 and connected between the first word line connection terminal and a ground voltage terminal Vss, and the reference voltage Vxg is applied to a gate; A fifth NMOS transistor MN5 connected between the second node N2 and a gate terminal of the tenth NMOS transistor MN10, and a gate thereof are connected to a source terminal of the fifth NMOS transistor MN5. Second word line boosting signal input And a tenth NMOS transistor MN10 connected between the second word line connection terminal and a gate connected to the first node N1, and between the second word line connection terminal and the ground voltage terminal Vss. A sixth yen connected between an eleventh NMOS transistor MN11 connected and a reference voltage Vxg applied to a gate, and connected between the second node N2 and a gate terminal of a twelfth NMOS transistor MN12 A MOS transistor MN6 and a twelfth NMOS transistor whose gate is connected to a source terminal of the sixth NMOS transistor MN6 and is connected between a third word line boosting signal input terminal and a third word line connection terminal; A MN12, a thirteenth NMOS transistor MN13 connected to the first node N1 and connected between the third word line connection terminal and a ground voltage terminal Vss, and the reference to the gate; The voltage Vxg is applied and the first A seventh NMOS transistor MN7 connected between a two node N2 and a gate terminal of the fourteenth NMOS transistor MN14, and a gate thereof is connected to a source terminal of the seventh NMOS transistor MN7, A fourteenth NMOS transistor MN14 connected between a four word line boosting signal input terminal and a fourth word line connecting terminal, and a gate thereof is connected to the first node N1, and the fourth word line connecting terminal is grounded; The 15th NMOS transistor MN15 is connected between the voltage terminals Vss.

First, when the low decoder precharge signal / DX is applied, the first PMOS transistor MP1 is turned on and the first node N1 is precharged high. Therefore, at this time, the word line is not selected and is in a standby state in which a row address signal according to the enable of the las signal is input.

In this state, when the las signal is enabled and the low address signal is applied, the first node N1 is enabled at the low level and inverted by the first inverter IV1, so that the second node N2 is at the high level. Is switched to. The high potential on the second node N2 is the eighth, tenth, twelfth, and fourteenth yen by the fourth, fifth, sixth, and seventh NMOS transistors turned on by the reference voltage Vxg. Each of the MOS transistors MN14 is simultaneously transferred to the gate terminal, and the corresponding word line is selected by the relationship with the word line boosting signal PX.

As shown in FIG. 1, two NMOS transistors connected in series at the front end of each word line cause the total area of the chip to increase.

FIG. 2 is a block diagram of a conventional decoder for 256K memory. In the case of a 256K memory cell array which is most commonly used in DRAM, 64 row decoders 30 for driving 256 word lines and 256 word lines are shown. The device is shown as a block diagram.

In this case, one row decoder 30 is configured to selectively drive four word lines.

Each of the 64 row decoders 30 includes a main decoder 10 and a sub decoder 20 of FIG. 1.

However, in the conventional row decoder apparatus having such a structure, 64 row decoders are required to control 256 word lines in the case of a 256K memory cell array. That is, 64 main decoders and 64 sub decoders are required, and since the number of MOS transistors constituting the sub decoder increases, the design area increases, the overall area of the chip increases, and the word address signal is applied to the main decoder. It will take time for it to be enabled. That is, the word line is turned on after the row address signal is applied.

In summary, the ROH decoder device having the conventional configuration has a problem in that the design area is increased and the turn-on time of the word line is slowed.

Accordingly, the present invention has been devised to solve the above problems, and includes a single main decoder device, which is commonly connected to a plurality of sub decoders, and controls a sub decoder by a row address signal, thereby reducing design area and turning on word lines. It is an object of the present invention to provide a decoder apparatus and a method for speeding up time.

1 is a row decoder circuit diagram according to the prior art;

2 is a row decoder block diagram for a 256K memory in accordance with the prior art;

3 is a row decoder circuit diagram according to an embodiment of the present invention;

4 is a row decoder block diagram for a 256K memory in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: Main decoder 20, 50, 70: Sub decoder

30: Roo Decoder 40, 60: Global Judecoder

PA1 ~ PX4: Word line boosting signal

Vxg: Reference voltage

/ DX: Roo decoder precharge signal

The present invention for achieving the above object is controlled by a predetermined signal to output a global signal;

And a plurality of sub decoders that simultaneously receive the global signals of the main decoder and deliver them to each word line through a MOS transistor controlled by a predetermined signal.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a low decoder circuit diagram according to an embodiment of the present invention. In order to reduce layout, a global main decoder 40 commonly connected to 64 sub decoder 50 input terminals in the case of a 256K memory cell array, and the global main decoder The decoder 40 includes a sub decoder 50 connected to an output terminal for selecting a corresponding word line.

The global main decoder 40 includes a third PMOS transistor MP3 connected to a gate decoder precharge signal and connected between a power supply voltage terminal Vcc and a third node N3, and the gate to the gate. A 16th NMOS transistor MN16 is connected between the third node N3 and the ground voltage terminal Vss and a gate is connected to the fourth node N4, and a decoder precharge signal is applied. A fourth PMOS transistor MP4 connected between Vcc and the third node N3, and a second inverter IV2 connected between the third node N3 and the fourth node N4. And the seventeenth NMOS transistor MN17 connected with the reference voltage Vxg as a gate and connected between the fourth node N4 and the gate terminal of the eighteenth NMOS transistor MN18, A word line boosting signal connected to a source terminal of the seventeenth NMOS transistor MN17; (PX) An eighteenth NMOS transistor MN18 connected between an input terminal and an output terminal of the global main decoder 40, and a gate thereof are connected to the third node N3, and the output terminal of the global main decoder 40 is connected. And the nineteenth NMOS transistor MN19 connected between the ground voltage terminal Vss and the ground voltage terminal Vss.

The sub decoder 50 is connected in series between the output terminal of the global main decoder 40 and the fifth node N5, and the fifth and fifth sub-decoder 50 are provided with predetermined row address signals AX76, AX54, and AX32, respectively. The sixth and seventh PMOS transistors MP5, MP6, and MP7 and a predetermined address signal AX10 are commonly applied to the gate, and the fifth node N5 and the first, second, third, and fourth electrodes are commonly applied. The eighth, ninth, tenth, and eleventh PMOS transistors MP8, MP9, MP10, and MP11 are respectively connected between word line connection terminals.

Referring to the operation of the row decoder device having the above-described configuration, when the row level decoder decoder precharge signal is input, the third PMOS transistor MP3 is turned on and the power supply voltage is transferred to the third node N3. . Accordingly, the eighteenth NMOS transistor MN18 is turned on and the nineteenth NMOS transistor MN19 is turned on so that a low level potential is output to the global main decoder output terminal and transferred to the input terminal of the sub decoder 50. do. At this time, the word line is not selected and is in a standby state.

When the high level low decoder precharge signal is applied in the standby state, the 16th NMOS transistor MN16 is turned on to output a ground voltage on the third node N3, and the 18th NMOS transistor MN18 is output. ) Is turned on and a high level potential is output to the global main decoder output terminal due to a potential difference from the word line boosting signal PX. The high output potential is transmitted to the sub decoder input terminal to wait.

In this state, the ROH address signal for controlling the sub decoder is inputted to the gate terminal of the fifth, sixth, seventh, eighth, ninth, tenth, and eleventh PMOS transistors at about the same time, thereby waiting for the sub decoder input terminal. The high level potential is transferred to the first, second, third, and fourth word lines to enable the word lines. Note that not all word lines, that is, the first, second, third, and fourth word lines are enabled, but the corresponding word lines are selected by controlling the potential of the word line boosting signal PX.

Hereinafter, a conventional decoder decoder device shown in FIG. 1 and a receiver decoder device of the present invention shown in FIG. 3 will be described.

In the conventional ROH decoder device, since the ROH address signal is input to the main decoder, the turn-on time of the word line is generated after the ROH address signal is input. For example, 64 row decoders, that is, 64 main decoders and 64 sub decoders are required, which increases the design area of the main decoder unit and increases the number of MOS transistors located in front of each word line, thereby increasing the overall chip size. Done.

On the other hand, in the anti-invention shown in FIG. 3, since there is only one global main decoder corresponding to the conventional main decoder, the design area is further reduced, and the number of MOS transistors located in front of each conventional word line is reduced to two. As a result, the design margin can be very large.

In addition, the sub-decoder consists of only a few MOS transistors that transmit a signal to enable the word line, which simplifies the circuit. The word line is turned on with the input of the address by being controlled by the row address signal. You can benefit from faster time.

FIG. 4 is a row decoder block diagram of a 256K memory according to an embodiment of the present invention, which includes 256 word lines connected to 256K memory cell blocks and 64 sub decoders for controlling each of the 256 word lines by four. 70 and one global main decoder 60 to control the 64 sub decoders 70 at the same time.

In the description of the present invention, the main decoder is defined as including a word line driver.

When the present invention described above is implemented in a row decoder device of a semiconductor memory device, a single word line driver existing for each word line is possible, so that the design area is reduced, and an operation is performed after an address is applied to a conventional main decoder. Since the word line is turned on immediately after receiving the address from the sub decoder, the turn-on time of the word line is increased.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (8)

In a semiconductor memory device, Separating the loo decoder into one main decoder and a plurality of sub decoders, The global signal of the main decoder is applied to each input terminal of the sub decoder in common, A row decoder method of a semiconductor memory device, characterized in that the word line is selected through a MOS transistor of a sub decoder controlled by a predetermined signal. The method of claim 1, And the main decoder is not controlled by a row address signal but by a predetermined signal such as a row decoder precharge signal and a word line boosting signal. The method of claim 1, And the sub decoder is controlled by a row address signal. A main decoder operated by a precharge signal and configured to include a sub wordline driver; A wordline connected to the cell, And a pass transistor formed between the sub word line driver and the word line and controlled by a decoded address. The method of claim 4, wherein And the main decoder is not controlled by a row address signal. The method of claim 4, wherein And the main decoder generates a global signal by two MOS transistors connected in series between a word line boosting signal input terminal and a ground voltage terminal. The method of claim 4, wherein The main decoder includes first and second MOS transistors connected in series with gate decoder pre-autonomous signals, respectively, as a gate between a power supply voltage terminal and a ground voltage terminal; A third MOS transistor, in which the first and second MOS transistor output signals are inverted and applied to a gate and connected between a power supply voltage terminal and the first and second MOS transistor output terminals; An inverter connected between the third MOS transistor drain terminal and a gate terminal; A fourth MOS transistor connected to a gate between the inverter output terminal and the fifth MOS transistor gate terminal by a reference voltage; A fifth MOS transistor having a gate connected to the fourth MOS transistor source terminal and connected between a word line boosting signal input terminal and a global signal output terminal; And a sixth MOS transistor having a gate connected to the inverter input terminal and connected between a global signal output terminal and a ground voltage terminal. The method of claim 4, wherein And the pass transistor is a PMOS transistor.