KR102424935B1 - Pulse signal generating apparatus - Google Patents

Abstract

The present invention discloses an apparatus for generating a pulse signal. A pulse signal generating apparatus according to a preferred embodiment of the present invention enables to easily adjust an interval between an on pulse and an off pulse, thereby receiving an on/off pulse signal from the pulse signal generating apparatus and driving an internal switching element. It is possible to allow the device to freely adjust the width of the power pulse. Due to this configuration, the pulse power supply including the pulse signal generating device of the present invention can provide a power pulse of a very short width, which could not be implemented in the prior art, to the load side.

Description

Pulse signal generating apparatus

The present invention relates to an apparatus for generating a pulse signal, and more particularly, to an apparatus for generating a pulse signal that can be used in a pulse power supply.

In general, a high voltage pulse power supply device refers to a device that supplies high voltage pulse power to loads such as various test equipment and plasma generators (PSII, etc.).

1A is a diagram showing a schematic structure of a general high voltage pulse power supply device. Referring to FIG. 1A , the high voltage pulse power supply controls the power supply unit 10 , the switching unit 20 connected between the power supply unit 10 and the load 40 , and the power supply unit 10 and the switching unit 20 . and a controller 30 , the controller 30 includes a charging control circuit 31 for controlling the power supply unit 10 and a switching control circuit 32 for controlling the switching unit 20 .

The power supply unit 10 rectifies the input power to charge high voltage DC power to a plurality of capacitors connected in series with each other. By temporarily discharging a high voltage pulse to the load 40 side, and when the switching unit 20 is turned off, the discharged capacitors are charged again.

Through this process, the high voltage pulse power is supplied to the load 40 , and the pulse width and repetition rate of the high voltage pulse power are controlled by controlling the switching unit 20 .

On the other hand, in recent years, various demands for the power pulse supplied from the pulse power supply to the load side are increasing. That is, various electronic devices that require power pulses having various pulse widths are on the rise, and in particular, power pulses capable of outputting power pulses having a significantly shorter pulse width than the power pulse widths output from conventional pulse power devices are increasing. Demand for pulsed power supplies is increasing.

However, according to the prior art, as shown in FIG. 1b , the width of the power pulse (V _{pulse_output} ) output from the power supply device is a switching control circuit to turn on the switches included in the switching unit 20 . It could not be smaller than the on pulse (Pulse ON) output in (32). Accordingly, for various applications requiring a power pulse of a very short width, there is a limit in that the required power pulse cannot be supplied.

In order to solve the problems of the prior art, it is urgent to develop a pulse signal generator capable of controlling the gate driving circuit included in the switching unit 20 by outputting a very short on/off pulse corresponding to a desired power pulse width. the current situation.

The problem to be solved by the present invention is to provide a pulse signal generator that generates and outputs on-pulse and off-pulse signals with short intervals, whereby a pulse power supply device receives short-interval on-pulse and off-pulse signals input from the pulse signal generator to be driven by , and as a result, the pulse power supply device can output a power pulse having a short pulse width as desired by the user.

A pulse signal generating apparatus according to a preferred embodiment of the present invention for solving the above problems is a pulse signal generating apparatus for outputting on-pulse and off-pulse signals, and a pulse width control signal for adjusting an interval between on-pulse and off-pulse a pulse width control unit that outputs a frequency controller for outputting a pulse period control signal for controlling the periods of the on pulse and the off pulse; a pulse signal generator for outputting first and second signals generated according to the pulse width control signal and the pulse period control signal to a high level input terminal and a low level input terminal of the signal amplifier, respectively; and a signal amplifying unit receiving the difference signal between the first signal and the second signal as an input signal and amplifying the signal amplifying unit to output on-pulse and off-pulse signals having an on-pulse width shorter than a width of the off-pulse.

In addition, the second signal has a delay and a longer pulse width than the first signal, and the signal amplifier subtracts the second signal from the first signal, so that the on pulse width is shorter than the off pulse width. It can accept pulsed and off-pulse signals as input signals.

In addition, the pulse signal generator, a first switching element (U1) connected between the first node (N1) and Vcc; a second switching element (U2) connected between the first node and the ground; a fifth resistor connected between Vcc and the source of the first switching element; a second capacitor (C2) connected between the first node and ground; a first current driver (U3) having an input terminal connected to the first node and an output terminal connected to the fourth node; a third resistor coupled between the second node and the fourth node; a second resistor and a diode connected between the second node and the third node; a third capacitor (C3) connected between the third node and ground; a second current driver (U4) having an input terminal connected to the third node; and a first resistor connected between the first node and the second node.

In addition, the pulse signal generator, the first current driver outputs the first signal to the high level input terminal of the signal amplifier, and the second current driver outputs the second signal to the low level input terminal of the signal amplifier can

In addition, the second switching element may be turned on/off according to the pulse period control signal to adjust the generation period of the on pulse and off pulse signals.

In addition, the first switching element is implemented as a p-channel FET, the drain of the first switching element is connected to the first node, the source is connected to Vcc, and the pulse width control signal is the first switching element The pulse width control signal may be input to a gate of , and the pulse width control signal may be input at a voltage lower than a turn-on voltage of the first switching element, so that the first switching element operates as a resistor in a linear region.

In addition, when the pulse width control signal is input to the gate of the first switching element, the second capacitor is charged, and when the voltage charged in the second capacitor exceeds a threshold voltage of the first current driver, the second capacitor is charged. A first current driver outputs the first signal as a square wave voltage signal, the third capacitor is charged by the square wave voltage signal output from the first current driver, and the voltage charged in the third capacitor is the second current When the threshold voltage of the driver is exceeded, the second current driver may output the second signal, which is a square wave voltage signal.

In addition, the above-described pulse signal generating apparatus according to the preferred embodiment of the present invention may be included in the pulse power supply.

The pulse signal generating apparatus of the present invention allows the interval between the on pulse and the off pulse to be easily adjusted, so that the pulse power supply that receives the on/off pulse signal from the pulse signal generating apparatus and drives the internal switching element receives a power pulse The width can be freely adjusted.

Due to this configuration, the pulse power supply including the pulse signal generating device of the present invention can provide a power pulse of a very short width, which could not be implemented in the prior art, to the load side.

1A is a diagram showing the configuration of a general pulse power supply device according to the prior art.
1B is a diagram illustrating an on/off pulse waveform for controlling a pulse power supply device and a power pulse waveform output from the pulse power supply device according to the related art.
2 is a diagram illustrating an example of a pulse power supply device including a pulse signal generating device according to a preferred embodiment of the present invention.
3 is a diagram illustrating a detailed configuration of an apparatus for generating a pulse signal according to a preferred embodiment of the present invention.
4 is a waveform diagram illustrating waveforms of signals output from respective components of a pulse generating apparatus according to a preferred embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating an example of a pulse power supply device including a pulse signal generating device 300 according to a preferred embodiment of the present invention.

Referring to FIG. 2 , a pulse power supply device including a pulse signal generating device 300 according to a preferred embodiment of the present invention includes a pulse signal generating device 300 for generating and outputting an on/off pulse signal, and a pulse power generating device The power supply unit 100 for supplying power used in the and a power pulse generating module 200 for simultaneously turning on the switches included in the .

At this time, as shown in FIG. 1B , the switches included in the power pulse generating module 200 are turned on when an on pulse is input, and turned off when an off pulse is input. That is, the power pulse generating module 200 outputs a power pulse having a width equal to the time when the on pulse signal is input from the pulse signal generating device 300 and the time when the off pulse is input to the load side, and thus, the present invention is The width of the power pulse output from the power pulse generating module 200 is adjusted by adjusting the interval between the on pulse and the off pulse.

To this end, the pulse signal generating apparatus 300 of the present invention is characterized in that the width of the on pulse is shorter than the width of the off pulse when compared to the on/off pulse signal generally generated in the prior art, and in particular, , is characterized in that the width of the on-pulse is significantly shorter than the width of the off-pulse.

On the other hand, the power supply unit 100 and the power pulse generating module 200 can be implemented in various ways without limitation in the implementation method as long as they can provide the above-described functions, and are not limited to the structure shown in FIG. 2 .

Therefore, in the following, only the configuration of the pulse signal generating apparatus 300 according to the preferred embodiment of the present invention will be described in detail so as to focus on the core of the present invention.

3 is a diagram showing a detailed configuration of a pulse signal generating apparatus 300 according to a preferred embodiment of the present invention, and FIG. 4 is each component of the pulse signal generating apparatus 300 according to a preferred embodiment of the present invention. It is a waveform diagram showing the waveforms of signals output from

3 and 4, a pulse signal generating apparatus 300 according to a preferred embodiment of the present invention includes a pulse width controller 310, a frequency controller 320, a pulse signal generator 330, and signal amplification. It is configured to include a unit 340 .

First, the pulse width controller 310 outputs a pulse width control signal to the pulse signal generator 330 to adjust the interval between the on pulse and the off pulse output from the pulse signal generator 300 , and consequently, the pulse power It controls the width of the power pulse output from the device to the load side. In a preferred embodiment of the present invention, the pulse width controller 310 adjusts the interval between the on pulse and the off pulse and the width of the power pulse by adjusting the magnitude of the voltage output to the pulse signal generator 330 .

The frequency controller 320 outputs a pulse period control signal to the pulse signal generator 330 to control the generation period of the on pulse and the off pulse, thereby controlling the output period of the power pulse. In a preferred embodiment of the present invention, the frequency controller 320 adjusts the cycle of outputting a constant voltage signal to the pulse signal generator 330, thereby controlling the generation cycle of the on pulse and the OFF pulse and the generation cycle of the power pulse.

The pulse signal generator 330 generates an on pulse and an off pulse spaced apart from each other according to a pulse width control signal input from the pulse width controller 310 at a predetermined time period according to a pulse period control signal input from the frequency controller 320 . generated and output to the signal amplifier 340 .

The signal amplifier 340 amplifies the on pulse and the off pulse input from the pulse signal generator 330 and outputs the amplified output to the power pulse generator module 200 .

When describing the configuration of the pulse signal generator 330 in more detail, first, the first switching element U1, the second switching element U2, the second capacitor C2, and the first An input terminal of the current driver U3 and one end of the first resistor R1 are connected.

At this time, as shown in FIG. 3 , the first switching element U1 is implemented as a p-channel FET, a first node N1 is connected to the drain, and a fifth resistor R5 is connected to the source, Vcc is connected to the other end of the fifth resistor R5, the first capacitor C1 is connected between the gate and Vcc, and the output terminal of the pulse width controller 310 is connected to the gate, and output from the pulse width controller 310 The pulse width control signal is input to the gate of the first switching element U1.

In addition, the second switching element U2 is implemented as an n-channel FET, the drain is connected to the first node N1, the source is connected to the ground terminal, and the output terminal of the frequency control unit 320 is connected to the gate, It is turned on/off according to the pulse period control signal output from the frequency controller 320 .

Meanwhile, the other end of the first resistor R1, one end of the second resistor R2, one end of the third resistor R3, and the anode of the diode D1 are respectively connected to the second node N2.

The other end of the second resistor R2, the third capacitor C3, the cathode of the diode D1, and the input end of the second current driver U4 are respectively connected to the third node.

The fourth node is connected to the other end of the third resistor R3 , the output terminal of the first current driver U3 , and the high level input terminal (+ input terminal) of the signal amplifier 340 .

An operation process of the pulse signal generating apparatus 300 according to a preferred embodiment of the present invention will be described with reference to section (a) of FIG. 4 .

First, when a pulse width control signal for determining the pulse width is applied to the gate of the first switching element U1, a current flows from the V _cc voltage source through the first switching element U1 to charge the second capacitor C2. do.

At this time, the pulse width control signal is a constant DC voltage, and is constantly applied at a voltage lower than the threshold voltage at which the first switching element U1 is completely turned on, and at this time, the first switching element U1 is It operates in the linear region and operates like a resistor with a constant resistance value.

The voltage V _C2 charged in the second capacitor C2 becomes the voltage of the first node N1 while linearly increasing as shown in FIG. 4 , and is applied to the input terminal of the first current driver U3 and , when the charging voltage V _C2 of the second capacitor C2 exceeds the threshold voltage V _{th_U3} of the first current driver U3 , the current flows through the first current driver U3 and a voltage in the form of a square wave (V _{out_U3} ) is output, and this voltage V _{out_U3} is maintained while the charging voltage V _C2 of the second capacitor C2 exceeds the threshold voltage V _{th_U3} of the first current driver U3 .

If the DC voltage value applied to the gate of the first switching element U1 as the pulse width control signal is changed, the current flowing through the second capacitor C2 is changed, and accordingly, the second capacitor C2 is charged. As the slope of the voltage waveform is changed, the interval between the on pulse and the off pulse and the width of the power pulse are changed as will be described later.

On the other hand, when a square wave voltage V _{out_U3} is output from the output terminal of the first current driver U3 , a current flows through the third resistor R3 and the diode D1 through the third capacitor C3 and the third capacitor The voltage V _C3 starts to be charged to C3 , and the same voltage is applied as the input voltage V _{IN_U4} of the second current driver U4 .

When the input voltage V _{IN_U4} of the second current driver U4 exceeds the threshold voltage of the second current driver U4 , a current is passed through the second current driver U4 like the first current driver U3 . A square wave voltage (V _{out_U4} ) is output to the low level input terminal (− input terminal) of the signal amplifier 340 while flowing, and this voltage is the input voltage (V _{IN_U4} ) of the second current driver U4 is the second current It is maintained while exceeding the threshold voltage of driver U4.

During this process, when the time reaches the period of the pulse signal preset by the frequency controller 320, the frequency controller 320 outputs the pulse period control signal to the second switching element U2 to the second switching element U2 ) is turned on, and when the second switching element U2 is turned on, the voltage V _C2 stored in the second capacitor C2 is discharged through the second switching element U2 and the voltage stored in the second capacitor C2 is turned on. (V _C2 ) is rapidly decreased to 0, and thus, the triangular waveform of the storage voltage V _C2 of the second capacitor C2 is completed.

In addition, the input voltage of the first current driver U3 connected to the same node as the second capacitor C2 also abruptly decreases to 0, and accordingly, the output voltage of the first current driver U3 also rapidly decreases to 0. A square wave (V _{out_U3} ) as shown in is completed.

On the other hand, when the output voltage of the first current driver U3 drops to 0, the voltage V _C3 charged in the third capacitor C3 is converted into a series of the second resistor R2 and the third resistor R3. Due to the connected resistor, the third capacitor C3 is discharged relatively slowly than the charging time, and at this time, the discharged voltage is applied to the input terminal of the second current driver U4, and the discharged voltage is applied to the second current driver (U4). When it falls below the threshold voltage of U4), the output voltage of the second current driver U4 becomes 0, and the square wave V _{out_U4} is completed.

Here, as the third capacitor voltage V _C3 applied to the second current driver U4 is rapidly charged and slowly discharged, the voltage output from the second current driver U4 is output from the first current driver U3 It has a very small delay and a longer pulse width compared to the voltage.

Accordingly, the signal amplifier 340 is a second current driver that is a signal input from the output voltage V _{out_U3} of the first current driver U3 that is a signal input to the high level input terminal (+) to the low level input terminal (-). The signal V on/off1 obtained by subtracting the output voltage V _{out_U4} of (U4) becomes a signal V on _{/ off1} having a very short on pulse and a relatively long off pulse, and the signal amplifier 340 is The signal (V _on/off1 ) is received as an input signal and amplified, and the amplified signal (V _on/off2 ) is output to the power pulse generating module 200 to drive the switching elements inside the power pulse generating module 200 and , finally the power pulse (Pulse Out) is output to the load side.

Meanwhile, sections (b) and (c) of FIG. 4 describe a process of further reducing the width of the power pulse out. In order to further reduce the width of the power pulse (pulse out) than in the section (a) of FIG. 4 , the voltage value of the pulse width control signal output from the pulse width control unit 310 to the gate of the first switching element U1 is To further decrease the resistance value of the first switching element U1 is made larger.

Then, as in the section (b) of FIG. 4 , the slope of the voltage V _C2 charged in the second capacitor further decreases, and accordingly, the input voltage of the first current driver U3 increases the threshold voltage V _{th_U3} . The exceeding section becomes shorter, so that the width of the output voltage V _{out_U3} of the first current driver U3 becomes shorter. In proportion to this, the widths of the third capacitor charging voltage V _C3 and the output voltage V _{out_U4} of the second current driver U4 also become shorter.

Accordingly, the interval between the on pulse and the off pulse of the signal (V _on/off1 ) input to the signal amplifier 340 and the output signal (V _on/off2 ) of the signal amplifier 340 is also shortened in proportion to this, and the As a result, the width of the power pulse (Pulse Out) corresponding to the interval between the on pulse and the off pulse is proportionally shortened.

In the same manner, when the voltage value of the pulse width control signal output from the pulse width control unit 310 to the gate of the first switching element U1 is further reduced, as shown in section (c) of FIG. 4 , the pulse signal The interval between the on pulse and the off pulse output from the generating device 300 becomes shorter, and a power pulse having a shorter width may be obtained in proportion to this.

So far, with respect to the present invention, the preferred embodiments have been looked at. Those of ordinary skill in the art to which the present invention pertains will understand that the present invention may be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments are to be considered in an illustrative rather than a restrictive sense. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the scope equivalent thereto should be construed as being included in the present invention.

100: power unit
200: power pulse generation module
300: pulse signal generating device
310: pulse width control
320: frequency control unit
330: pulse signal generator
340: signal amplification unit

Claims (8)

delete A pulse signal generating device for outputting on-pulse and off-pulse signals, comprising:
a pulse width control unit outputting a pulse width control signal for adjusting an interval between the on pulse and the off pulse;
a frequency controller for outputting a pulse period control signal for controlling the periods of the on pulse and the off pulse; and
a pulse signal generator for outputting first and second signals generated according to the pulse width control signal and the pulse period control signal to a high level input terminal and a low level input terminal of the signal amplifier, respectively; and
and a signal amplifying unit for receiving and amplifying the difference signal between the first signal and the second signal as an input signal, and outputting on-pulse and off-pulse signals having an on-pulse width shorter than that of an off-pulse,
The second signal has a delay and a longer pulse width than the first signal,
The signal amplifying unit subtracts the second signal from the first signal, and receives an on-pulse signal and an off-pulse signal having an on-pulse width shorter than an off-pulse width as an input signal. The method of claim 2, wherein the pulse signal generator
a first switching element U1 connected between the first node N1 and Vcc;
a second switching element (U2) connected between the first node and the ground;
a fifth resistor connected between Vcc and the source of the first switching element;
a second capacitor (C2) connected between the first node and ground;
a first current driver (U3) having an input terminal connected to the first node and an output terminal connected to the fourth node;
a third resistor coupled between the second node and the fourth node;
a second resistor and a diode connected between the second node and the third node;
a third capacitor (C3) connected between the third node and ground;
a second current driver (U4) having an input terminal connected to the third node; and
and a first resistor connected between the first node and the second node. 4. The method of claim 3, wherein the pulse signal generator
The first current driver outputs the first signal to the high level input terminal of the signal amplifier, and the second current driver outputs the second signal to the low level input terminal of the signal amplifier. . 5. The method of claim 4,
The second switching element is turned on/off according to the pulse period control signal to control the generation period of the on pulse and off pulse signals. 6. The method of claim 5,
The first switching element is implemented as a p-channel FET,
A drain of the first switching element is connected to the first node, a source is connected to Vcc, and the pulse width control signal is input to a gate of the first switching element,
The pulse width control signal is input at a voltage lower than a turn-on voltage of the first switching element, so that the first switching element operates as a resistor in a linear region. 7. The method of claim 6,
When the pulse width control signal is input to the gate of the first switching element, the second capacitor is charged, and when the voltage charged in the second capacitor exceeds a threshold voltage of the first current driver, the first current a driver outputs the first signal, which is a square wave voltage signal,
When the third capacitor is charged by the square wave voltage signal output from the first current driver and the voltage charged in the third capacitor exceeds a threshold voltage of the second current driver, the second current driver generates a square wave voltage and outputting the second signal, which is a signal. A pulse power supply comprising the pulse signal generating device according to any one of claims 2 to 7.

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